JPH08242590A - Drive circuit for power converting apparatus - Google Patents

Abstract

PURPOSE: To miniaturize a transformer provided for insulation and reduce switching loss and stresses onto a switching element. CONSTITUTION: High frequency output from a signal source 4c is alternately applied to respective primary windings n11 and n12 of a drive transformer Tc during on-period and off-period of a low frequency square wave output from a signals source 4a. Output of the secondary winding n2 of the drive transformer Tc is rectified by diodes Dc1 and Dc2 and charged to capacitors Cc1 and Cc2 . By properly setting on-duty of a high frequency, the voltage at both the ends of the capacitors Cc1 and Cc2 is changed to high and low during on-period and off-period of a square wave from a signal source 4a. This high- and low- relation is compared with a comparator CP1 for obtaining signals for turning the switching element Q on and off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit of a power conversion device for driving a switching element used in a power conversion device for converting power to an input and outputting the power, such as an inverter circuit.

[0002]

2. Description of the Related Art Generally, a power conversion device such as an inverter circuit is provided with a switching element such as a transistor and a MOSFET, and the switching element is turned on / off by a control signal from a control circuit.
The control signal is applied to the switching element through the drive circuit so that the level of the control signal drives the switching element.

For example, the power conversion device shown in FIG.
Flyback type D that obtains AC from DC
The DC power supply E is stepped up (may be stepped down) using a C-DC converter, and the stepped up DC voltage is converted into the inverter circuit 2
Is configured to be converted into an alternating voltage. DC-D
C converter connects the series circuit of a primary winding n ₁ of the switching element Q ₀ and the transformer T ₀ such as a MOSFET to both ends of a DC power source E, 2 winding n ₂ of the transformer T ₀
A capacitor C ₀ is connected to both ends of the capacitor via a diode D ₀ . The primary winding n ₁ and the secondary winding n _{2 of the} transformer T ₀ are used with the polarities shown in the figure. When the switching element Q ₀ is turned on, energy is stored in the transformer T ₀ and the switching element Q ₀ is turned off. by charging the capacitor C ₀ through the diode D ₀ in energy released from the transformer T ₀ to time, it is possible to boost or step down the voltage to the voltage across the capacitor C ₀ with respect to the DC power source E. The switching element Q ₀ is turned on / off by the control circuit 3 which outputs a high frequency rectangular wave signal.

[0004] The inverter circuit 2 is intended to four switching elements Q ₁ to Q ₄ consisting MOSFET full bridge type in which bridge-connected switching elements of each respective two Q _1, Q ₂ and Q _3, Q _It has a configuration in which a pair of series circuits in which ₄ are respectively connected in series are connected between both ends of the capacitor C ₀ . The output of the inverter circuit 2 is taken from the output terminal t _1, t ₂ connected to a connection point between the switching elements Q ₁ to Q ₄ in series connected two switching elements Q _1, Q ₂ and Q _3, Q ₄ Be done. Further, the two switching elements Q ₁ , Q ₂ and Q ₃ , Q ₄ connected in series are turned on and off so as not to be turned on at the same time, and a pair of switching elements Q ₁ , Q ₄ or Q ₂ , Q _{3 are provided.} Are turned on at the same time. Therefore, the switching elements Q ₁ , Q
₄ is turned on at the same time, the switching element Q ₂ ,
By alternately generating the periods in which Q ₃ is simultaneously turned on, the polarities of the voltages generated at the output terminals t ₁ and t ₂ can be alternated.

A control circuit 4 for outputting a rectangular wave control signal is connected to the switching elements Q _{1 to} Q ₄ via drive circuits 5 _{1 to} 5 ₄ . The control circuit 4 includes a signal source 4a that outputs a rectangular wave and an inverting circuit 4b that inverts the rectangular wave output from the signal source 4a.
Is set to be lower than the switching frequency of the switching element Q ₀ in the DC-DC converter. The switching element Q _2, Q ₃ to when the switching element Q _1, Q ₄ is so turned off, the switching element Q _1, Q ₄ is driven a square wave output from the signal source 4a as a control signal, The switching elements Q ₂ and Q ₃ are driven with a signal obtained by inverting the rectangular wave output from the signal source 4a by the inverting circuit 4b as a control signal.

In the inverter circuit 2 having the above structure, since the switching elements Q _{1 to} Q ₄ are connected to the positive electrode side and the negative electrode side of the capacitor C ₀ respectively, the switching element Q is connected between the positive electrode side and the negative electrode side. The reference potentials of _{1 to} Q ₄ are different. For example, the switching element Q ₂ uses the negative electrode side of the capacitor C ₀ as the reference potential, but the switching element Q ₁ has the size of the load connected to the output terminals t ₁ and t ₂ and the switching elements Q _{1 to} Q ₄ . It fluctuates depending on on / off. Therefore, in the drive circuits 5 ₁ and 5 ₃ for the switching elements Q ₁ and Q ₃ connected to the positive electrode side of the capacitor C ₀ , it is necessary to insulate the control circuit 4 from the switching elements Q ₁ and Q _3. Become.

That is, each drive circuit 5 shown in FIG.
_1, the 5 _2, provided with a complementary connecting each pair of transistors Qa ₁ was, Qb _1, Qa _2, Qb _2, connect the base of each pair of transistors Qa _1, Qb _1, Qa _2, Qb ₂ in common Control signal is being input. Also, each pair of transistors Qa ₁ , Qb ₁ , Qa ₂ , Q
The emitter-collector series circuit of b ₂ is connected across the DC power source E. In the drive circuit 5 ₂ corresponding to the switching element Q ₂ , a resistor R is provided at the connection point between the emitters of the complementary-connected transistors Qa ₂ and Qb _2.
The gate of the switching element Q ₂ is connected via ₂ . In the drive circuit 5 ₁ corresponding to the switching element Q ₁ , the complementary-connected transistor Q ₁ is used.
A series circuit of the primary winding n ₁ of the drive transformer Ta and the capacitor Ca is connected between the connection point between the emitters of a ₁ and Qb ₁ and the negative electrode of the DC power supply E to connect the drive transformer Ta to
One end of the secondary winding n ₂ is connected to the gate of the switching element Q ₁ via the resistor R _1, and the other end of the secondary winding n ₂ is connected to the source of the switching element Q ₁ . That is, the switching element Q ₁ is insulated from the primary side of the drive transformer Ta via the drive transformer Ta.

In particular, as shown in FIG. 29, when the negative electrode of the DC power source E is on the ground side and the positive electrode of the capacitor C ₀ is on the ground side, as in the configuration of FIG. Therefore, the drive transformer Ta is required in all the drive circuits 5 _{1 to} 5 ₄ , which leads to further size increase. Therefore, for the purpose of downsizing, it is preferable to adopt the configuration of FIG. 27 as compared with the configuration of FIG. 29, but there is a problem that the size cannot be sufficiently reduced.

In order to solve such a problem, the structure disclosed in Japanese Patent Laid-Open No. 4-17575 is used (see FIG. 3).
0 See), the control circuit 4 in addition to the signal source 4a for outputting a rectangular wave of a low frequency by adding a signal source 4c for outputting a high frequency, the AND gate 4d ₁ ~4d ₄ in the low-frequency control signal
High frequency while AND gate 4d ₁
Pass the high frequency wave through 4d ₄ to drive transformer T
configuration through to a ₁₁ ~Ta ₁₄ have been considered.

The one shown in FIG. 30 drives an inverter circuit A in which two switching elements are connected in series, and the output to the switching element is two outputs. Further, the signal source 4a that outputs the low-frequency control signal is 2
An output is provided, and while one output is at H level, the other output is set at L level, and one output is at H level.
Both outputs are set to L level during the transition from the level period to the period in which the other output is H level. Each output of the signal source 4a is connected to AND gates 4d ₁ and 4d.
It is directly input to ₃ and AND gates 4d ₂ and 4d ₄
Is input after being inverted by the inversion circuits 4e ₂ and 4e ₄ . Here, the inverting circuits 4e ₂ and 4e ₄ are provided in order to accelerate the transition to the OFF state by applying a reverse bias to the switching element when the ON period of the switching element of the inverter circuit ends.

[0011] is connected a series circuit of a respective primary winding n ₁ is the transistor Qa ₁₁ ~Qa ₁₄ of each drive transformer Ta ₁₁ to Ta ₁₄ across the DC power source E. The secondary windings n ₂ of the drive transformers Ta _{11 to} Ta ₁₄ include resistors Ra _{11 to} Ra.
It is connected to each switching element of the inverter circuit 2 through a series circuit of ₁₄ and the diodes Da ₁₁ and Da ₁₄ . Drive transformer Ta ₁₁ of two by two to one switching element of the inverter circuit 2, than are associated with Ta ₁₂ and Ta _13, Ta _14, two drive transformers Ta ₁₁ corresponding to one of the switching elements, Ta ₁₂ and T
In a ₁₃ and Ta ₁₄ , the primary winding n ₁ and the secondary winding n ₂ have opposite polarities, and the secondary windings of the drive transformers Ta ₁₁ , Ta ₁₂ and Ta ₁₃ , Ta ₁₄ corresponding to one switching element. The series circuit of the winding n ₂ , the resistors Ra ₁₁ , Ra ₁₂ and Ra ₁₃ , Ra ₁₄ and the diodes Da ₁₁ , Da ₁₂ and Da ₁₃ , Da ₁₄ is connected in parallel. However, the diodes Da ₁₁ , Da ₁₂ and D of the series circuit connected in parallel are
a ₁₃ and Da ₁₄ are antiparallel.

The signal source 4a is provided on one of the primary windings n ₁ of the pair of drive transformers Ta ₁₁ , Ta ₁₂ and Ta ₁₃ , Ta ₁₄ corresponding to one switching element of the inverter circuit 2.
AND gates 4d ₁ and 4 to which the output of is input without being inverted
Transistors Qa ₁₁ and Q that are turned on / off by the output of d ₃
a ₁₃ is connected, and the other primary winding n ₁ is turned on / off by the outputs of AND gates 4d ₂ and 4d ₄ which are input by inverting the output of the signal source 4a by inverting circuits 4e ₂ and 4e _4. Transistors Qa ₁₂ and Qa ₁₄ are connected.

With the above structure, each transistor Qa ₁₁
The signal for turning on / off Qa ₁₄ is a signal obtained by modulating a high frequency signal with a low frequency control signal. Also, the signal source 4a
During a period in which the output of one of the above is at the H level, the transistors Qa ₁₁ and Qa ₁₃ are turned on and off, so that the switching element of the inverter circuit 2 is turned on during the on period of the transistors Qa ₁₁ and Qa ₁₃ . On the other hand, the signal source 4a
During the period in which the output of one of the above is at the L level, the transistors Qa ₁₂ and Qa ₁₄ are turned on / off, so that the switching element of the inverter circuit 2 is reverse biased during the on period of the transistors Qa ₁₂ and Qa _14. , Turn off the switching element faster. After all, like the complementary-connected transistors Qa ₁ and Qa _{2 in} the drive circuits 5 ₁ and 5 ₂ shown in FIG.
₁₁ , Qa ₁₂ and Qa ₁₃ , Qb ₁₄ also function complementarily to the switching elements of the inverter circuit 2.

[0014]

In the structure shown in FIG. 30, the signals transmitted between the primary side and the secondary side of the drive transformers Ta _{11 to} Ta ₁₄ are high-frequency intermittent signals at low frequencies. Therefore, high-frequency drive transformers Ta _{11 to} Ta ₁₄ can be used, and the size can be reduced. However, unless the current flowing to the secondary side of the drive transformers Ta _{11 to} Ta ₁₄ is made small, the primary side is discharged to the secondary side and the insulation cannot be maintained. Therefore, usually, the series resistance on the secondary side (that is, the DC resistance of the secondary windings n ₂ of the resistors Ra _{11 to} Ra ₁₄ and the drive transformers Ta _{11 to} Ta ₁₄ ) is set relatively large. However, when the series resistance on the secondary side is increased, the switching element (M
The time required for charging / discharging the gate-source capacitance of the switching element (OSFET) becomes long, the rise and fall of the switching element becomes slow, and the loss at the time of switching of the switching element becomes large, and stress to the switching element is increased. It grows up. Moreover, since the output impedance to the gate of the switching element is high, the switching element malfunctions due to the current flowing from the main circuit side of the switching element (the drain side if the switching element is a MOSFET, the collector side if the transistor is a switching element) to the control circuit 4 side. More likely to.

The present invention has been made in view of the above circumstances, and an object thereof is to downsize a transformer and control the switching element when insulation by the transformer is required between the switching element and the control side. It is an object of the present invention to provide a drive circuit of a power conversion device in which malfunctions are less likely to occur by reducing the switching loss and the stress on the switching element by making the rising and falling edges of the signal to be steep and further reducing the output impedance.

[0016]

The invention according to claim 1 is provided with at least one switching element, and is used in a power converter for converting and outputting power of a power supply by turning on / off the switching element. In a drive circuit for controlling to turn on and off, a means for switching and generating two types of high-frequency signals at a predetermined cycle, a drive transformer for electrically isolating each of the signals and transmitting it to a subsequent circuit, A pair of capacitors connected to the secondary side of the transformer through the rectifying means, a means for exchanging the magnitude relationship of the voltage across each capacitor according to the above signals, and a determination result of the magnitude relationship between the voltage across both capacitors. A binary output is generated accordingly, and means for driving the switching element by the binary output is provided.

According to a second aspect of the present invention, the two types of signals have different frequencies, and a resonance circuit having the frequency of each signal as a resonance frequency is inserted in the charging path to the drive transformer and each capacitor. It is characterized in that the magnitude relationship of the voltage across the capacitor is switched according to the frequency of the signal. According to a third aspect of the present invention, the two types of signals have different frequencies, and a low-pass filter and a high-pass filter having a cut-off frequency at an intermediate frequency between the frequencies of the signals are provided in the charging path to the drive transformer and the capacitors. One of the two is inserted, and the magnitude relationship of the voltage across each capacitor is switched according to the frequency of the signal.

According to a fourth aspect of the present invention, the drive transformer includes a plurality of secondary windings, and a pair of capacitors connected via a rectifying means and a magnitude relationship between the voltages across the capacitors according to the signals are determined. Generates a binary output according to the result of the replacement and the determination result of the magnitude relationship between the voltages across both capacitors,
Means for driving the switching element by the binary output.

The invention of claim 5 is characterized in that a filter circuit for stabilizing one of the voltages to be compared is provided at the input portion of the means for determining the magnitude relationship of the voltages across both capacitors. The invention of claim 6 is characterized in that the capacitors have different capacities. . The invention of claim 7 is characterized in that a delay circuit for delaying one voltage change to be compared is inserted in the input part of the means for judging the magnitude relation of the voltages across both capacitors.

The present invention according to claim 8 is used in a power conversion device which comprises at least one switching element and which converts and outputs electric power of a power supply by turning the switching element on and off to turn the switching element on and off. In the drive circuit controlled to the above, means for switching and generating two types of high-frequency signals at a predetermined cycle, a drive transformer for electrically insulating the above signals and transmitting them to the subsequent circuit, and a secondary side of the drive transformer. A pair of capacitors connected via rectifying means, a means for exchanging the magnitude relationship of the voltages across the capacitors according to the signals, and a binary output by comparing the difference between the voltages across the capacitors with a threshold value. However, a means for driving the switching element by the binary output is provided.

[0021]

According to the present invention, the two types of high frequency signals are passed through the drive transformer to insulate the switching element from the signal side, and the transformer transmits the high frequency. Therefore, a small one can be used. Further, since the two types of signals are charged so as to switch the magnitude relationship between the voltages across the pair of capacitors, and a binary signal is generated based on this magnitude relationship, the switching element can be turned on / off. Moreover, unlike the conventional configuration, the switching element is not connected to the secondary winding of the transformer through the resistor,
By generating a binary signal to drive the switching element, the rising and falling edges of the signal controlling the switching element can be made steep, and switching loss and stress on the switching element can be reduced. Moreover, since the output impedance for the switching element can be appropriately set as a circuit configuration, it is possible to reduce the sneak from the main circuit side controlled by the switching element and prevent malfunction.

According to the configuration of the inventions of claims 5 to 7, when comparing the magnitude relations of the voltages across both capacitors, it is possible to make a difference in the time change of the voltages to be compared, and as a result, It is possible to appropriately set the timing for turning on / off the switching element. That is, it is possible to turn on each other by using a plurality of switching elements.
When it is required to shift the off timing, it is possible to satisfy the requirement only by adjusting the secondary side of the drive transformer while keeping the signal on the primary side of the drive transformer in common.

According to the configuration of the invention of claim 8, since the binary signal is generated by comparing the voltage difference between both capacitors with a threshold value, the same operation as in claims 1 to 4 is achieved, and By properly setting the relationship between the difference between the voltage across the capacitor and the threshold value, the on / off timing of the switching element can be adjusted only by adjusting the secondary side of the drive transformer.

[0024]

【Example】

(Embodiment 1) The present invention is a drive circuit used in a power conversion circuit such as an inverter circuit, and the same configuration can be adopted regardless of the number of switching elements used in the power conversion circuit. In the description, a drive circuit for one switching element will be described. When there are a plurality of switching elements, a similar drive circuit may be expanded and used depending on the number.

As shown in FIG. 1, this embodiment uses a control circuit 4 similar to the conventional configuration shown in FIG. That is, the signal source 4a that outputs a low frequency rectangular wave and the signal source 4c that outputs a high frequency rectangular wave are used. The output of the signal source 4a is input to the AND gate 4d ₁ together with the output of the signal source 4c, and is inverted by the inverting circuit 4e ₁ and then input to the AND gate 4d ₂ . The transistors Qc ₁ and Qc ₂ are turned on / off by the outputs of the AND gates 4d ₁ and 4d ₂ . By the way, the drive transformer Tc used in the present embodiment has a center tap 1
Comprising a winding n _11, n _12, as well as serially connected to the primary winding n _11, the transistor Qc ₁ each end of n _12, the Qc ₂ collector, the center tap - the primary winding n _11, n ₁₂ - collectors of the transistors Qc _1, Qc ₂ - a series circuit of the emitter, is connected across the DC power source E.

On the other hand, one end of the secondary winding n ₂ of the drive transformer Tc is connected to a connection point of a series circuit of a pair of diodes Dc ₁ and Dc ₂ , and the other end is a pair of capacitors Cc ₁ and Cc.
₂ is connected to the connection point of the series circuit. Diode D
A series circuit of c ₁ and Dc _{2 and} a series circuit of capacitors Cc ₁ and Cc ₂ are connected in parallel, and a pair of resistors R
The series circuit of c ₁ and Rc ₂ is also connected in parallel. Therefore, the output of the secondary winding n ₂ of the drive transformer Tc is full-wave rectified by the diodes Dc ₁ and Dc ₂ , and the capacitor C
The voltage smoothed by the series circuit of c ₁ and Cc ₂ is applied to the resistor Rc ₁ ,
It means that it is applied to both ends of the series circuit of Rc ₂ . The potential at the midpoint of the series circuit of the capacitors Cc ₁ and Cc ₂ changes according to the direction of the electromotive force generated in the secondary winding n ₂ of the drive transformer Tc. Here, diodes Dc ₁ and Dc ₂ and capacitors Cc ₁ and C that are connected in series are
It is assumed that c ₂ and resistors Rc ₁ and Rc ₂ have the same specifications.

The connection point of the series circuit of the resistors Rc ₁ and Rc ₂ is connected to the non-inverting input terminal of the comparator CP ₁ , and the connection point of the series circuit of the capacitors Cc ₁ and Cc ₂ is connected to the inverting input terminal of the comparator CP _1. To be done. Therefore, the resistance R
The potential of the connection point of the series circuit of c ₁ and Rc ₂ and the potential of the connection point of the series circuit of the capacitors Cc ₁ and Cc ₂ are compared by the comparator CP ₁ . In addition, the comparator C
The output terminal of P ₁ is commonly connected to the bases of a pair of complementary connected transistors Qa and Qb, and is pulled up to the positive electrode side of the series circuit of the capacitors Cc ₁ and Cc ₂ by a resistor Rd. Also, both transistors Q
The collector-emitter series circuit of a and Qb is connected in parallel to the series circuit of capacitors Cc ₁ and Cc ₂ . With respect to the drive circuit 5 thus configured, the gate of the switching element (MOSFET) Q of the inverter circuit 2 is connected to the connection point between the emitters of both transistors Qa and Qb, and the source of the switching element Q is the capacitor Cc.
Connect to the negative electrode of the series circuit of ₁ and Cc ₂ .

Next, the operation will be described. As shown in FIG. 2B, the signal source 4a outputs a control signal that is a low-frequency rectangular wave that goes to H level in a predetermined cycle at predetermined intervals, and the signal source 4c outputs a control signal as shown in FIG. Continuously outputs a high frequency rectangular wave. Therefore, a high frequency is output from the AND gate 4d ₁ during the H level period of the control signal as shown in FIG. 2C, and a high frequency is output from the AND gate 4d ₂ during the L level period of the control signal as shown in FIG. 2D. High frequency is output to. The transistors Qc ₁ and Qc ₂ are turned on while the outputs of the AND gates 4d ₁ and 4d ₂ connected to their bases are at the H level.

[0029] Thus, during the on period of the transistor Qc ₁ is charged capacitor Cc ₁ through the diode Dc _1, transistor Qc ₁ capacitor Cc ₂ is charged through the diode Dc ₂ by stored energy of the drive transformer Tc and turned off . Where capacitor C
Compared to the charging energy of c ₁ is set high frequency on-duty output from the signal source 4c so that the charging energy of the capacitor Cc ₂ is small, the voltage across the capacitor Cc ₁ is the voltage across the capacitor Cc ₂ It is designed to be higher than. Similarly, the transistor Q
As for c ₂ , the capacitor Cc ₂ is charged through the diode Dc ₂ when turned on, and when the transistor Qc ₂ is turned off, the energy stored in the driving transformer Tc is stored in the diode Dc _2.
The capacitor Cc ₁ is discharged through c ₁ so that the capacitor Cc ₁ is charged. In this case, the voltage across the capacitor Cc ₂ becomes higher than the voltage across the capacitor Cc ₁ . That is, while the control signal is at the H level, the capacitor Cc ₁
Is higher than the voltage across the capacitor Cc ₂ ,
This relationship is reversed when the control signal is at L level.

Comparator CP₁Then the resistance Rc₁, Rc
₂Potential at the connection point and the capacitor Cc ₁, Cc₂Connection point
Compare with the potential of. Here, as described above,
Sensor Cc₁, Cc₂Is the control signal at the H level
Both capacitors Cc vary depending on whether it is L level or not.₁,
Cc₂Is the added value of the voltage across both terminals considered to be almost constant?
, Comparator CP₁The voltage applied to the non-inverting input terminal of
It becomes almost constant. On the other hand, the comparator CP₁Inverted input of
The voltage applied to the end is low when the control signal is at H level.
When the control signal is L level, it becomes high.
By this, the comparator CP₁Output is the control signal
It has the same waveform as the No. In short, the diode Dc₁, Dc
₂, Capacitor Cc₁, Cc₂, Resistance Rc₁, Rc₂,
Comparator CP₁Through the drive transformer Tc
You have taken out the high frequency collapse line. That
After that, the complementary connected transistors Qa, Q
b is the comparator CP₁By driving with the output of
Comparator CP₁Output is high level
The transistor Qa turns on and the switching element Q turns on.
And comparator CP₁Is in the L level period
Is turned on and the source of the switching element Q is
The charge due to the capacitance between the gates is removed and the switching element Q
Can be turned off rapidly. From the above explanation
As can be seen, the transistors Qa and Qb are the capacitors Cc.
₁, Cc₂The power source is the voltage across the series circuit of
Is isolated from the DC power source E by the dynamic transformer Tc
ing.

With the above configuration, the signal sources 4a and 4c
And the switching element Q are insulated from each other, and the drive transformer Tc used for insulation is configured to allow a small size to be used as the drive transformer Tc by transmitting a high frequency. Complementary connection of a pair of transistors Q
Since the driving is performed by using a and Qb, the switching element Q can be rapidly turned on / off, the switching loss is reduced, and the stress on the switching element Q is reduced. Further, by using the pair of transistors Qa and Qb that are connected in a complementary manner at the connection portion with the switching element Q, the output impedance with respect to the switching element Q is reduced, and current flows from the main circuit (drain side of the switching element Q). However, it has no other effect.

[0032] (Example 2) This example, as shown in FIG. 3, with having no center tap in the primary winding n ₁ as a drive transformer Tc, the primary winding n ₁ and the transistor Qc Is connected between both ends of the DC power source E, and the transistor Qc is driven by a signal which passes the outputs of the signal sources 4a and 4c through the exclusive OR circuit XOR. That is, the signal source 4a outputs a rectangular wave low-frequency control signal as shown in FIG. 4B, and the signal source 4c outputs the control signal of FIG.
When a high frequency signal as shown in (a) is continuously output, the output of the exclusive OR circuit XOR is as shown in FIG.
It becomes like (c). In short, the high frequency from the signal source 4c is output as it is while the control signal is at L level,
When the fish signal H is at H level, the signal source 4c outputs a signal which becomes H level during high frequency L level. The polarities of the primary winding n ₁ and the secondary winding n ₂ of the drive transformer Tc are set so that the capacitor Cc ₂ is charged during the ON period of the transistor Qc.

Therefore, if the ON period of the high frequency output from the signal source 4c is set shorter than the OFF period, the ON period of the switching element Qc becomes longer than the OFF period while the control signal is at H level. On the contrary, the ON period of the switching element Qc is shorter than the OFF period while the control signal is at the L level. Then, the switching element Qc
During the period when the on-duty of C is small (the period when the control signal is L level), the voltage across the capacitor C ₂ is
The voltage becomes higher than the voltage across _{1 and} the voltage across the capacitor C ₂ becomes lower than the voltage across the capacitor C ₁ while the control signal is at the H level. That is, the comparator CP ₁
Output becomes L level while the control signal is L level,
It becomes H level while the control signal is at H level. That is,
The switching element Q can be controlled by the same signal as the control signal. Other configurations and operations are the same as the first embodiment.
Is the same as

(Embodiment 3) In each of the above embodiments, the secondary winding n ₁ of the drive transformer Tc is one winding, but as shown in FIG. 5, the secondary windings n ₂₁ and n with a center tap are provided. ₂₂ may be provided. The center tap is commonly connected to one end having the same polarity of the secondary windings n ₂₁ and n ₂₂ divided into two. In this configuration, the output of the secondary winding n _21, n ₂₂ connect the diode Dc _1, Dc ₂ for full-wave rectification on each end of the secondary winding n _21, n _22, the center tap capacitor Cc ₁ , Cc ₂
Connect to the connection point of. Other configurations are the same as those of the first and second embodiments, and the switching circuit indicated by reference numeral 6 in FIG. 5 corresponds to the circuit indicated by the same reference numeral in FIGS. 1 and 3. However, when the primary windings n ₁₁ and n ₁₂ with center taps are used as shown in FIG. 1, the primary winding n ₁ of the drive transformer Tc shown in FIG. 5 is replaced with the configuration shown in FIG. To do. This point is the same in each of the following embodiments.

Also in the configuration of this embodiment, the period during which the capacitor Cc ₁ is charged from the secondary winding n ₂₁ of the driving transformer Tc through the diode Dc ₁ and the capacitor Cc ₁ is charged from the secondary winding n ₂₂ of the driving transformer Tc through the diode Dc _2. A period for charging Cc ₂ is provided, and both capacitors Cc ₁ and Cc
_A difference can be generated in the voltage between both ends of ₂ . Therefore, the output of the comparator CP ₁ can be inverted according to the control signal by reversing the magnitude relationship of the voltages across the capacitors Cc ₁ and Cc ₂ according to the H level and L level of the control signal. is there.

(Embodiment 4) In this embodiment, as shown in FIG. 6, the drive transformer Tc uses secondary windings n ₂₁ and n ₂₂ with center taps and is divided into two secondary windings. A center tap is commonly connected to the opposite ends of the lines n ₂₁ and n ₂₂ . Therefore, the two diodes Dc ₁ and Dc ₂
In each case, the drive transformer Tc side is used as an anode.

In this structure, the potential of the center tap is set to the reference potential, and the comparator CP ₁ uses the capacitor C.
Instead of comparing the potential at the connection point of c ₁ and Cc ₂ with the potential at the connection point of resistors Rc ₁ and Rc ₂ , each capacitor Cc
The potentials at the connection points of ₁ and Cc ₂ and the diodes Dc ₁ and Dc ₂ are compared. That is, the control signal is at H level or L
Depending on the level, the capacitor C seen from the center tap
The output of the comparator CP ₁ is inverted by utilizing the fact that the magnitude relation of the potentials at the ends of c ₁ and Cc ₂ is reversed. Other configurations and operations are similar to those of the third embodiment.

(Embodiment 5) In this embodiment, as shown in FIG. 7, two drive transformers Tc ₁ and Tc ₂ are used, and the primary winding of each drive transformer Tc ₁ and Tc ₂ is used. The n ₁ and the secondary winding n ₂ are connected to each other at one end having the same polarity. The other configuration is the same as that of the third embodiment and functions similarly to the third embodiment. When the same switching circuit as that of the first embodiment is used, the primary windings n ₁₁ and n ₁₂ with center taps are connected in parallel. The same applies to the sixth embodiment.

(Embodiment 6) In this embodiment, two drive transformers Tc ₁ and Tc ₂ are used as shown in FIG. 8, and the primary winding of each drive transformer Tc ₁ and Tc ₂ is used. n ₁ has one end having the same polarity connected to each other, and the secondary winding n ₂ has one end having the different polarity connected to each other. The other configuration is the same as that of the fourth embodiment and functions similarly to the fourth embodiment.

[0040] (Embodiment 7) In this embodiment, as shown in FIG. 9, there is a capacitor Cd connected in parallel to a series circuit of a capacitor Cc _1, Cc _2, the comparator CP ₁
In the capacitor Cc ₁ and Cc _2, the voltage compared with the voltage across the capacitors Cc ₁ and Cc _{2 and} the voltage supplied to the series circuit of the complementary connected transistors Qa and Qb are
It is stabilized by d. Other configurations and operations are similar to those of the first and second embodiments.

(Embodiment 8) This embodiment is shown in FIG.
As described above, in the configuration of the third embodiment,
Next winding n_{twenty one}, N_{twenty two}And each diode Dc₁, Dc₂Between
Each capacitor Cr₁, Cr₂And inductor Lr
₁, Lr₂Series resonance circuit consisting of 7₁, 7 ₂Insert
Each series resonance circuit 7₁, 7₂And diode Dc₁, Dc₂
Resistance Rr between the connection point₁, Rr₂Connect the series circuit of
It has a different configuration. In addition, the secondary winding n_{twenty one}, N_{twenty two}The center of
And resistance Rr₁, Rr₂Connection point and capacitor C
c₁, Dc₂Are connected to each other. For each series
Swing circuit 7₁, 7₂Are set to different resonance frequencies
It

Further, the signal source 4c outputs a high frequency having a frequency equal to the resonance frequency of each series resonance circuit 7 ₁ , 7 ₂ , and the control signal output from the signal source 4a is at H level or L level.
The output frequency of the signal source 4c can be switched according to the level. That is, a high frequency that is approximately equal to the resonance frequency of the series resonance circuit 7 ₁ is applied to the drive transformer Tc while the control signal is at the H level, the capacitor C ₁ is mainly charged, and the series resonance occurs while the control signal is at the L level. A high frequency approximately equal to the resonance frequency of the circuit 7 ₂ is given to the drive transformer Tc, and the capacitor C ₂ is mainly charged. Therefore, it is possible to reverse the magnitude relation of the voltages across the capacitors C ₁ and C ₂ depending on whether the control signal is at the H level or the L level, and as in the first and second embodiments,
The output of the comparator CP ₁ can be inverted according to the control signal. Other configurations and operations are similar to those of the first and second embodiments.

(Ninth Embodiment) In this embodiment, as in the eighth embodiment, a signal source 4c that outputs high frequencies of two kinds of frequencies is used. However, the series resonance circuit 7 ₁ , 7 ₂
Instead of the resistors Rr ₁ and Rr ₂ , _one is a low-pass filter 8 _{1 including an} inductor Lf ₁ and a capacitor Cf _1, and the other is an inductor Lf ₂ and a capacitor Cf _2.
And a high-pass filter 8 ₁ composed of That is,
One of the outputs of the respective secondary windings n ₂₁ and n ₂₂ of the drive transformer Tc which is divided is a low pass filter 8 ₁ and a diode D.
The capacitor Cc ₁ is charged through the c ₁ , and the other charges the capacitor Cc ₂ through the high pass filter 8 ₁ and the diode Dc ₂ . Here, the low-pass filter 8 ₁
The high-pass filter 8 _{2 has} the same cutoff frequency, and the cutoff frequency is set between both frequencies of the high frequency output from the signal source 4c.

Therefore, if the signal source 4c outputs the high frequency wave having the lower frequency while the control signal output from the signal source 4a is at the H level, the low pass filter 8
Voltage across the capacitor Cc ₁ by passing through the ₁ becomes higher than the voltage across the capacitor Cc _2, by reverse the control signal to output a high frequency the higher frequency in the period is at the L level from the signal source 4c , Capacitor Cc
Therefore, the voltage across ₁ becomes lower than the voltage across capacitor Cc ₂ . Other configurations and operations are similar to those of the third embodiment.

(Embodiment 10) In each of the above embodiments, the switching element Q of the inverter circuit 2 and the comparator CP ₁
A transistor Qa, which is complementary connected between
Although Qb is interposed, as shown in FIG. 12, if the operational amplifier OP ₁ is used as a comparator, an output circuit corresponding to the transistors Qa and Qb is built in.
The transistors Qa and Qb can be omitted. Any of the above-described embodiments can be replaced with the configuration of this embodiment.

[0046] (Example 11) This example is an example using the one with the output circuit of an open collector type as a comparator CP _1, as shown in FIG. 13, the pull-up the output terminal of the comparator CP ₁ A resistor Rp is connected. Therefore, when the switching element Q is turned on, the gate voltage is applied to the switching element Q through the pull-up resistor Rp, and when the switching element Q is turned off, the switching element built in the comparator CP ₁ is turned on. The residual charge of the gate is removed. Any of the configurations of the first to ninth embodiments can be replaced with the configuration of this embodiment.

(Embodiment 12) In this embodiment, as shown in FIG. 14, the collector-base of the transistor Qd is connected to both ends of the pull-up resistor Rp in the embodiment 11, and a diode is provided between the base-emitter of the transistor Qd. It has a configuration in which Dd is connected in the opposite direction. In addition, the comparator C
The output terminal of P ₁ is connected to the connection point between the base of the transistor Qd and the cathode of the diode Dd,
The connection point between the emitter of d and the anode of the diode Dd is connected to the gate of the switching element Q.

In this configuration, when the switching element Q is turned on, the transistor Qd becomes conductive and the current supplied to the gate of the switching element Q can be made larger than that in the eleventh embodiment. Therefore, the switching element Q is turned on. The time is shortened as compared with the eleventh embodiment. Other configurations and operations are similar to those of the eleventh embodiment, and any of the first to ninth embodiments can be replaced with the configuration of this embodiment.

(Embodiment 13) In this embodiment, as shown in FIG. 15, in place of the comparator CP ₁ used in Embodiments 1 to 9, a pair of complementary connected transistors Qe ₁ and Qe ₂ is used. Using capacitor C
The configuration is such that the magnitude relation between the connection points of c ₁ and Cc _{2 and} the connection points of the resistors Rc ₁ and Rc ₂ is determined. The bases of the output transistors Qf ₁ and Qf ₂ are connected to the collectors of the transistors Qe ₁ and Qe ₂ , respectively. The transistors Qf ₁ and Qf ₂ are complementary, and the collectors are connected to each other by a switching element Qf.
Commonly connected to the gate of.

In this configuration, the capacitors Cc ₁ and Cc _{2 are}
One of the transistors Qe ₁ and Qe ₂ is turned on in accordance with the magnitude relation between the potential of the connection point of Q and the potential of the connection point of the resistors Rc ₁ and Rc ₂ , and the transistor Q which is turned on is turned on.
A transistor Q whose base is connected to e ₁ and Qe _2.
f ₁ and Qf ₂ are turned on. Therefore, like the first to ninth embodiments, the switching element Q can be turned on / off depending on whether the control signal is at the H level or the L level.

(Embodiment 14) In this embodiment, as shown in FIG. 16, a series circuit in which resistors Re ₁ and Re ₂ are connected in series at both ends of a series circuit of Zener diodes ZD ₁ and ZD ₂ is used as a capacitor Cc _1. , Cc ₂ are connected in parallel to each other, and the connection points of both capacitors Cc ₁ and Cc _{2 and} the connection points of both Zener diodes ZD ₁ and ZD ₂ are commonly connected.
Furthermore, Zener diodes ZD ₁ and ZD ₂ and resistors R
e _1, transistor Qf ₁ to a connection point between the Re _2, Qf ₂
It has a configuration in which the bases of are connected. Transistor Q
f ₁ and Qf ₂ are complementary as in the thirteenth embodiment. Also, both Zener diodes Z
The breakover voltages of D ₁ and ZD ₂ are set equal.

In this configuration, the capacitors Cc ₁ and Cc _{2 are}
The voltage across both ends is detected by Zener diodes ZD ₁ and ZD ₂ . When the voltage across the capacitor Cc ₁ exceeds the breakover voltage of the Zener diode ZD ₁ , the transistor Qf ₁ turns on, and when the voltage across the capacitor Cc ₂ exceeds the breakover voltage of the Zener diode ZD ₂ , the transistor Qf ₂ turns on. Become. Therefore, the comparator CP ₁ and the transistors Qa and Qb
It operates similarly to the configuration using. Further, the configuration of this embodiment can be replaced with any of the configurations of the first to ninth embodiments.

(Fifteenth Embodiment) In the first and second embodiments, the transistors Qa and Qb for driving the switching element Q are driven by using the voltage across the series circuit of the capacitors Cc ₁ and Cc ₂ as a power source. However, as shown in FIG. 17, power may be obtained from both ends of the switching element Q. That is, the voltage across the switching element Q obtained through the current limiting resistor Rf and the diode Df is stabilized by the Zener diode ZDf, and the capacitor C
By smoothing with g, the voltage across the capacitor Cg is used as the power source for driving the transistors Qa and Qb. Other configurations and operations are similar to those of the first and second embodiments.

(Embodiment 16) This embodiment is shown in FIG.
As described above, in the circuit configurations of the first and second embodiments,
One drive transformer Tc and two secondary windings n_{twenty three}, N_{twenty four}To
Provide each secondary winding n _{twenty three}, N_{twenty four}Drive circuit for each 5₁,
5₂And each switching element Q₁, Q₂The drive
To do. Here, the embodiment in FIG.
Those having the same functions as those of the respective configurations of 1 are the same as those of the first embodiment.
After the number, the subscript of 1 or 2 is added. This structure
In the configuration, each secondary winding n of the drive transformer Tc_{twenty three}, N_{twenty four}Is after
It is connected in reverse polarity to the stage circuit. Because of this
The switching element Q₁And switching element Q₂What is
The on / off timing is reversed. This embodiment
In this configuration, for example, half bridge type inverter
It can be used for driving path 2. In addition, in this embodiment
Full bridge type inverter circuit 2 if two sets are used
It is also possible to drive. For other configurations and operations
The same applies to the first and second embodiments.

(Embodiment 17) In this embodiment, as shown in FIG. 19, in the circuit configuration of Embodiment 1, Embodiment 2, etc.,
Four secondary windings n ₂₃ ~n ₂₆ provided on one driving transformer Tc, the drive circuits 51 _to each secondary winding n ₂₃ ~n ₂₆
5 in _{which 4} is provided for driving each separate switching element Q ₁ to Q _4. That is, the secondary windings n _{23 to} n ₂₆ have two opposite polarities with respect to the subsequent circuit. Here, in FIG. 19, components having the same functions as those of the configuration of the first embodiment are denoted by the same reference numerals as those in the first embodiment, and then 1 to 4 are added.
Is attached. By using this circuit, for example, the full-bridge type inverter circuit 2 can be driven.

(Embodiment 18) In this embodiment, as shown in FIG. 20, a capacitor Ch is connected in parallel to a resistor Rc ₂ in the structure of the embodiment 1. As described in the first embodiment, in the comparator CP ₁ , the input voltage to the non-inverting input terminal (potential of the connection point of the resistors Rc ₁ and Rc _{2 in} the _first embodiment) and the connection point of the capacitors Cc ₁ and Cc ₂ are connected. Since the potential is compared, the potential at the connection point of the capacitors Cc ₁ and Cc ₂ is equal to the voltage across the capacitor Cc ₂ when the negative side of the capacitor Cc ₂ is used as a reference. This voltage, as shown in FIG. 21 (f), the transistor Qc ₂ is turned on but rises immediately from (FIG. 21 (d) refer) immediately capacitor Cc ₂ is charged, discharge resistance Rc _1, Rc ₂ And the like, the fall of the voltage after the transistor Qc ₂ is turned off becomes gentle (the voltage across the capacitor Cc ₁ shown in FIG. 21E with respect to the on / off of the transistor Qc ₁ shown in FIG. 21C). The same).

On the other hand, by connecting the capacitor Ch to the non-inverting input terminal of the comparator CP ₁ ,
Since the voltage applied to the non-inverting input terminal is stable as shown in FIG. 21 (g), the output change timing of the comparator CP ₁ is set according to the voltage change of the capacitor Cc ₂ as shown in FIG. 21 (h). You can do it. That is, Example 17
When driving the _four switching elements Q _{1 to} Q ₄ as described above, it may be required to shift the operation timings of the respective switching elements Q _{1 to} Q _{4 at} the timings shown in FIG. Such a timing shift can be easily realized by appropriately setting the discharge characteristics of the capacitor Cc ₂ (that is, changing the capacitances of the capacitors Cc ₁ and Cc ₂ and the resistance values of the resistors Rc ₁ and Rc ₂ ). it can. In FIG. 21, (a) shows the output of the signal source 4c, and (b) shows the output of the signal source 4a.

(Embodiment 19) In Embodiment 18, the capacitors Cc ₁ and Cc ₂ are set to have substantially the same capacitance, but in the configuration of Embodiment 1, both capacitors Cc ₁ and Cc ₂ are set.
By making the capacitance of c ₂ different (Cc ₁ <Cc ₂ ), a time difference as shown in FIG. 22 can be provided in the operation timing of each of the switching elements Q _{1 to} Q ₄ .

[0059] That is, with the configuration that does not use the capacitor Ch as in Example 18, as shown in FIG. 23 (g), variation occurs in the input to the non-inverting input terminal of the comparator CP _1, the capacitor Since there is a difference in the capacities of Cc ₁ and Cc ₂ , there is also a difference in the charging / discharging time (Fig. 21 (e) shows the voltage across capacitor Cc ₁ ,
(F) is the voltage across capacitor Cc ₂ ), FIG.
As described above, the rising and falling edges of the comparator CP ₁ differ from the rising and falling edges of the control signal (shown in FIG. 23 (b)) in timing differences td ₁ and td.
₂ will be offset. Note that in FIG. 23, (a)
Is the output of the signal source 4c, (c) is the operation of the transistor Qc ₁ , and (d) is the operation of the transistor Qc ₂ . Also,
The configuration other than the capacitances of the capacitors Cc ₁ and Cc ₂ is the same as that of the first embodiment.

(Embodiment 20) In this embodiment, the resistance values of the resistors Rc ₁ and Rc ₂ in the circuit configuration of the embodiment 1 are made different (Rc ₁ > Rc ₂ ). Here, the voltage applied to the non-inverting input terminal of the comparator CP ₁ is half of the added value of the voltages across the capacitors Cc ₁ and Cc ₂ , which theoretically becomes a constant value, but in reality, Figure 24
(G) 'and FIG. 24 (g), the capacitor Cc
_Since there is a difference between the rising speed and the falling speed of the voltage across the terminals ₁ and Cc ₂ (FIG. 24 (e) is the voltage across the capacitor Cc ₁ , FIG. 24 (f) is the voltage across the capacitor Cc ₂ ), the control signal (Shown in FIG. 24 (b)) is H level and L
When it switches to the level, it becomes high only for a short time. That is, if the resistance values of the resistors Rc ₁ and Rc ₂ are equal,
When the control signal changes from the H level to the L level, the voltage across the capacitor Cc ₂ immediately rises to bring the output of the comparator CP ₁ to the L level. When the control signal changes from the L level to the H level, the capacitor C
fall of the voltage across the c ₂ is the gradual, but the output of the comparator CP ₁ by the voltage at the non-inverting input terminal of the comparator CP ₁ is temporarily increased rises to H level in a relatively short period of time.

On the other hand, as in the present embodiment, the resistance Rc
By providing a difference between the resistance values of ₁ and Rc _2, the timing at which the voltage applied to the non-inverting input terminal of the comparator CP ₁ becomes high is delayed as shown in FIG.
As described above, there is a delay in the time when the output of the comparator CP ₁ rises to the H level. In this way, the resistance R
By providing a difference between the resistance values of c ₁ and Rc ₂ ,
It is possible to shift the rising and falling timings of the output of the comparator CP ₁ .

(Embodiment 21) Embodiment 14 shown in FIG.
When adopting the configuration of Zener diode Z
By making the breakover voltages of D ₁ and ZD ₂ different, it is possible to shift the inversion timing of the switching element Q with respect to the inversion timing of the control signal.

(Embodiment 22) In this embodiment, as shown in FIG. 25, in the configuration of Embodiment 1, capacitors Cc ₁ ,
A delay circuit composed of a resistor Rk, a diode Dk and a capacitor Ck is inserted between the connection point of Cc ₂ and the inverting input terminal of the comparator CP ₁ . The resistor Rk and the diode Dk are connected in parallel, and the cathode of the diode Dk is connected to the connection point of the capacitors Cc ₁ and Cc ₂ . A series circuit of the diode Dk and the capacitor Ck is connected in parallel with the capacitor Cc ₂ .

[0064] By providing the delay circuit as described above, it will be input at the time of rise of the voltage across the capacitor Cc ₂ to the inverting input the comparator CP ₁ is delayed, also the voltage across the capacitor Cc ₂ At the time of the fall, the presence of the diode Dk causes the fall without delay. Therefore, by appropriately setting the time constant of the delay circuit, the switching element Q can respond to the control signal.
The on / off timing of can be shifted. Other configurations and operations are the same as those of the first embodiment.

(Embodiment 23) In this embodiment, as shown in FIG. 26, a resistor Rj is inserted between the input and output ends of the comparator CP ₁ in the embodiment 18 shown in FIG. Hysteresis is added to the operation of ₁ . With this configuration, the output of the comparator CP ₁ is stable even if the input changes a little. Other configurations and operations are similar to those of the eighteenth embodiment.

In each of the above-described embodiments, the reference terminals (for example, the emitters of transistors and the sources of FETs) of the switching elements Q _{1 to} Q ₄ of the inverter circuit have the lowest potential with respect to the capacitors Cc ₁ and Cc ₂ . While connected to, for example, example 1, by connecting the reference terminal to the connection point of the capacitor Cc _1, Cc ₂ in such second embodiment, at the oFF time of the switching elements Q ₁ to Q _4, the switching element Q ₁ It is also possible to set the potential of the control terminals (base or gate) of Q ₄ to negative.

[0067]

According to the invention of claims 1 to 4, two kinds of high-frequency signals are passed through the drive transformer to insulate the signal side from the switching element, and the transformer transmits high frequencies to reduce the size. There is an advantage that one can be used. Further, since the two types of signals are charged so as to switch the magnitude relationship between the voltages across the pair of capacitors, and a binary signal is generated based on this magnitude relationship, the switching element can be turned on / off. Moreover, like the conventional configuration, the transformer 2
By driving a switching element by generating a binary signal instead of connecting the switching element to the next winding via a resistor, the rising and falling edges of the signal controlling the switching element can be made steep. It is possible to reduce switching loss and stress on the switching element. Moreover, since the output impedance for the switching element can be appropriately set as a circuit configuration,
There is an advantage that the sneak from the main circuit side controlled by the switching element can be reduced and the malfunction can be less likely to occur.

According to the fifth to seventh aspects of the invention, when comparing the magnitude relations of the voltages across both capacitors, it is possible to make a difference in the time change of the voltages to be compared,
As a result, it is possible to appropriately set the timing for turning on / off the switching element. That is, when it is required to shift the on / off timings from each other by using a plurality of switching elements, it is required only by adjusting the secondary side of the drive transformer while making the signal on the primary side of the drive transformer common. Has the advantage that

According to the invention of claim 8, since the binary signal is generated by comparing the voltage difference between both capacitors with a threshold value, the same effect as that of claims 1 to 4 can be obtained.
By appropriately setting the relationship between the voltage difference between both ends of the capacitor and the threshold value, there is an advantage that the on / off timing of the switching element can be adjusted only by adjustment on the secondary side of the drive transformer.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is an operation explanatory diagram of the first embodiment.

FIG. 3 is a circuit diagram of a second embodiment.

FIG. 4 is an operation explanatory diagram of the second embodiment.

FIG. 5 is a circuit diagram of a main part of the third embodiment.

FIG. 6 is a circuit diagram of a fourth embodiment.

FIG. 7 is a circuit diagram of a main part of the fifth embodiment.

FIG. 8 is a circuit diagram of a main part of the sixth embodiment.

FIG. 9 is a circuit diagram of a main part of the seventh embodiment.

FIG. 10 is a circuit diagram of a main part of the eighth embodiment.

FIG. 11 is a circuit diagram of a main part of the ninth embodiment.

FIG. 12 is a circuit diagram of a main part of the tenth embodiment.

FIG. 13 is a circuit diagram of a main part of the eleventh embodiment.

FIG. 14 is a circuit diagram of essential parts of Example 12;

FIG. 15 is a circuit diagram of a main part of the thirteenth embodiment.

FIG. 16 is a circuit diagram of essential parts of Example 14;

FIG. 17 is a main-portion circuit diagram of the fifteenth embodiment.

FIG. 18 is a circuit diagram of the sixteenth embodiment.

FIG. 19 is a circuit diagram of the seventeenth embodiment.

FIG. 20 is a circuit diagram of the eighteenth embodiment.

FIG. 21 is an explanatory diagram of the operation of the eighteenth embodiment.

FIG. 22 is an explanatory diagram of the operation of the eighteenth embodiment.

FIG. 23 is an explanatory diagram of the operation of the nineteenth embodiment.

FIG. 24 is an operation explanatory view of the twentieth embodiment.

FIG. 25 is a circuit diagram of an example 22.

FIG. 26 is a main-portion circuit diagram of the twenty-third embodiment.

FIG. 27 is a circuit diagram of a conventional example.

FIG. 28 is a circuit diagram of a main part of a conventional example.

FIG. 29 is a circuit diagram of another conventional example.

FIG. 30 is a circuit diagram of still another conventional example.

[Explanation of symbols]

2 inverter circuit 4 control circuit 4a signal source 4c signal source 4d ₁ AND gate 4d ₂ AND gate 4e ₂ inverting circuit Cc ₁ capacitor Cc ₂ capacitor CP ₁ comparator Dc ₁ diode Dc ₂ diode Q switching element Qa transistor Qb transistor Qc ₁ transistor Qc ₂ transistor Rc ₁ resistor Rc ₂ resistor Tc drive transformer

Claims (8)

[Claims] 1. A drive circuit comprising at least one switching element, which is used in a power conversion device for converting and outputting power of a power supply by turning on / off the switching element, and which controls to turn on / off the switching element. , A means for generating two kinds of high-frequency signals by switching them at a predetermined cycle, a drive transformer for electrically insulating the above signals and transmitting them to a subsequent circuit, and a rectifying means on the secondary side of the drive transformer. A pair of connected capacitors,
A binary output is generated in accordance with the means for exchanging the magnitude relationship between the voltages across the capacitors according to the signals and the determination result of the magnitude relationship between the voltages across the capacitors, and the switching element is driven by the binary output. And a drive circuit of a power conversion device. 2. The two kinds of signals have different frequencies, and a resonance circuit having a resonance frequency of each signal is inserted in a charging path to the drive transformer and each capacitor, and The drive circuit of the power converter according to claim 1, wherein the magnitude relationship is switched according to the frequency of the signal. 3. The two types of signals have different frequencies, and a low-pass filter and a high-pass filter having a cut-off frequency at an intermediate frequency between the frequencies of the respective signals are provided in the charging path to the drive transformer and the respective capacitors. 2. The drive circuit for a power conversion device according to claim 1, wherein one of the capacitors is inserted and the magnitude relationship of the voltage across each capacitor is switched according to the frequency of the signal. 4. The drive transformer comprises a plurality of secondary windings,
A pair of capacitors connected via rectifying means, a means for exchanging the magnitude relationship of the voltage across each capacitor according to the above signals, and a binary output depending on the determination result of the magnitude relationship between the voltage across both capacitors. The drive circuit of the power converter according to claim 1, further comprising: a means for generating and driving the switching element by the binary output. 5. A filter circuit for stabilizing one of the voltages to be compared is provided at an input portion of the means for determining the magnitude relationship of the voltages across both capacitors. Power converter drive circuit. 6. The drive circuit for a power converter according to claim 1, wherein the capacitors have different capacities. 7. A delay circuit for delaying one voltage change to be compared is inserted in the input part of the means for judging the magnitude relation of the voltage across both capacitors. Power converter drive circuit. 8. A drive circuit which is provided with at least one switching element, is used in a power conversion device for converting and outputting power of a power supply by turning on / off the switching element, and controls to turn on / off the switching element. , A means for generating two kinds of high-frequency signals by switching them at a predetermined cycle, a drive transformer for electrically insulating the above signals and transmitting them to a subsequent circuit, and a rectifying means on the secondary side of the drive transformer. A pair of connected capacitors,
Means for exchanging the magnitude relationship between the voltages across the capacitors according to the signals, and means for comparing the difference between the voltages across the capacitors with a threshold value to generate a binary output and driving the switching element by the binary output. A drive circuit for a power conversion device, comprising: