JPH08273400A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor memory device that facilitates word line defect analysis. A memory cell array in which memory cells are arranged at respective intersections of a plurality of word lines WL and bit lines BL,
In a mask ROM having a word line selection circuit and a bit line sense amplifier circuit, a test memory cell array 15 in which a predetermined data pattern for detecting a word line defect is written is arranged at the end of a word line WL. A bit line selection circuit 16 and a sense amplifier circuit 17 for reading data from the dedicated memory cell array 15 are arranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a mask ROM, EP
The present invention relates to a semiconductor memory device such as a ROM and an EEPROM, and more particularly to a semiconductor memory device that facilitates a test for initial failure.

[0002]

2. Description of the Related Art Mask ROMs are
Chip failure analysis becomes very difficult. For example,
NAND mask RO made by submicron rule
In the M chip, it is very difficult to detect a defect by observing it optically. Further, usually, for screening, memory data is read before cutting chips from a wafer to electrically check (die sort) whether there is a defective bit. At this time, even if there is a defect of a plurality of bits, it is not easy to determine whether it is a memory cell write defect, a word line defect, or a bit line defect. It is possible to perform scrambling processing that rearranges the bit pattern corresponding to the actual layout on the chip and calculate whether the defect of a plurality of bits is along the word line direction or the bit line direction by calculation. take time. Even if a defect in the word line direction is known, it is difficult to determine whether the word line is open or short-circuited.

[0003]

As described above, in the conventional semiconductor memory device, failure analysis is difficult due to the miniaturization of elements. The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device that facilitates word line defect analysis.

[0004]

According to the present invention, a memory cell array in which memory cells are arranged at respective intersections of a plurality of word lines and bit lines, a word line selection circuit for selectively driving the word lines, and a bit line are provided. In a semiconductor memory device having a sense amplifier circuit for reading line data, a test memory cell array for detecting a word line defect at the end of the word line, and a test sense amplifier for reading data from the test memory cell array. And a circuit are arranged.

For example, a memory cell array is an N-stage NAND
In the case of the type configuration, the test memory cell array has an N-type for detecting an open or a short of N word lines.
An N-stage NAND type configuration having a pair of bit lines,
It is assumed that the test data is written in the patterns reverse to each other for each bit line pair. A bit line selection circuit is provided for selectively connecting one of the bit line pairs to the sense amplifier circuit.

[0006]

According to the present invention, a test memory cell array in which a predetermined test data pattern has been written is arranged at the word line termination portion, and the open defect and the short defect of the word line can be easily checked by reading the data. it can.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAN according to an embodiment of the present invention.
2 is a block diagram of a main part of a D-type mask ROM. As shown, a plurality of word lines WL (WL0, WL1,
,) And bit lines BL (BL0, BL1, ...) At the intersections of the memory cells, a memory cell array 11 in which data is mask-programmed, a word line selection circuit 12 for selectively driving that word line, a bit line Selection circuit 1
3 and a sense amplifier circuit 14 for reading the data of the selected bit line.

At the end of the word line WL of the memory cell array 11, there is provided a test memory cell array 15 in which memory cells similar to the memory cell array 11 driven by these word lines WL are arranged with a predetermined data pattern. Has been. A bit line selection circuit 16 and a sense amplifier circuit 17 are also provided for the test memory cell 15.

FIG. 2 shows a specific configuration of the memory cell array 11 and the test memory cell array 15 in the case of an 8-stage NAND type mask ROM. As shown in the drawing, eight memory MOS transistors adjacent to each other are connected in series so as to share the source and the drain and are connected to one bit line. Each memory MOS transistor of the memory cell array 11 is set to D type by, for example, selective ion implantation, or is left in an E type state having a high threshold voltage. The memory transistors surrounded by circles in Fig. 2 are D type, and the others are E type.
It is a type.

In the test memory cell array 15, eight pairs of bit lines are prepared for eight word lines WL. Data is written in each of the eight word lines WL in a data pattern necessary for detecting an open or a short. The data pattern is shown in FIG. The circles in FIG. 3 correspond to the circles in FIG. 2 and indicate that the memory MOS transistors there are of the D type.

For example, focusing on the bit line pair BL01 and BL02 of the test memory cell array 15, this bit line pair BL01 and BL02 is for testing the word line WL7.
When viewed along BL01, only the intersection with WL7 is of E type, the other is of D type, and along BL02, the pattern is opposite to that of BL01. Next bit line pair BL11 and BL
Reference numeral 12 is for testing the word line WL6, and when viewed along BL11, only the intersection with WL6 is of E type, the other is of D type, and along BL12, the pattern is opposite to that of BL11. Similarly, test data is written in opposite patterns along one pair of bit lines so that only one is of E type and the other is of D type.

As shown in FIG. 3, the sense amplifier circuit 17 includes a sense amplifier SA0, which is provided for each bit line pair.
SA1, ... As the bit line selection circuit 16, there are provided select gate MOS transistor pairs (S00, S01), (S10, S11), ... Which selectively connect one of the bit line pairs to the sense amplifiers SA0, SA1 ,. . These select gate MOS transistor pairs are selected by select gate lines S0 and S1.

With such a structure, at the time of die sort after the wafer process is completed, the word line WL is set as follows.
Defect check is performed. Explaining the defect check of the word line WL7, first, the word line WL7 =
“H”, WL0 to WL6 = “L”, and select gate lines are S0 = “H” and S1 = “L”. Under this condition, if the word line WL7 does not have a defect such as an open or a short circuit, all the memory MOS transistors along the bit line BL01 become conductive, and the sense amplifier SA0 is drawn by drawing the current.
Input node goes to "L" level. At this time, since the other sense amplifiers SA1 to SA7 do not draw current,
These input nodes remain "H".

When the word line WL7 is open or short-circuited with the adjacent word line WL6, the memory MOS transistor at the intersection of this and the bit line BL01 is not turned on, or becomes an intermediate potential together with the adjacent word line WL6.
Memory transistor at the intersection of WL7 and BL01, and WL
The memory transistors of 6 and BL11 are turned on at the same time, and current is drawn into these bit lines BL01 and BL11. The former can be detected by reading the output of the sense amplifier SA0, and the latter can be detected by providing the same output to the two sense amplifiers SA0 and SA1. From the above, it is possible to determine whether the word line WL7 is open or short-circuited or normal.

To determine whether the word line WL7 has an open defect or a short defect, the word line WL7 =
"L", WL0 to WL6 = "H", and the selection gate line is S0 = "L" and S1 = "H". Under this condition, even if the word line WL7 is open, if the other word lines are normal, all the memory MOS transistors along the bit line BL02 become conductive, so that the sense amplifier S
The potential of the input node of A0 drops. At this time, no current is drawn in the other sense amplifiers SA1 to SA7. If the word lines WL7 and WL6 are short-circuited, the potential of the word line WL6 drops, the E-type memory MOS transistor on this word line WL6 cannot conduct, and there is no current drawing at the input node of the sense amplifier SA0. Or, the word lines WL6 and WL7 are set to an intermediate potential, the memory transistors at the intersections of the bit lines BL01 and BL11 and these word lines are turned on, and the same output is obtained to the sense amplifiers SA0 and SA1. Will be This allows
It can be determined whether the word line WL7 has an open defect or a short defect.

The same applies to the other word lines WL6, WL5, .... That is, the selection gate line is S0 = “H”, S
1 = “L”, the word lines are sequentially set to “H” one by one, and scanning is performed to keep the rest at “L”, and S0 =
By setting "L" and S1 = "H", the word lines are sequentially set to "L" one by one, and the rest is held at "H", so that the word lines WL7 are output at the outputs of the sense amplifiers SA0, SA1 ,. , WL6, ... Can be inspected for open or short defects.

As described above, according to this embodiment, a test memory cell array in which a predetermined test data pattern has been written is arranged at the word line terminal portion, and it is possible to easily check an open or short defect of the word line. it can. The test memory cell array has 16 bit lines in the case of 8-stage NAND type memory and 32 bit lines in the case of 16-stage NAND type memory, and its area is neglected with respect to the original area of the memory cell array. It is small enough to be possible, so increasing the chip area is of little concern. Also, the data of the test memory cell is only tested by the probe during die sort at the wafer stage,
Of course, the output terminal after packaging is unnecessary.

The present invention is not limited to the above embodiment. For example, although the NAND-type mask ROM has been described in the embodiment, E
The present invention can be similarly applied to PROMs and EEPROMs as well as when a NOR type memory cell structure is used.

[0019]

As described above, according to the present invention, a test memory cell array in which a predetermined test data pattern is written is arranged at the word line terminal portion, and the data line is read out easily to make a word line open defect. Also, a semiconductor memory device capable of checking for short circuit defects can be obtained.

[Brief description of drawings]

FIG. 1 shows a main configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 shows configurations of a memory cell array and a test memory cell array according to the same embodiment.

FIG. 3 shows a configuration of a test memory cell array of the same embodiment.

[Explanation of symbols]

11 ... Memory cell array, 12 ... Word line selection circuit, 1
3 ... Bit line selection circuit, 14 ... Sense amplifier circuit, 15
... test memory cell array, 16 ... bit line selection circuit, 17 ... sense amplifier circuit.

Claims (2)

[Claims] 1. A memory cell array in which memory cells are arranged at intersections of a plurality of word lines and bit lines, a word line selection circuit for selectively driving the word lines, and a sense amplifier circuit for reading out bit line data. In a semiconductor memory device having a memory cell array, a test memory cell array for detecting a word line defect and a test sense amplifier circuit for reading data from the test memory cell array are arranged at the end of the word line. A semiconductor memory device characterized by: 2. The memory cell array comprises N stages of NANs.
The test memory cell array has a D-type configuration, and the test memory cell array has an N-stage NAND-type configuration having N pairs of bit lines for detecting an open or a short circuit of N word lines. 2. The semiconductor memory device according to claim 1, further comprising a bit line selection circuit for writing the test data in the reverse pattern and selectively connecting one of the bit line pairs to the sense amplifier circuit.