JPH0828834B2 - Signal processor - Google Patents

Description

The present invention relates to a real-time digital signal processing device, and more particularly to a high-definition digital television, a video equalizer, a communication equalizer, an image signal processing, etc. The present invention relates to a circuit system of a high-speed digital signal processing device.

[Conventional technology]

Prior Art 1: Toshihide Watanabe et al., 1985, National Institute of Electronics and Communication Engineers Semiconductor and Materials Division National Convention p2-119 Prior Art 2: Murakami et al., Ai. E. E, E, CEE, 29, No.3, 1983, pp.129-133 (Jinzo Muraka
mi et al, IEEE, CE-29, No.3, 1983, p129-133) The conventional high-speed digital signal processing device has a large number of arithmetic circuits 4, multiplication circuits 5, registers 3, coefficient memories as shown in FIG.
It consisted of 7, delay memory 6 and so on. In particular, the transversal filter shown in the right-hand block 10 in FIG. 2 is very often used, and the number of elements of the multiplier 5 and the arithmetic circuit 4 used here is about 3,000 transistors and about 1,0, respectively.
Since there are as many as 00 transistors, the circuit scale becomes large, which is a problem. As one of the countermeasures, multiply by RAM
A method has been proposed in which a look-up table (reference table) using (random access memory) is used. (Prior Art 1) However, even if the above method is used, the number of elements used per tap of the transversal filter is about 5,000 transistors, and with the filter 10 (symmetry coefficient 8 taps) of FIG. The circuit scale is 40,000 transistors. This is the same number of devices as a 16-bit micro computer. In high-definition digital television receivers, nearly ten such filters are used, and reducing the circuit scale of these filters is a major issue.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider the effect of improving the device performance as described below, and each arithmetic circuit is used without time multiplexing, so that the circuit scale is very large and there is a problem in making it into an LSI.

With the progress of process technology, the gate length of MOS transistors has become shorter, and along with this, the device characteristics, especially the gate delay time, have become shorter. The calculation processing speed of multipliers and the like using this has also been improved. Figure 23 shows the changes. The 8 × 8 bit multiplication time (231), which required 50 ns in the 3 μm technology, can be executed in 12 ns in the 0.8 μm technology. On the other hand, for example, since the sampling time (232) of the digital TV system is constant at 70 ns, it would be extremely wasteful to use each arithmetic circuit only once in one sampling time.

In the above example, time multiplexing can be performed at least 5 times, and the number of operation circuits used can be 1/5. This tendency becomes stronger as the process technology advances.

An object of the present invention is to provide a signal processing circuit that efficiently uses this time-division multiplexing.

The present invention can be applied not only to MOS transistors but also to bipolar transistors or hybrid circuits of MOS and bipolar circuits.

[Means to solve the problem and its action]

The above-mentioned object is a unit signal processing circuit (hereinafter SPC: Signal
It is achieved by performing signal processing using a plurality of Processing Cores. Fig. 1 shows the conventional circuit of Fig. 2 by SPC.
It is configured by using. In this example, a high-definition digital television signal processing circuit is shown, and the sampling time is 70 ns. On the other hand, if the gate length of the MOS transistor used is 0.8 μm, the operation processing time of the 8 × 8 bit multiplier, which takes the longest processing time, is 12 ns, so 5 times of time multiplexing or 14 ns instruction execution time is required. SPC
Can be operated. Here, SPC2 (2) is performing a transversal filter, and SPC1 (1) is performing other arithmetic processing. As can be seen from Fig. 1, focusing only on the number of arithmetic processing circuits that show the largest proportion in the circuit, SPC1 is 2/9, SPC2 has 1/4 multiplier and 2 arithmetic circuits.
It has been reduced to / 7.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1, Table 1 and Table 2.
It will be described with reference to a table. SPC1 (1) and SPC2 shown in Fig. 1
(2) operates with the programs shown in Table 1 and Table 2, respectively. Regarding the concrete configuration of the control circuit,
As will be described later with reference to the drawings, the execution of instructions will be described here with reference to SPC2 (FIG. 1) and Table 2. The signal processing to be realized is the transversal filter shown in FIG.

In FIG. 1, 3 is a register, 4 is an arithmetic circuit, 5 is a multiplication circuit, 6 is a delay memory, 7 is a coefficient memory, 8 is a latch, and 9 is a data bus.

First, in the first step, the input data is read into the latch L6 (L6 = IN), and at the same time, the first coefficient C1 is loaded into the latch L5 from the coefficient memory 7 (L5 = C1). These latches 8 are all master / slave latches as shown in FIG. 3, and data is taken in at the first phase clock φ ₁ and appears at the output at the _second clock source φ ₂ . This makes the first
In the latter half of the step, data is input to the multiplication circuit 5 immediately after φ ₂ rises.

In the second step, the multiplication result is two latches L8 and L10.
At the same time (L8 = L6 * L5, L10 = L6 * L5), L7,
The data to be added to these are taken into the L9 from the delay memory 6, respectively. (L7 = Z7, L9 = 0) Also,
At the same time, the coefficient C2 to be multiplied next is taken into the latch L5.

At the third step, the next multiplication result is fetched into the latches L8 and L10, and at the same time, the addition result of L7 and L8 by the arithmetic circuit 4 is stored in the register R13 (R13 = L7 + L8) and the addition result of L9 and L10 is stored in the memory. Taken in by Z1 (Z1 = L9 + L10). In this way, multiply the current data by adding the previous data. It uses a pipeline process that is executed at the same time as the process. Also, the two adders 4 are operating in parallel.

The reason why pipeline processing is possible is that a master / slave type latch or a memory is used for input / output of each arithmetic processing circuit. This will be briefly described with reference to FIGS. 3 and 4.

Figure 3 shows master / slave latches A (14), B (1
4 ') are provided between arithmetic circuits A (15) and B (15'). Further, FIG. 4 shows the timing chart.

When φ ₂ rises at time T ₁ , the nth output appears in the latch A (14) and this is immediately processed by the arithmetic circuit A (15). After the delay time T _A , the nth calculation result appears at the output terminal of the arithmetic circuit A, and the latch B (14 ′) takes in it at φ ₁ . By the way, at the time T ₁ , the output of the latch B is the (n−1) th, that is, one before the current data, and this data is processed by the arithmetic circuit B (15 ′). This processing is executed simultaneously with the arithmetic circuit A. This is pipeline processing, which is a method for speeding up arithmetic processing.

As another circuit configuration method of the master / slave latch, there is also a circuit for feeding back to the inverter 511 as shown in FIG. 5 by the clocked inverter 512. In terms of speed, the number of signal passing gates is small, which is high speed. Is.

The clocked inverter is connected to the drive MOS transistor 5 of the inverter as shown in FIG.
14 is continued by the switch MOS transistor 515.

When the frequency of the input signal is high, as shown in FIG. 7, the dynamic type circuit in which the clocked inverter 512 of FIG. 5 is omitted also operates. As a result, not only the number of elements can be reduced, but also the speed can be increased by reducing the parasitic capacitance.

In this way, proceed to Step 6 in Table 2
Perform processing equivalent to that shown in the figure. However, since parallel processing is possible, the previous and next processing can be added to the first and sixth steps, and the sampling interval (5 steps in Table 2) can be shortened. In addition, NOP in Table 2
Is the part that does not execute the command No Operation, and SP
It is inserted to match the timing (5 steps / sampling) with C1, but if the SPCs are operated by independent clocks, this NOP can be removed and the number of steps can be reduced to 4 steps / sampling.

In SPC2 of FIG. 1, two adder circuits 4 are used for parallel operation. This is the signal flow of FIG. This is because it is considered that the two are added simultaneously to the flow and the signal flow in the left direction. As in this case, by adopting the SPC architecture according to the signal processing content, the parallelism of the signal processing is enhanced and the signal processing can be performed at higher speed. If the number of adders is one in the above example, the same signal processing requires approximately twice the number of program steps.

The SPC1 shown in FIG. 1 also employs an architecture that takes into account the details of signal processing. In this case, four bus lines 9 are provided to increase the parallelism of the data flow. In SPC1, 3 is a register, 4 is an arithmetic circuit, and 8 is a latch.

FIG. 8 shows a part of the control circuit of the SPC. The two-phase clocks φ ₁ and φ ₂ that operate the master / slave latches LA, LB, LC (16) use the AND gate 18.
Continued by the latch control signals LAE, LBE, LCE. The timing is as shown in FIG. Here, the latch is when φ ₁ is at H level (in the figure, between T ₁ and T ₂ or T ₅ ,
T ₆ between) takes in input data, phi ₂ conveys ipecac's data latch output in becomes H-level (T _8, T ₇₎ output. Therefore, in order to perform the pipeline operation, the rising edge T _a of the latch control signal is before the rising edge T _{5 of} φ ₁ and φ
After the falling edge T _{4 of 2,} the falling edge T _b is φ ₂ after the falling edge T ₈ of φ
It is desirable to set it before the rising T _{9 of 1} . Also, considering that the output of each latch is updated at the rise of φ ₂ , the control signals ALUC, MPL of the multiplexer 23 and the arithmetic circuit 17 are updated.
XC is set as shown in FIG. Here, it is desirable that the rising edge T _{c of the} control signal is immediately after the rising edge T _{3 of} φ _{2 and} the falling edge T _d is just before the rising edge T _{7 of} φ ₂ .

The above control signals are stored in the program memory 19 shown in FIG.
Are simultaneously read from every one program step.
It also uses the program counter 20 to set the address of this memory. ₁ The clock program counter _phi, using phi _2, reset for the initial state set (R) or Purisetsuto (PR) input is also provided.

Next, the circuit configuration and control method of the registers used in FIG. 1 will be described. As can be seen from the program in Table 2, the Z1, Z2, and Z3 registers in FIG. 1 perform both writing and reading simultaneously in one step. Therefore, the register used here is a master / slave type latch 25 (28: input bus, 29: output bus) as shown in FIG.
In this case, the two-phase clocks φ ₁ and φ ₂ are supplied only to the latch 25 selected by the address decoder 26. Also, only the output of the selected register is a clocked inverter.
Connected to output bus 29 by 27. When writing is not performed, it is necessary to set all outputs of the address decoder to 0. Since one word is always selected in the 4-word / 2-bit address ZAAD, the decoder output ZAO is set to the O level when the ZAWE signal is unnecessary as shown in FIG.

Although a dynamic circuit is used in the circuit of FIG. 10, a static circuit as shown in FIGS. 3 and 5 can also be used. The dynamic circuit has the advantage that it requires a small number of elements.

The registers Z4, Z5, Z6 and Z7 in FIG. 1 are written simultaneously in one step as can be seen from the program in Table 2.
Also, another word is being read. In order to realize this, it is necessary to use a multiport memory cell as shown in FIG. Here, the memory cell 30 is a static circuit of four transistors, but a dynamic circuit of one transistor or the like can also be used. Such a memory cell is assembled with the circuit configuration shown in FIG. Here, an independent address decoder 36 (ZBAD
1, ZBAD2, ZBAD3: address signals) are provided. In addition, since writing is performed only when necessary, write address
The decoder has the enable signal ZB as shown in Fig. 11.
WE1 and ZBWE2 are input. This register consists of 2 input ports and 1 output port (37: data input, 38: data output, 35: sense amplifier, 34: write amplifier, 33: data line, 3
2: Word line, 31: Select switch, 30: Memory cell), but can be freely configured according to the contents of program and architecture.

The coefficient registers C1, C2, C3, C4 in FIG. 1 must be static type in order to hold data for a long time. Therefore, in addition to the memory cell structure shown in FIG. 12, a circuit configuration using the clocked inverter 40 shown in FIG. 14 can be obtained (39: memory cell, 41: address decoder, CAD: address signal). This is to cut off the clocked inverter 40 only at the time of writing and input the data through the tri-state gate 43 and the input bus 42. At this time, the write enable CWE is at 1 level. This circuit has a smaller number of elements compared to the master / slave latches in Figs. 3 and 5, and it does not require a sense amplifier or write amplifier compared to the one in Fig. 12, so it can operate at high speed. is there.

The pulse of the signal that controls the latch and the register group
The timing is shown in FIG. This signal corresponds to the program in Table 2. The binary number in the address signal indicates the address number in each register group, and the x mark indicates that any number may be used.

Figure 16 shows the circuit configuration of the program memory (44: address decoder, 45: buffer, 46: “1” level memory cell, 47: “0” level memory cell, 48: word line, 49: data). line). The stored contents correspond to the programs in Table 2 and the timing chart in FIG. In order to enable high-speed control, each memory cell 46, 47 connects the data line 49 directly to the power supply V _dd or grounds it depending on the stored contents. This program memory contains static RAM, fuse type
PROM, electrically writable EPROM, electrically writable / erasable EEPROM, etc. can also be used.

A circuit for generating the address of the program memory is shown in FIG. 17, and its pulse timing is shown in FIG. In particular, if the frequency of the internal clocks φ ₁ and φ ₂ exceeds 50MHz, it becomes difficult to supply from the outside. Therefore, as shown in the figure above, the internal clock is replaced by a PLL circuit (phase locked loop)
Caused by. The voltage controlled oscillator 52 oscillates the two-phase clocks φ ₁ and φ ₂ , and these are counted down by the quinary counter 53 in accordance with 5 program steps. During this period, 3-bit program memory driving addresses (a0, a1, a2) are generated. This counting down result ▲ ▼ and input signal sampling clock CL
Accurate synchronization is achieved by comparing the phase of KS with the phase comparator 50. In order to set the initial state, the counter 53 is provided with a reset terminal or a preset terminal and a data input terminal. In FIG. 17, 51
Is a lowpass filter. This circuit is provided independently for each SPC (signal processing core) or commonly provided for multiple SPCs. In either case, since the value of the n-ary counter in the PLL circuit can be set independently, the optimum instruction execution time can be set for each SPC.

Further, the clocks φ ₁ and φ ₂ can be supplied from the outside as long as there is no problem in speed.

Now, when a large number of SPCs (unit signal processing circuits) are used, it is necessary to set each operation mode, set arithmetic coefficients and test surely and quickly. This can be achieved by using the SPC bus shown in Figs.

FIG. 19 shows the structure of the SPC2 shown in FIG. 1 when the interface with the SPC bus is taken into consideration. First, the device address (D
A) is read and it is determined whether or not it has been selected by the device decoder 56. When selected, outputs 1 level signal to DS. This allows the program counter to
A multiplexer 57 switches from the main program counter 54 to the external clock and sub-program counter 55 controlled by the preset signal. Thereby, the coefficient setting of the program memory 19, the operation mode setting or the testing program is executed. In the coefficient setting mode, the data (DT) from the SPC bus 59 is input to the coefficient memory 7 via the internal bus 58. In the testing mode, first, input data is set in the coefficient memory 7, the input latch L6 and the delay memory 6 via the internal bus 58, and the program
After running the memory filtering program,
The processing result stored in each memory is read out to the SPC bus 59 via the internal bus 58. Reference numeral 50 is a tri-state gate controlled by each control signal.

In system VLSI, as shown in Fig. 20, a large number of SPC60 (SPC60
PC1 ~ SPC5) are located. All of these SPCs are SPCs
It is controlled from the outside through the interface circuit 61 via the bus 59 or by the internal processor 62. In the figure, 64 is an external processor and 65 is an external bus. In normal operation, in the figure The signal is processed along the high-speed signal path 63, and the interface circuit 61 or the internal processor 62 accesses a specific SPC at the time of setting the testing, the coefficient, or the operation mode to perform the testing or setting.
For example, in an adaptive filter, SPC performs filtering at high speed, and an internal processor performs complicated adaptive calculation processing. The calculated coefficient is transmitted to the SPC filter via the SPC bus during the blanking period or the like.

〔The invention's effect〕

The effect of the present invention is that by performing time multiplexing processing,
That is, the number of elements such as an arithmetic processing circuit can be significantly reduced. 21 and 22 show the above effects. The target signal processing is a 16-tap transversal filter with a symmetric coefficient that expands the function of SPC2 in FIG.

FIG. 21 is a schematic view of the filter, focusing on the arithmetic processing. FIG. 22 shows the total number of transistors in each circuit configuration. FIG. 21 (A) shows a conventional construction method in which time multiplexing is not performed, and the number of elements is about 58,000 transistors as shown in FIG. Including the following circuit,
Here, it is assumed that all have coefficient setting and testing functions. In the above-mentioned prior art 1, the circuit (A) is reported to have about 80,000 elements because the static RAM is used instead of the multiplier.

Now, the filter can be realized by four SPCs that perform time multiplexing twice as shown in FIG. 21 (B). Each SPC 60 having one multiplier 5 and two adders 4 has a transversal filter function with a symmetric coefficient of 4 taps.
(66 is a control circuit section) From FIG. 22, the total number of elements in the above circuit is about 34,000. One SPC if multiplexed 4 more times
Can realize an 8-tap filter, and as shown in (C), 2
The circuit shown in (A) can be realized with one SPC. In this case, the total number of elements is about 19,000, which is reduced to about 1/3 of the conventional circuit. The clock frequency is four times that of the conventional circuit. Considering application to a digital television, for example, the sampling frequency is 14.3 MHz, and four times that frequency is 57.2 MHz. This is 17.5ns in time and the second
From Fig. 3, it is a specification that can be fully realized by using a transistor with a gate length of 0.8 μm.

When the above circuit is multiplexed eight times, a 16 tap filter can be realized with one SPC as shown in FIG. 7D, and the number of elements becomes about 13,000 transistors. The reason that the number of elements is not reduced so much as compared with the above-mentioned FIG. (C) is that the number of elements used for each latch and memory increases.

With respect to other signal processing circuits such as SPC1 in FIG. 1, the effect of reducing the number of elements can be similarly realized. From the above,
It can be seen that the present invention has a large effect in reducing the number of elements as compared with the conventional method, since each arithmetic processing circuit in the processor is utilized with high efficiency by the time multiplex processing.

Another effect is that by using the SPC bus shown in FIG. 20, the operation mode of each SPC, coefficient setting, or testing can be easily performed.

Also, by using the PLL synchronization circuit shown in Fig. 18, a high-speed clock can be generated stably inside the processor, and by providing the PLL synchronization circuit independently, each SPC can independently execute the clock frequency and instruction execution. It has the effect of setting the time.

The signal processing device of the present invention is a high-definition digital TV, LAN, P
LSI for large-scale digital signal processing system such as CM communication
It is very effective against the change.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, a circuit block diagram showing an example of the configuration of an SPC, FIG. 2 is a circuit block diagram showing a conventional digital signal processing device, and FIGS. 3 and 4 are master / slave latches. FIG. 5, FIG. 6, FIG. 6 and FIG. 7 are circuit diagrams showing another configuration example of the master / slave latch, and FIG.
9 and 10 are diagrams for explaining the SPC control circuit, FIG. 10 is a circuit diagram showing an example of the latch register of the SPC, FIG. 11 is a circuit diagram showing the decoder section of FIG. 10, FIG. Figures 13 and 14
Circuit diagram showing an example of another latch register of SPC, 15th
The figure shows the control pulse timing diagram of the latch register group of the SPC. Fig. 16 shows the circuit diagram of an example of the program memory of the SPC. Figs. 17 and 18 explain the address generation circuit of the program memory. Fig. 19 is a circuit block diagram showing the relationship between the SPC and the SPC bus. Fig. 20 is a circuit block diagram showing the configuration of a system VLSI consisting of a plurality of SPCs. Fig. 21 is a conventional transversal filter (A ) And the SPC of the present invention
FIG. 22 is a circuit block diagram showing a comparison with a transversal filter (B to D) according to the configuration, FIG. 22 is a diagram showing the effect of the present invention, and FIG. 23 is a diagram explaining the improvement of the arithmetic processing speed of a multiplier or the like. is there. 1, 2 ... Unit signal processing circuit (SPC), 3 ... Register, 4 ... Operation circuit (or addition circuit), 5 ... Multiplication circuit, 6 ... Delay memory, 7 ... Coefficient memory, 8 ... Latch, 9 ... Data bus ,
10 ... Transversal filter, 11 ... Inverter, 12
... AND circuit, 13 ... NAND circuit, 14, 14 '... Master / slave latch circuit, 15, 15' ... Operation circuit.

Front page continuation (72) Inventor Shinya Oba 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-62-292080 (JP, A)

Claims (3)

[Claims] 1. A signal processing device for performing a predetermined signal processing in synchronization with an input digital signal, wherein the input digital signal and a signal read from a memory are inputted, and the input digital signal and the signal are read. It has a multiplier for computing the read signal, and a first and a second adder, one input of the first adder is connected to the output of the multiplier, the first adder Of the second adder is connected to the output of the first adder via the first latch circuit, and one input of the second adder is connected to the output of the multiplier. The other input of the signal processing device is connected to the output of the second adder via a second latch circuit. 2. In the signal processing device, the output of the first adder is further connected to the other input of the first adder via a delay memory, and the output of the second adder is The signal processing device according to claim 1, wherein the signal processing device is connected to the other input of the second adder through a delay memory. 3. The multiplier, the first adder, and the second adder are configured to operate a plurality of times in a reference clock cycle. The signal processing device according to item 2.