JPH08293200A - Semiconductor memory device and semiconductor memory device testing apparatus and testing method - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a semiconductor memory device capable of shortening an operation test time and improving the efficiency of a redundancy test. A cell information detection circuit that outputs a detection signal K for detecting whether or not the cell information of the storage cells C is the same to a plurality of storage cells C connected to a common bit line BL, BL. 6 is connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device testing apparatus. 2. Description of the Related Art In recent years, semiconductor memory devices have become more highly integrated and have a larger storage capacity. In such a semiconductor memory device, an operation test is performed prior to product shipment, but the operation test tends to take a longer time as the capacity increases. Therefore, it is necessary to reduce the test time.

Further, as the storage capacity increases, the number of defective memory cells tends to increase. Such a semiconductor memory device has a redundancy function for improving yield by switching access to a defective cell to access to a redundant cell provided in advance. Then, during the operation test, a redundancy test for setting redundant cells is also performed for all defective cells, and it is necessary to reduce the time required for this redundancy test and improve the efficiency of the redundancy test.

[0003]

2. Description of the Related Art In an operation test of a semiconductor memory device by a conventional test apparatus, the same data is written in a memory cell of a memory under test, the written data is read out and stored in a test memory in the test apparatus. . At this time, the address of the read data from the memory under test is associated with the address of the test memory in which the read data is stored.

Then, by determining whether all the data stored in the test memory are the same, it is determined whether or not each memory cell of the memory under test is operating normally. At this time, when each storage cell of the test memory in the test apparatus is accessed to read the cell information and it is determined whether or not all the read data are the same, the test time is increased in the semiconductor memory device having a large capacity. Will be long.

Therefore, AND logic or OR logic of the cell information read from the memory cells connected to the same word line to each bit line is taken, and the defective cells are connected to a large number of memory cells connected to the word line. It is generally practiced to shorten the test time by detecting whether or not is included.

The operation of a redundancy test for setting a redundant cell for a defective cell will be described with reference to FIG. First, the test apparatus performs an operation test on each memory cell of the memory under test to generate the fail bit map 1 shown in FIG. 7 (step 1).

That is, the same data is written and read in the memory under test for which the operation test is performed,
The read data is stored in the corresponding address of the test memory. When the data stored in the memory cells connected to each word line of the memory are not the same, all the memory cells connected to the word line are accessed to store the abnormal data. The fail bit map 1 is generated by detecting the address, that is, the address of the defective cell of the memory under test.

For convenience sake, FIG. 7 is composed of 10 word lines of a to n rows and 10 bit lines of A to J columns.
A cell matrix of × 10 will be used to explain 2 in the word line direction.
2 rows of redundant word lines R1 and R2 are provided, and 2 in the bit line direction
It is assumed that column redundant bit lines R3 and R4 are provided. The address detected as a defective cell is indicated by a cross.

Then, it is judged whether or not there is a defective cell based on the fail bit map 1 (step 2). If there is no defective cell, it is not necessary to set the redundant cell, so that it is judged as a completely good product. A judgment is made (step 3), and the test is ended.

When the presence of defective cells is detected in step 2, it is first judged whether or not there are a certain number or more of defective cells on the same word line (step 4). Replace the lines with redundant word lines (step 5).

Here, if the fixed number is set to "5", since the word line does not exist in the fail bit map 1,
Next, it is determined whether or not there are a certain number or more of defective cells on the same bit line (step 6), and if there is, the bit line is replaced with a redundant bit line (step 7).

Since there are 6 defective cells in the bit line in the E column, the bit line in the E column is the redundant bit line R3.
Is replaced by. Next, it is determined whether or not there is a word line and a bit line in which a defective cell is further present (step 8), and if they are not present, it is determined that the repair of the defective cell by the redundant cell is completed (step 9). ), End the test.

When it is determined in step 8 that the word line and the bit line in which the defective cell exists are present, the remaining redundant word line and redundant bit line are sequentially replaced (steps 8, 10, 11).

If the redundant word line and the redundant bit line to be replaced do not remain despite the existence of the word line and the bit line in which the defective cell exists, the repair of the defective cell cannot be completed. The chip is determined to be a defective chip (step 12), and the test ends.

[0015]

In the operation test in the test apparatus as described above, the word lines of the test memory in the test apparatus are sequentially selected and the cell information is read to connect to each word line. It is possible to determine whether or not abnormal data is stored in the memory cells that are stored in the memory cells.By selecting each bit line sequentially, it is possible to determine whether or not abnormal data is stored in the memory cells connected to each bit line. It cannot be judged.

Further, in order to judge the cell information of all the memory cells, it is necessary to sequentially select each word line, and the test time cannot be further shortened. In the redundancy test as described above, when the defective word line and the defective bit line are replaced with the redundant word line and the redundant bit line in step 8, depending on which of the defective word line and the defective bit line is made redundant first, The required number of redundant word lines and redundant bit lines may differ.

That is, for example, the lower order (a row) of the word line
When the replacement is sequentially performed from the direction, when the word lines in the second row and the second row are replaced with the redundant word lines R1 and R2, the redundant word lines are left. Next, it is necessary to replace the bit lines of the B column, the C column, and the F column with the redundant bit lines, but the redundant bit line R3 is already used for the replacement of the bit line of the E column, and the redundant bit lines are insufficient. .

Therefore, since this chip cannot completely repair the defective cell, it is determined to be a defective chip. On the other hand, when the word lines are sequentially replaced from the upper (nu) row direction, the word lines of the Jth row and the Tth row are replaced by the redundant word line R1,
When replaced with R2, the rest of the redundant word lines are gone.
Then, by replacing the bit line of column D with the redundant bit line R4, all defective cells can be relieved.

If the defective word line and the defective bit line are replaced with those having a large number of defective cells, the word line in row H is replaced with the redundant word line R1, and the bit line in column D is replaced with the redundant bit line R4. All defective cells can be relieved.

Even if the bit lines are sequentially replaced, as described above, there are cases where all the defective cells cannot be relieved and cases where the defective cells can be relieved. Therefore, in the redundancy test as described above, even when the same number of defective cells are generated, depending on the existence position of the defective cells and the replacement order of the defective word line and the defective bit line, it is possible to perform relief and when it is not possible. Therefore, there is a problem that the redundancy efficiency is poor and the chip yield cannot be sufficiently improved.

An object of the present invention is to provide a test apparatus which can shorten the operation test time of a semiconductor memory device and improve the efficiency of a redundancy test.

[0022]

FIG. 1 is a diagram for explaining the principle of the invention of claim 1. That is, for the plurality of storage cells C connected to the common bit line BL and bar BL, the detection signal K for detecting whether or not the cell information of the storage cells C is the same.
Is connected to the cell information detection circuit 6.

According to a second aspect of the present invention, a plurality of memory cells connected to a common bit line are connected to a first cell information detection circuit for detecting whether or not the cell information of the memory cells is the same. Multiple memory cells connected to a common word line
A second cell information detection circuit for detecting whether or not the cell information of the memory cells is the same is provided.

According to a third aspect of the present invention, the first cell information detection circuit includes a detection bit line connected to a high potential side power source through a high resistance, and between the detection bit line and the low potential side power source. And a plurality of switch circuits that are opened and closed based on cell information stored in the memory cell, and the second cell information detection circuit is connected to a high-potential-side power source via a high resistance. A detection word line connected thereto, and a plurality of switch circuits interposed between the detection word line and the low-potential-side power supply and opened / closed based on cell information stored in the memory cell. To be done.

According to a fourth aspect of the present invention, the test apparatus includes a test control section and a test memory, and the test control section writes the cell information in the memory under test and reads the cell information written in the memory under test. , The defective cell in the memory under test is detected based on the cell information stored in the test memory. In the test memory, a word line and a bit line are respectively connected to a large number of memory cells to form a cell matrix, and the memory cell is selected by selecting the word line and the bit line. A write / read operation is performed on the memory cell and a plurality of memory cells connected to a common bit line are connected to a cell information detection circuit that detects whether or not the cell information of the memory cells is the same.

According to a fifth aspect of the present invention, the test memory detects, for a plurality of storage cells connected to a common bit line, whether or not the cell information of the storage cells is the same. A second cell information detection circuit that detects whether or not the cell information of the storage cells is the same is connected to the plurality of storage cells connected to the circuit and connected to the common word line.

According to a sixth aspect, the test control section, based on the output signals of the first and second cell information detection circuits,
The number of defective word lines including defective cells and defective bit lines including defective cells is detected, and from the defective bit line and the defective word line, the line with the smallest number of defective cells becomes the redundant line. Replacement is performed, and this operation is repeated to specify a redundant line that makes the defective word line and the defective bit line redundant, and based on the number of redundant lines required to replace the defective bit line and the defective word line, all defective lines are defective. A redundancy test device for determining whether or not the cell can be repaired is provided.

According to a seventh aspect of the present invention, by detecting whether or not the cell information of a plurality of memory cells connected to a common bit line is the same, the number of defective bit lines including a defective cell is detected and the common bit line is detected. The number of defective word lines including defective cells is detected by detecting whether or not the cell information of a plurality of memory cells connected to the word line is the same. , The line with the most defective cells with the smaller number is replaced with a redundant line, and this operation is repeated to identify the redundant line that makes the defective word line and the defective bit line redundant, and the defective bit line and the defective word line are identified. It is determined whether all defective cells can be repaired based on the number of redundant lines required for line replacement.

[0029]

According to the first aspect, the common bit line BL, bar BL
The cell information detection circuit 6 detects whether or not the cell information of the plurality of memory cells C connected to the same is the same, and outputs it as the detection signal K.

In the second aspect, the first cell information detection circuit detects whether or not the cell information of a plurality of memory cells connected to the common bit line is the same, and the second cell information detection circuit. Thus, it is detected whether or not the cell information of a plurality of memory cells connected to the common word line is the same.

According to a third aspect of the present invention, in the first cell information detection circuit, when at least one switch circuit is turned on based on the cell information, the detection bit line is set to the low-potential-side power supply level and all the switch circuits are turned off. Then, the detection bit line is maintained at the high-potential-side power supply level. The second cell information detection circuit, when at least one switch circuit is made conductive based on the cell information, sets the detection word line to the low potential side power supply level, and when all the switch circuits become non-conductive,
The detection word line is maintained at the power supply level on the high potential side.

According to a fourth aspect of the present invention, the cell information of the memory under test is stored in the test memory, and the cell information detecting circuit provided in the test memory causes the cell information of a plurality of storage cells connected to a common bit line. Are detected to be the same.

According to a fifth aspect of the present invention, in the test memory, the first cell information detection circuit detects whether or not the cell information of a plurality of storage cells connected to a common bit line is the same, The second cell information detection circuit detects whether or not the cell information of the plurality of storage cells connected to the common word line is the same.

According to the sixth and seventh aspects, the number of defective bit lines including defective cells is detected by detecting whether or not the cell information of a plurality of memory cells connected to a common bit line is the same. The number of defective word lines including defective cells is detected by detecting whether or not the cell information of a plurality of memory cells connected to a common word line is the same.
Of the defective bit lines and defective word lines, the line with the most defective cells with the smaller number is replaced with a redundant line,
By repeating this operation, the redundant line that makes the defective word line and the defective bit line redundant is specified. Further, based on the number of redundant lines required to replace the defective bit line and the defective word line, it is determined whether all defective cells can be repaired.

[0035]

EXAMPLE FIG. 2 shows a schematic configuration of a test apparatus embodying the present invention. A test controller 3 and a test memory 4 are provided in the test apparatus 2. Further, the memory under test 5 is connected to the test apparatus 2 during a memory operation test. Then, the test control section 3 outputs the control signal C1 and the write data WD1 to the memory under test 5 to write the same data to the memory under test 5 and to write the data written in the memory under test 5. It is read out as read data RD1.

The test control section 3 outputs a control signal C2 to the test memory 4 and outputs the read data RD1 read from the memory under test 5 to the corresponding address of the test memory 4 as write data WD2. To do.

Further, the test controller 3 reads the read data RD2 based on the data written in the test memory 4.
And the detection signals K1 to Kn and L1 to Lm are read to detect whether or not abnormal data is stored in the test memory 4 and the address at which the abnormal data is stored. The presence or absence of a cell and the address of the defective cell are detected.

The memory under test 5 has a redundancy function, and is assumed to have, for example, two redundant word lines and two redundant bit lines. The test memory 4 also has a redundant area of the same capacity.

The test memory 4 embodied by SRAM.
FIG. 3 shows a first embodiment of this cell array. A large number of flip-flop type storage cells C are respectively connected to a pair of bit lines BL1 and BL1 to BL1 through a pair of transfer transistors TG.
It is connected to any pair of BLn and bar BLn.

The gate of the transfer transistor TG is connected to one of the word lines WL1 to WLm,
An m × n cell matrix is constructed. Therefore, based on the row address signal output from the test controller 3, a row decoder (not shown) uses the word line WL1.
When any of WLm to WLm is selected, the cell information stored in the memory cell C connected to the word line is read out to the bit line BL1, bars BL1 to BLn, bar BLn.

Bit line BL1, bars BL1 to BL
The cell information read out to the n and bar BLn is amplified by a sense amplifier (not shown), and cell information of any bit line is selected by a column decoder (not shown).
The read data RD2 is output to the test controller 3.

Two N-channel MOS transistors T for detecting cell information are provided at one node of each memory cell C.
The gates of n1 and Tn2 are connected. The transistor Tn
The sources of 1 and Tn2 are connected to the ground GND.

The drain of the transistor Tn1 provided in the memory cell C connected to the bit line in the same column is
The bit lines for detection BLk1 to BLkn provided in each column for detecting cell information are respectively connected.

The detection bit lines BLk1 to BLkn are connected to the power supply Vcc via the P-channel MOS transistor Tp1 having a small size, and the gate of the transistor Tp1 is connected to the ground GND. Therefore, the transistor Tp1 is always turned on in a high resistance state, and the detection bit line BLk1 is turned on unless the transistor Tn1 is turned on.
~ BLkn is maintained at the power supply Vcc level.

The drains of the transistors Tn2 provided in the memory cells C connected to the same word line have detection word lines WLk1 to WLkm provided in parallel with the word lines WL1 to WLm for detecting cell information. Connected to.

The detection word lines WLk1 to WLkm are connected to the power supply Vcc through the P-channel MOS transistor Tp2 having a small size, and the gate of the transistor Tp2 is connected to the ground GND. Therefore, the transistor Tp2 is always turned on in the high resistance state, and the word lines WLk1 to WLk are turned on unless the transistor Tn2 is turned on.
Hold km at the power supply Vcc level.

The test control unit 3 is provided in each memory cell C.
As a result, cell information in which one of the nodes to which the transistors Tn1 and Tn2 are connected becomes L level is written in advance.

Then, during the operation test of the memory under test 5, as abnormal data read from the defective cell of the memory under test 5, cell information in which one node to which the transistors Tn1 and Tn2 are connected becomes H level Is written.

Therefore, since the transistors Tn1 and Tn2 are turned on in the memory cell C storing abnormal data, the detection word line and the detection bit line connected to the memory cell C become L level.

With such a configuration, each of the detection word lines WLk1 to WLkm is at the H level only when normal data is stored in all the memory cells C connected to the detection word lines WLk1 to WLkm. The detection signals L1 to Lm are output to the test control unit 3.

If abnormal data is stored in one or more storage cells C among the storage cells C connected to the detection word lines WLk1 to WLkm, the detection word lines WL are detected.
k1 to WLkm output the L level detection signals L1 to Lm to the test control unit 3.

Similarly, each detection bit line BLk1 to BLkn
Outputs H level detection signals K1 to Kn to the test control unit 3 only when normal data is stored in all the memory cells C connected to the detection bit lines BLk1 to BLkn.

Further, if abnormal data is stored in one or more memory cells C among the memory cells C connected to the respective word lines BLk1 to BLkn for detection, each word line BL for detection is detected.
k1 to BLkn output the L level detection signals K1 to Kn to the test control unit 3.

Therefore, the test control unit 3 detects the detection signals L1 to L1.
With Lm and K1 to Kn, the word line and the bit line to which the memory cell storing the abnormal data is connected, in other words, the word line and the bit line to which the defective cell is connected can be detected in the memory under test 5. Has become.

Next, the test apparatus 2 configured as described above.
The operation will be described with reference to FIG. First, the test control unit 3 of the test apparatus 2 performs an operation test on all the memory cells of the memory under test 5 to generate the fail bit map 1 shown in FIG. 7 (step 21).

In other words, the test control section 3 controls the memory under test 5
When the abnormal data is detected from the read data, the abnormal data is stored in the corresponding address of the test memory 4. Then, the fail bit map 1 is generated on the test memory 4.

Next, the test controller 3 determines whether or not there is a defective cell based on the fail bit map 1 (step 22). If there is no defective cell, the redundant cell need not be set. Therefore, it is determined that the product is completely non-defective (step 23), and the test ends.

When there is a defective cell, the detection signals L1 to Lm, K1 to be output from the test memory 4 are detected.
The number of word lines and bit lines including defective cells is detected based on Kn (step 24).

Next, the number A of word lines including defective cells
And the number B of bit lines including defective cells are compared (step 25). For example, in FIG. 7, since the number of word lines including defective cells is “6” and the number of bit lines including defective cells is “5”, A> B.

Next, the test control section 3 calculates the number of defective cells of each bit line including the defective cell based on the fail bit map 1, and the bit line in the E column having the most defective cells is set to the redundant bit line R3. Replace (step 28).

Next, the test control section 3 detects whether or not there is a defective cell and whether or not a redundant area remains (steps 29 and 31). Now there are still bad cells,
Since the redundant area remains, the process proceeds to step 24.

Next, the test controller 3 detects that the number of word lines including defective cells is "3" and the number of bit lines including defective cells is "4", and A <B. Then, the test control unit 3 calculates the number of defective cells of each word line including the defective cell based on the fail bit map 1,
The word line of row C having the most defective cells is the redundant word line R1.
(Step 26).

Next, the test controller 3 detects that the defective cell still exists and that the redundant area remains (steps 29 and 31), and the number of word lines including the defective cell is "2", The number of bit lines including defective cells is "1"
It is detected that A> B.

Then, the test control section 3 replaces the bit line in the D row having the most defective cells with the redundant bit line R4 (step 26). Next, the test control unit 3 detects that there is no defective cell (step 29), determines repair completion (step 30), and ends the test.

In step 25, when the number A of word lines including defective cells and the number B of bit lines match, the remaining number C of redundant word lines and the remaining number D of redundant bit lines are set. Are compared (step 27).

If C> D, the process proceeds to step 26, and if C ≦ D, the process proceeds to step 28. If it is determined in step 31 that the redundant area does not remain, the defective cells cannot be relieved.
Is determined to be a defective chip (step 32), and the test ends.

As described above, the test memory 4 provided in the test apparatus 2 does not select the word lines WL1 to WLm and the bit lines BL1, the bars BL1 to BLn, and the bar BLn, and detects the detection word lines WLk1 to WLk1. Detection signals L1 to L output to WLkm and detection bit lines BLk1 to BLkn
The number of word lines and bit lines including defective cells can be detected based on m and K1 to Kn.

Therefore, without performing the read operation for selecting the word line and the bit line based on the address signal,
Since the number of word lines and bit lines including defective cells can be instantly detected, the test time can be shortened.

Further, based on the number of word lines and bit lines including defective cells, the word lines and bit lines including defective cells can be efficiently replaced with the minimum number of redundant word lines and redundant bit lines.

Further, since the number of redundant word lines and redundant bit lines to be replaced can be minimized, the yield of the memory under test can be improved and the number of redundant steps of the memory under test in the next process can be reduced. The cost can be reduced.

FIG. 5 shows a second embodiment of the test memory 4. In this embodiment, the detection word lines WLk1 to WLkm and the transistor Tn2 are removed from the first embodiment.

With this structure, the bit lines including the defective cells are detected by the detection signals K1 to Kn as in the first embodiment.
Can be detected based on. The word line including the defective cell can be detected by sequentially selecting each of the word lines WL1 to WLm and reading the cell information.

Therefore, it becomes possible to detect the number of word lines and bit lines including defective cells, and the test control unit 3
Thus, as in the first embodiment, the word lines and bit lines including defective cells can be efficiently replaced with the minimum number of redundant word lines and redundant bit lines.

In the above embodiment, the transistors Tn1 and Tn2 are connected to one node of the memory cell C to output the detection signals L1 to Lm and K1 to Kn. A signal may be taken out. In this case, the write node of the normal data and the abnormal data for the memory cell C can be inverted.

Further, the memory cell C can be similarly implemented with a configuration other than the flip-flop type. The detection signals L1 to Lm and K1 to Kn can also be generated by taking the OR logic or AND logic of the cell information of the memory cell C.

The technical ideas other than the claims that can be understood from the above-described embodiments will be described below along with their effects. (1) In claim 3, the switch circuit is composed of an N-channel MOS transistor having a gate connected to one node of the memory cell. When at least one node of the memory cells connected to the redundant word line and the redundant bit line via the switch circuit becomes H level due to abnormal data, the N-channel MOS transistor is turned on and the redundant word line and the redundant bit line are turned on. It becomes the ground GND level.

[0077]

As described in detail above, according to the inventions of claims 1 to 3, the operation test time of the semiconductor memory device can be shortened.

Further, according to the inventions of claims 4 and 5, it is possible to provide a test apparatus capable of shortening the operation test time of the semiconductor memory device. Further, in the inventions of claims 6 and 7, the operation test time of the semiconductor memory device can be shortened and the efficiency of the redundancy test can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a test apparatus.

FIG. 3 is a circuit diagram showing a first embodiment of a test memory.

FIG. 4 is a flowchart showing the operation of the test apparatus.

FIG. 5 is a circuit diagram showing a second embodiment of the test memory.

FIG. 6 is a flowchart showing the operation of the conventional test apparatus.

FIG. 7 is an explanatory diagram showing a cell matrix.

[Explanation of symbols]

 6 Cell information detection circuit BL, bar BL Bit line C Storage cell K detection signal

Claims (7)

[Claims] 1. A cell matrix is formed by connecting a word line and a bit line to a large number of memory cells, and selecting the memory cell by selecting the word line and the bit line. A semiconductor memory device performing a read operation, wherein a plurality of memory cells connected to a common bit line outputs a detection signal for detecting whether or not the cell information of the memory cells is the same, and cell information detection A semiconductor memory device, to which circuits are connected. 2. A word line and a bit line are respectively connected to a large number of memory cells to form a cell matrix, and the memory cell is selected by selecting the word line and the bit line. In a semiconductor memory device that performs a read operation, a plurality of memory cells connected to a common bit line includes a first cell information detection circuit that detects whether or not the cell information of the memory cells is the same. A plurality of memory cells connected to a common word line are provided with a second cell information detection circuit for detecting whether or not the cell information of the memory cells is the same. apparatus. 3. The first cell information detection circuit includes a detection bit line connected to a high potential side power source via a high resistance,
A plurality of switch circuits that are interposed between the detection bit line and a low-potential-side power supply and that are opened / closed based on the cell information stored in the memory cell, and detect the second cell information. The circuit is interposed between the detection word line and the low-potential-side power supply and connected to the high-potential-side power supply via a high resistance, and cell information stored in the memory cell is provided. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device comprises a plurality of switch circuits that are opened and closed based on the above. 4. A test control unit and a test memory are provided, wherein the test control unit writes cell information in the memory under test, reads the cell information written in the memory under test, and stores the cell information in the test memory. A test device of a semiconductor memory device for detecting a defective cell in a memory under test based on cell information stored in the test memory, wherein the test memory includes word lines and A bit line is connected to each other to form a cell matrix, the memory cell is selected by selecting the word line and the bit line, write and read operations are performed on the memory cell, and connected to a common bit line. A testing device for a semiconductor memory device, wherein the plurality of memory cells are provided with a cell information detection circuit for detecting whether or not the cell information of the memory cells is the same. 5. The test memory has a plurality of storage cells connected to a common bit line connected to a first cell information detection circuit for detecting whether or not the cell information of the storage cells is the same. The second cell information detection circuit for detecting whether or not the cell information of the storage cells is the same is connected to the plurality of storage cells connected to the common word line. A semiconductor memory device testing device as described above. 6. The test control unit detects the number of defective word lines including defective cells and defective bit lines including defective cells based on the output signals of the first and second cell information detection circuits. Of the defective bit line and defective word line
The line with the largest number of defective cells with the smaller number is replaced with the redundant line, and this operation is repeated to identify the redundant line that makes the defective word line and the defective bit line redundant, and the defective bit line and the defective word line are identified. 6. The semiconductor memory device testing device according to claim 5, further comprising a redundancy testing device for determining whether or not all defective cells can be repaired based on the number of redundant lines required for replacement. 7. The number of defective bit lines including defective cells is detected by detecting whether or not the cell information of a plurality of memory cells connected to the common bit line is the same, and the common word line is detected. The number of defective word lines including a defective cell is detected by detecting whether or not the cell information of a plurality of storage cells connected to each other is the same, and the number of defective word lines and defective word lines is detected. The line with the most defective cells, which has the smallest number of cells, is replaced with the redundant line, and this operation is repeated to identify the redundant line that makes the defective word line and the defective bit line redundant, and replaces the defective bit line with the defective word line. A method of testing a semiconductor memory device, comprising: determining whether or not all defective cells can be repaired based on the number of redundant lines required for the above.