JPH08305551A - Random number generator - Google Patents
Random number generatorInfo
- Publication number
- JPH08305551A JPH08305551A JP7128938A JP12893895A JPH08305551A JP H08305551 A JPH08305551 A JP H08305551A JP 7128938 A JP7128938 A JP 7128938A JP 12893895 A JP12893895 A JP 12893895A JP H08305551 A JPH08305551 A JP H08305551A
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- Prior art keywords
- random number
- circuit
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- circuits
- probability
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Links
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、論理“１”の発生確率
を制御することができる乱数発生装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random number generator capable of controlling the probability of occurrence of logic "1".
【０００２】[0002]
【従来の技術】論理“１”の発生確率を制御することが
できる従来の乱数発生装置の一例として、実開昭６２−
２０１８５８号に記載のものがある。図２はその先願に
記載されている乱数発生装置を示すブロック図である。2. Description of the Related Art As an example of a conventional random number generator capable of controlling the probability of occurrence of a logic "1", a real-life numbering machine 62-
There is one described in No. 2018858. FIG. 2 is a block diagram showing a random number generator described in that prior application.
【０００３】図２において、基本乱数発生回路１ａ〜１
ｃはそれぞれ確率１／２で論理“１”を発生する。ＡＮ
Ｄ回路２ａには基本乱数発生回路１ａ，１ｂの出力が入
力され、ＡＮＤ回路２ｂには基本乱数発生回路１ａ〜１
ｃの出力が入力される。確率設定回路３ａ〜３ｃはそれ
ぞれ“０”もしくは“１”に設定され、論理“０”もし
くは“１”を出力する。ＡＮＤ回路４ａには基本乱数発
生回路１ａの出力と確率設定回路３ａの出力が入力さ
れ、ＡＮＤ回路４ｂにはＡＮＤ回路２ａの出力と確率設
定回路３ｂの出力が入力され、ＡＮＤ回路４ｃにはＡＮ
Ｄ回路２ｂの出力と確率設定回路３ｃの出力が入力され
る。ＡＮＤ回路４ａ〜４ｃの出力はＯＲ回路５に入力さ
れ、このＯＲ回路５の出力が論理“１”の出現確率が制
御された出力Ｐとなる。In FIG. 2, basic random number generating circuits 1a to 1 are provided.
Each c produces a logic "1" with probability 1/2. AN
Outputs of the basic random number generating circuits 1a and 1b are input to the D circuit 2a, and basic random number generating circuits 1a to 1 are input to the AND circuit 2b.
The output of c is input. The probability setting circuits 3a to 3c are set to "0" or "1", respectively, and output logic "0" or "1". The AND circuit 4a receives the output of the basic random number generation circuit 1a and the output of the probability setting circuit 3a, the AND circuit 4b receives the output of the AND circuit 2a and the output of the probability setting circuit 3b, and the AND circuit 4c receives the AN signal.
The output of the D circuit 2b and the output of the probability setting circuit 3c are input. The outputs of the AND circuits 4a to 4c are input to the OR circuit 5, and the output of the OR circuit 5 becomes the output P in which the appearance probability of the logic "1" is controlled.
【０００４】この従来の乱数発生装置において、確率設
定回路３ａが“１”に設定されると、出力Ｐが論理
“１”となる確率は１／２となり、確率設定回路３ｂが
“１”に設定されると、出力Ｐが論理“１”となる確率
は１／４となり、確率設定回路３ｃが“１”に設定され
ると、出力Ｐが論理“１”となる確率は１／８となる。
即ち、図２に示す従来の乱数発生装置では、論理“１”
の発生確率を１／２，１／４，１／８から選択すること
ができる。なお、基本乱数発生回路１（１ａ〜１ｃ），
ＡＮＤ回路２（２ａ，２ｂ），確率設定回路３（３ａ〜
３ｃ），ＡＮＤ回路４（４ａ〜４ｃ）を増やせば、論理
“１”の発生確率を１／２n （ｎは正の整数）から選択
することが可能となる。In this conventional random number generator, when the probability setting circuit 3a is set to "1", the probability that the output P becomes the logic "1" becomes 1/2, and the probability setting circuit 3b becomes "1". When set, the probability that the output P will be a logical "1" is 1/4, and when the probability setting circuit 3c is set to "1", the probability that the output P will be a logical "1" is 1/8. Become.
That is, in the conventional random number generator shown in FIG.
The occurrence probability of can be selected from 1/2, 1/4, and 1/8. In addition, the basic random number generation circuit 1 (1a to 1c),
AND circuit 2 (2a, 2b), probability setting circuit 3 (3a-
3c) and the number of AND circuits 4 (4a to 4c) is increased, it becomes possible to select the probability of occurrence of logic "1" from 1/2 n (n is a positive integer).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た従来の乱数発生装置では、例えば確率設定回路３ａ〜
３ｃの全てを“１”に設定したとしても、出力Ｐが論理
“１”となる確率は１／２であり、６／８，７／８のよ
うにｍ／８（ｍは正の整数）という任意の確率を指定す
ることはできないという問題点がある。本発明はこのよ
うな問題点に鑑みなされたものであり、論理“１”をｍ
／２n（ｍ，ｎは正の整数）の発生確率で発生すること
ができる乱数発生装置を提供することを目的とする。However, in the above-described conventional random number generator, for example, the probability setting circuits 3a ...
Even if all 3c are set to "1", the probability that the output P will be a logical "1" is 1/2, and m / 8 (m is a positive integer) like 6/8 and 7/8. There is a problem that it is not possible to specify an arbitrary probability. The present invention has been made in view of such problems, and the logic "1" is set to m.
It is an object of the present invention to provide a random number generator capable of generating with a probability of occurrence of / 2 n (m and n are positive integers).
【０００６】[0006]
【課題を解決するための手段】本発明は、上述した従来
の技術の課題を解決するため、所定の確率で論理“１”
を発生する複数個の基本乱数発生回路（１１ａ〜１１
ｃ）よりなる基本乱数発生部（１１）と、前記基本乱数
発生部におけるそれぞれの基本乱数発生回路の出力が供
給される乱数決定回路（１２ａ〜１２ｃ）を複数個縦方
向に接続した乱数決定部（１２）と、前記乱数決定部に
おけるそれぞれの乱数決定回路の出力が供給される乱数
加算回路（１３ａ〜１３ｃ）を複数個縦方向に接続した
乱数加算部（１３）と、前記乱数加算部におけるそれぞ
れの乱数加算回路に論理“０”もしくは“１”を入力し
て論理“１”の最終的な発生確率を設定する確率設定部
（１４）とを備え、前記乱数決定部は、それぞれの乱数
決定回路において前段の前記基本乱数発生回路より論理
“０”が供給されると論理“０”を前記乱数加算部に出
力する手段と、前段の前記基本乱数発生回路より論理
“１”が供給される縦方向最初の乱数決定回路のみが論
理“１”を前記乱数加算部に出力する共に、それより縦
方向後段の乱数決定回路の全てが前段の前記基本乱数発
生回路の出力にかかわらず論理“０”を前記乱数加算部
に出力する手段とを有し、前記乱数加算部は、それぞれ
の乱数加算回路において前記乱数決定回路の出力と前記
確率設定部の出力とのＡＮＤをとると共に、その全ての
ＯＲをとることにより前記最終的な発生確率にて論理
“１”を発生する手段を有することを特徴とする乱数発
生装置を提供するものである。In order to solve the above-mentioned problems of the conventional technique, the present invention has a predetermined probability of logical "1".
A plurality of basic random number generation circuits (11a-11
and a plurality of random number determining circuits (12a to 12c) to which outputs of the respective basic random number generating circuits in the basic random number generating unit are connected in the vertical direction. (12), a random number addition unit (13) in which a plurality of random number addition circuits (13a to 13c) to which outputs of the respective random number determination circuits in the random number determination unit are connected in the vertical direction, and the random number addition unit And a probability setting unit (14) for inputting a logical "0" or "1" to each random number addition circuit and setting a final occurrence probability of the logical "1". In the deciding circuit, a means for outputting a logical "0" to the random number adder when the logic "0" is supplied from the preceding basic random number generating circuit, and a logic "1" is supplied from the preceding basic random number generating circuit. Ru Only the first random number determining circuit in the direction outputs a logical "1" to the random number adding unit, and all the random number determining circuits in the subsequent vertical direction are logical "0" regardless of the output of the basic random number generating circuit in the previous stage. Is output to the random number addition unit, and the random number addition unit performs AND of the output of the random number determination circuit and the output of the probability setting unit in each random number addition circuit, and all ORs thereof. By providing the above, there is provided a random number generator characterized in that it has means for generating a logical "1" at the final occurrence probability.
【０００７】[0007]
【実施例】以下、本発明の乱数発生装置について、添付
図面を参照して説明する。図１は本発明の乱数発生装置
の一実施例を示すブロック図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A random number generator of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a random number generator of the present invention.
【０００８】本発明の乱数発生装置は、図１に示すよう
に、基本乱数発生部１１，乱数決定部１２，乱数加算部
１３，確率設定部１４より構成される。本実施例では、
基本乱数発生部１１は３つの基本乱数発生回路１１ａ〜
１１ｃを備え、乱数決定部１２は３つの乱数決定回路１
２ａ〜１２ｃを備える。乱数加算部１３は３つの乱数加
算回路１３ａ〜１３ｃを備え、確率設定部１４は３つの
確率設定回路１４ａ〜１４ｃを備える。乱数決定回路１
２ａ〜１２ｃ，乱数加算回路１３ａ〜１３ｃは後述する
ように縦方向にも接続されている。As shown in FIG. 1, the random number generating device of the present invention comprises a basic random number generating section 11, a random number determining section 12, a random number adding section 13, and a probability setting section 14. In this embodiment,
The basic random number generator 11 includes three basic random number generating circuits 11a to 11a.
11c, the random number determination unit 12 includes three random number determination circuits 1
2a to 12c. The random number addition unit 13 includes three random number addition circuits 13a to 13c, and the probability setting unit 14 includes three probability setting circuits 14a to 14c. Random number determination circuit 1
2a to 12c and random number adding circuits 13a to 13c are also connected in the vertical direction as described later.
【０００９】図１において、基本乱数発生回路１１ａ〜
１１ｃはそれぞれ例えば確率１／２で論理“１”を発生
する。基本乱数発生回路１１ａ〜１１ｃの出力は乱数決
定回路１２ａ〜１２ｃに入力される。乱数決定回路１２
ａ〜１２ｃはそれぞれＡＮＤ回路１２１と一方が反転入
力されるＡＮＤ回路１２２とを備えて構成される。乱数
決定回路１２ａにおけるＡＮＤ回路１２１の一方の入力
には端子Ｓ１２より常時“１”が入力され、もう一方の
入力には基本乱数発生回路１１ａの出力が入力される。
乱数決定回路１２ａにおけるＡＮＤ回路１２２の一方の
入力には端子Ｓ１２より常時“１”が入力され、もう一
方の入力には基本乱数発生回路１１ａの出力が反転され
て入力される。In FIG. 1, basic random number generating circuits 11a-
11c each generate a logic "1" with a probability of 1/2, for example. The outputs of the basic random number generation circuits 11a to 11c are input to the random number determination circuits 12a to 12c. Random number determination circuit 12
Each of a to 12c includes an AND circuit 121 and an AND circuit 122, one of which is inverted. In the random number determining circuit 12a, one input of the AND circuit 121 is constantly input with "1" from the terminal S12, and the other input is input with the output of the basic random number generating circuit 11a.
In the random number determination circuit 12a, one input of the AND circuit 122 is constantly input with "1" from the terminal S12, and the other input is inverted and input with the output of the basic random number generation circuit 11a.
【００１０】また、乱数決定回路１２ｂにおけるＡＮＤ
回路１２１の一方の入力には乱数決定回路１２ａ中のＡ
ＮＤ回路１２２の出力が入力され、もう一方の入力には
基本乱数発生回路１１ｂの出力が入力される。乱数決定
回路１２ｂにおけるＡＮＤ回路１２２の一方の入力には
乱数決定回路１２ａ中のＡＮＤ回路１２２の出力が入力
され、もう一方の入力には基本乱数発生回路１１ｂの出
力が反転されて入力される。同様に、乱数決定回路１２
ｃにおけるＡＮＤ回路１２１の一方の入力には乱数決定
回路１２ｂ中のＡＮＤ回路１２２の出力が入力され、も
う一方の入力には基本乱数発生回路１１ｃの出力が入力
される。乱数決定回路１２ｃにおけるＡＮＤ回路１２２
の一方の入力には乱数決定回路１２ｂ中のＡＮＤ回路１
２２の出力が入力され、もう一方の入力には基本乱数発
生回路１１ｃの出力が反転されて入力される。Further, AND in the random number determination circuit 12b
One of the inputs of the circuit 121 is A in the random number determination circuit 12a.
The output of the ND circuit 122 is input, and the output of the basic random number generation circuit 11b is input to the other input. The output of the AND circuit 122 in the random number determination circuit 12a is input to one input of the AND circuit 122 in the random number determination circuit 12b, and the output of the basic random number generation circuit 11b is inverted and input to the other input. Similarly, the random number determination circuit 12
The output of the AND circuit 122 in the random number determination circuit 12b is input to one input of the AND circuit 121 in c, and the output of the basic random number generation circuit 11c is input to the other input. AND circuit 122 in random number determination circuit 12c
AND circuit 1 in the random number determination circuit 12b has one input
The output of the basic random number generation circuit 11c is inverted and input to the other input.
【００１１】乱数決定回路１２ａ〜１２ｃの出力は乱数
加算回路１３ａ〜１３ｃに入力される。乱数加算回路１
３ａ〜１３ｃはそれぞれＡＮＤ回路１３１とＯＲ回路１
３２とを備えて構成される。乱数加算回路１３ａにおけ
るＡＮＤ回路１３１の一方の入力には確率設定回路１４
ａの出力が入力され、もう一方の入力には乱数決定回路
１２ａ中のＡＮＤ回路１２１の出力が入力される。乱数
加算回路１３ａにおけるＯＲ回路１３２の一方の入力に
はＡＮＤ回路１３１の出力が入力され、もう一方の入力
には端子Ｓ１３より“０”（もしくは“１”）が入力さ
れる。The outputs of the random number determining circuits 12a-12c are input to the random number adding circuits 13a-13c. Random number addition circuit 1
3a to 13c are an AND circuit 131 and an OR circuit 1 respectively.
And 32. The probability setting circuit 14 is connected to one input of the AND circuit 131 in the random number addition circuit 13a.
The output of a is input, and the output of the AND circuit 121 in the random number determination circuit 12a is input to the other input. The output of the AND circuit 131 is input to one input of the OR circuit 132 in the random number addition circuit 13a, and "0" (or "1") is input to the other input from the terminal S13.
【００１２】また、乱数加算回路１３ｂにおけるＡＮＤ
回路１３１の一方の入力には確率設定回路１４ｂの出力
が入力され、もう一方の入力には乱数決定回路１２ｂ中
のＡＮＤ回路１２１の出力が入力される。乱数加算回路
１３ｂにおけるＯＲ回路１３２の一方の入力にはＡＮＤ
回路１３１の出力が入力され、もう一方の入力には乱数
加算回路１３ａ中のＯＲ回路１３２の出力が入力され
る。同様に、乱数加算回路１３ｃにおけるＡＮＤ回路１
３１の一方の入力には確率設定回路１４ｃの出力が入力
され、もう一方の入力には乱数決定回路１２ｃ中のＡＮ
Ｄ回路１２１の出力が入力される。乱数加算回路１３ｃ
におけるＯＲ回路１３２の一方の入力にはＡＮＤ回路１
３１の出力が入力され、もう一方の入力には乱数加算回
路１３ｂ中のＯＲ回路１３２の出力が入力される。そし
て、このＯＲ回路１３２の出力が論理“１”の発生確率
が制御された出力Ｐとなる。Further, AND in the random number addition circuit 13b
The output of the probability setting circuit 14b is input to one input of the circuit 131, and the output of the AND circuit 121 in the random number determination circuit 12b is input to the other input. AND is applied to one input of the OR circuit 132 in the random number addition circuit 13b.
The output of the circuit 131 is input, and the output of the OR circuit 132 in the random number addition circuit 13a is input to the other input. Similarly, the AND circuit 1 in the random number addition circuit 13c
The output of the probability setting circuit 14c is input to one input of 31 and the AN in the random number determining circuit 12c is input to the other input.
The output of the D circuit 121 is input. Random number addition circuit 13c
AND circuit 1 is connected to one input of the OR circuit 132 in
The output of 31 is input, and the output of the OR circuit 132 in the random number addition circuit 13b is input to the other input. Then, the output of the OR circuit 132 becomes the output P in which the occurrence probability of the logic "1" is controlled.
【００１３】確率設定回路１４ａ〜１４ｃはそれぞれ
“０”もしくは“１”に設定され、論理“０”もしくは
“１”を出力する。The probability setting circuits 14a to 14c are set to "0" or "1", respectively, and output logic "0" or "1".
【００１４】以上のように構成される本発明の乱数発生
装置において、基本乱数発生回路１１ａの出力が“１”
の時、乱数決定回路１２ａ中のＡＮＤ回路１２１の出力
は“１”、ＡＮＤ回路１２２の出力は“０”となるの
で、基本乱数発生回路１１ｂ，１１ｃの出力が“０”で
あろうとも“１”であろうとも、乱数決定回路１２ａ〜
１２ｃにおけるＡＮＤ回路１２１の出力はそれぞれ
“１”，“０”，“０”となる。In the random number generator of the present invention configured as described above, the output of the basic random number generation circuit 11a is "1".
At this time, the output of the AND circuit 121 in the random number determination circuit 12a is "1", and the output of the AND circuit 122 is "0". Therefore, even if the outputs of the basic random number generation circuits 11b and 11c are "0", Even if it is 1 ", the random number determination circuit 12a-
The outputs of the AND circuit 121 in 12c are "1", "0", and "0", respectively.
【００１５】同様にして、基本乱数発生回路１１ａの出
力が“０”で、基本乱数発生回路１１ｂの出力が“１”
の時は、基本乱数発生回路１１ｃの出力が“０”であろ
うとも“１”であろうとも、乱数決定回路１２ａ〜１２
ｃにおけるＡＮＤ回路１２１の出力はそれぞれ“０”，
“１”，“０”となる。基本乱数発生回路１１ａ，１１
ｂの出力が“０”で、基本乱数発生回路１１ｃの出力が
“１”の時は、乱数決定回路１２ａ〜１２ｃにおけるＡ
ＮＤ回路１２１の出力はそれぞれ“０”，“０”，
“１”となる。即ち、この構成においては、基本乱数発
生部１における１つの基本乱数発生回路（１１ａ〜１１
ｃ）のいずれかに“１”が発生すると、その“１”が発
生した基本乱数発生回路に接続された乱数決定回路（１
２ａ〜１２ｃ）より縦方向後段の乱数決定回路における
ＡＮＤ回路１２１の出力は全て“０”となることが分か
る。Similarly, the output of the basic random number generating circuit 11a is "0" and the output of the basic random number generating circuit 11b is "1".
At this time, whether the output of the basic random number generation circuit 11c is "0" or "1", the random number determination circuits 12a to 12
The output of the AND circuit 121 in c is "0",
It becomes "1" and "0". Basic random number generation circuits 11a, 11
When the output of b is "0" and the output of the basic random number generation circuit 11c is "1", A in the random number determination circuits 12a to 12c.
The outputs of the ND circuit 121 are "0", "0",
It becomes “1”. That is, in this configuration, one basic random number generation circuit (11a to 11) in the basic random number generation unit 1 is used.
When "1" occurs in any of c), the random number determination circuit (1
2a to 12c), it can be seen that the outputs of the AND circuit 121 in the random number determination circuit in the subsequent stage in the vertical direction are all "0".
【００１６】以上をまとめると、基本乱数発生回路１１
ａ〜１１ｃの出力が（１，？，？）となる確率は１／２
で、この時、乱数決定回路１２ａ〜１２ｃにおけるＡＮ
Ｄ回路１２１の出力は（１，０，０）となる。なお、
“？”は“０”でも“１”でもよいことを示している。
基本乱数発生回路１１ａ〜１１ｃの出力が（０，１，
？）となる確率は１／４で、この時、乱数決定回路１２
ａ〜１２ｃにおけるＡＮＤ回路１２１の出力は（０，
１，０）となる。基本乱数発生回路１１ａ〜１１ｃの出
力が（０，０，１）となる確率は１／８で、この時、乱
数決定回路１２ａ〜１２ｃにおけるＡＮＤ回路１２１の
出力は（０，０，１）となる。To summarize the above, the basic random number generation circuit 11
The probability that the output of a to 11c becomes (1,?,?) is 1/2
Then, at this time, the AN in the random number determination circuits 12a to 12c
The output of the D circuit 121 is (1, 0, 0). In addition,
"?" Indicates that "0" or "1" may be used.
The outputs of the basic random number generation circuits 11a to 11c are (0, 1,
? ) Is 1/4, and at this time, the random number determination circuit 12
The output of the AND circuit 121 in a to 12c is (0,
1,0). The probability that the outputs of the basic random number generation circuits 11a to 11c are (0, 0, 1) is 1/8, and at this time, the output of the AND circuit 121 in the random number determination circuits 12a to 12c is (0, 0, 1). Become.
【００１７】乱数加算回路１３ａ〜１３ｃは確率設定回
路１４ａ〜１４ｃの出力と乱数決定回路１２ａ〜１２ｃ
中のＡＮＤ回路１２１の出力とのＡＮＤをとり、その全
てのＯＲをとる構成である。従って、乱数加算回路１３
ａ中のＯＲ回路１３２に端子Ｓ１３より“０”が入力さ
れている時、乱数加算回路１３ｃ中のＯＲ回路１３２か
らの出力Ｐが論理“１”となる確率は、確率設定回路１
４ａ〜１４ｃの設定によって表１のようになる。なお、
表１において、設定値は確率設定回路１４ａ〜１４ｃの
出力値を表している。この表１より分かるように、本発
明の乱数発生装置では、ｍ／８の確率で論理“１”を発
生することができる。The random number adding circuits 13a to 13c output the probability setting circuits 14a to 14c and the random number determining circuits 12a to 12c.
The configuration is such that AND with the output of the AND circuit 121 in the inside is taken and all the ORs thereof are taken. Therefore, the random number addition circuit 13
When "0" is input from the terminal S13 to the OR circuit 132 in a, the probability that the output P from the OR circuit 132 in the random number addition circuit 13c becomes the logic "1" is determined by the probability setting circuit 1
Table 1 is obtained according to the settings of 4a to 14c. In addition,
In Table 1, the set value represents the output value of the probability setting circuits 14a to 14c. As can be seen from Table 1, the random number generator of the present invention can generate a logic "1" with a probability of m / 8.
【００１８】[0018]
【表１】 [Table 1]
【００１９】なお、端子Ｓ１３より“１”を入力する
と、乱数加算回路１３ａ中のＯＲ回路１３２の出力が
“１”となり、縦方向後段の乱数加算回路１３ｂ，１３
ｃ中のＯＲ回路１３２の出力も“１”となるので、出力
Ｐは確率設定回路１４ａ〜１４ｃの設定にかかわらず常
に“１”となる。なお、本実施例では端子Ｓ１３より信
号を入力するように構成しているが、確率設定部１４に
おける確率設定回路をもう１つ増やし、その１つを乱数
加算回路１３ａ中のＯＲ回路１３２に入力する確率設定
信号としてもよい。When "1" is input from the terminal S13, the output of the OR circuit 132 in the random number addition circuit 13a becomes "1", and the random number addition circuits 13b and 13 in the subsequent stage in the vertical direction.
Since the output of the OR circuit 132 in c is also "1", the output P is always "1" regardless of the settings of the probability setting circuits 14a to 14c. Although the signal is input from the terminal S13 in this embodiment, the number of probability setting circuits in the probability setting unit 14 is increased by one and the one is input to the OR circuit 132 in the random number addition circuit 13a. It may be a probability setting signal.
【００２０】以上説明した本実施例では、基本乱数発生
部１１，乱数決定部１２，乱数加算部１３におけるそれ
ぞれの回路を縦方向に３つ並べた構成であるので、論理
“１”を発生する確率はｍ／８となるが、縦方向にそれ
ぞれの回路を４つ並べればｍ／１６、縦方向に５つ並べ
ればｍ／３２のように、論理“１”の発生確率をｍ／２
n （ｍ，ｎは正の整数）で発生することができる。勿
論、この時、確率設定部１４における確率設定回路は縦
方向に並べた回路の数に応じて増やすことは当然であ
る。なお、図１において、確率設定部１４は便宜上３つ
の確率設定回路１４ａ〜１４ｃを並べて構成している
が、実際には３ビットの２進数を発生させ、その最上位
ビットを確率設定回路１４ａの出力、中央のビットを確
率設定回路１４ｂの出力、最下位ビットを確率設定回路
１４ｃの出力とすればよい。In the present embodiment described above, since the respective circuits of the basic random number generator 11, the random number determiner 12, and the random number adder 13 are arranged in the vertical direction, a logic "1" is generated. The probability is m / 8, but if four circuits are arranged in the vertical direction, then m / 16, and if five circuits are arranged in the vertical direction, m / 32, the probability of occurrence of logic “1” is m / 2.
n (m and n are positive integers). Of course, at this time, the number of probability setting circuits in the probability setting unit 14 is naturally increased according to the number of circuits arranged in the vertical direction. Note that, in FIG. 1, the probability setting unit 14 is configured by arranging three probability setting circuits 14a to 14c for convenience, but in reality, a 3-bit binary number is generated, and the most significant bit thereof is stored in the probability setting circuit 14a. The output, the central bit may be the output of the probability setting circuit 14b, and the least significant bit may be the output of the probability setting circuit 14c.
【００２１】本発明の乱数発生装置は、ｍ／２n の発生
確率で論理“１”を発生することができる特長を有する
他に、ｍ／１６，ｍ／３２のように発生確率を異ならせ
る際には、基本乱数発生回路１１，乱数決定回路１２，
乱数加算回路１３を縦方向に増やしていくだけでよいと
いう特長も有している。また、回路構成もＡＮＤ回路や
ＯＲ回路等を用いた簡単な構成であるので、安価に実現
できる。The random number generator of the present invention has the feature that it can generate a logical "1" with a probability of occurrence of m / 2 n , and has different occurrence probabilities such as m / 16 and m / 32. At that time, the basic random number generation circuit 11, the random number determination circuit 12,
It also has the feature that it is sufficient to increase the random number addition circuit 13 in the vertical direction. Further, the circuit configuration is a simple configuration using an AND circuit, an OR circuit, etc., so that it can be realized at low cost.
【００２２】[0022]
【発明の効果】以上詳細に説明したように、本発明の乱
数発生装置は、所定の確率で論理“１”を発生する複数
個の基本乱数発生回路よりなる基本乱数発生部と、前記
基本乱数発生部におけるそれぞれの基本乱数発生回路の
出力が供給される乱数決定回路を複数個縦方向に接続し
た乱数決定部と、前記乱数決定部におけるそれぞれの乱
数決定回路の出力が供給される乱数加算回路を複数個縦
方向に接続した乱数加算部と、前記乱数加算部における
それぞれの乱数加算回路に論理“０”もしくは“１”を
入力して論理“１”の最終的な発生確率を設定する確率
設定部とを備え、前記乱数決定部は、それぞれの乱数決
定回路において前段の前記基本乱数発生回路より論理
“０”が供給されると論理“０”を前記乱数加算部に出
力する手段と、前段の前記基本乱数発生回路より論理
“１”が供給される縦方向最初の乱数決定回路のみが論
理“１”を前記乱数加算部に出力する共に、それより縦
方向後段の乱数決定回路の全てが前段の前記基本乱数発
生回路の出力にかかわらず論理“０”を前記乱数加算部
に出力する手段とを有し、前記乱数加算部は、それぞれ
の乱数加算回路において前記乱数決定回路の出力と前記
確率設定部の出力とのＡＮＤをとると共に、その全ての
ＯＲをとることにより前記最終的な発生確率にて論理
“１”を発生する手段を有するので、論理“１”をｍ／
２n （ｍ，ｎは正の整数）の発生確率で発生することが
できるという特長を有する。As described above in detail, the random number generating device of the present invention includes a basic random number generating section including a plurality of basic random number generating circuits that generate a logic "1" with a predetermined probability, and the basic random number. A random number determining section in which a plurality of random number determining circuits to which the outputs of the respective basic random number generating circuits in the generating section are connected are vertically connected, and a random number adding circuit to which outputs of the respective random number determining circuits in the random number determining section are supplied. Probability of setting a final occurrence probability of a logical "1" by inputting a logical "0" or "1" into a random number adding section in which a plurality of vertical lines are connected and each random number adding circuit in the random number adding section. A setting unit, wherein the random number determination unit outputs a logical "0" to the random number addition unit when a logical "0" is supplied from the basic random number generation circuit in the preceding stage in each random number determination circuit; Front stage Only the first random number determination circuit in the vertical direction supplied with the logic "1" from the basic random number generation circuit outputs the logic "1" to the random number addition unit, and all the random number determination circuits in the subsequent stages in the vertical direction from the previous stage. Means for outputting a logical "0" to the random number addition unit regardless of the output of the basic random number generation circuit, and the random number addition unit outputs the output of the random number determination circuit and the probability in each random number addition circuit. Since there is a means for generating a logical "1" at the final occurrence probability by taking the AND with the output of the setting unit and taking the OR of all of them, the logical "1" is m / m.
It has a feature that it can be generated with an occurrence probability of 2 n (m and n are positive integers).
【図１】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
【図２】従来例を示すブロック図である。FIG. 2 is a block diagram showing a conventional example.
１１ 基本乱数発生部 １１ａ〜１１ｃ 基本乱数発生回路 １２ 乱数決定部 １２ａ〜１２ｃ 乱数決定回路 １３ 乱数加算部 １３ａ〜１３ｃ 乱数加算回路 １４ 確率設定部 １４ａ〜１４ｃ 確率設定回路 11 Basic Random Number Generation Units 11a to 11c Basic Random Number Generation Circuits 12 Random Number Determination Units 12a to 12c Random Number Determination Circuits 13 Random Number Addition Units 13a to 13c Random Number Addition Circuits 14 Probability Setting Units 14a to 14c Probability Setting Circuits
Claims (1)
の基本乱数発生回路よりなる基本乱数発生部と、 前記基本乱数発生部におけるそれぞれの基本乱数発生回
路の出力が供給される乱数決定回路を複数個縦方向に接
続した乱数決定部と、 前記乱数決定部におけるそれぞれの乱数決定回路の出力
が供給される乱数加算回路を複数個縦方向に接続した乱
数加算部と、 前記乱数加算部におけるそれぞれの乱数加算回路に論理
“０”もしくは“１”を入力して論理“１”の最終的な
発生確率を設定する確率設定部とを備え、 前記乱数決定部は、それぞれの乱数決定回路において前
段の前記基本乱数発生回路より論理“０”が供給される
と論理“０”を前記乱数加算部に出力する手段と、前段
の前記基本乱数発生回路より論理“１”が供給される縦
方向最初の乱数決定回路のみが論理“１”を前記乱数加
算部に出力する共に、それより縦方向後段の乱数決定回
路の全てが前段の前記基本乱数発生回路の出力にかかわ
らず論理“０”を前記乱数加算部に出力する手段とを有
し、 前記乱数加算部は、それぞれの乱数加算回路において前
記乱数決定回路の出力と前記確率設定部の出力とのＡＮ
Ｄをとると共に、その全てのＯＲをとることにより前記
最終的な発生確率にて論理“１”を発生する手段を有す
ることを特徴とする乱数発生装置。1. A basic random number generator comprising a plurality of basic random number generators that generate a logic "1" with a predetermined probability, and a random number to which the output of each basic random number generator in the basic random number generator is supplied. A random number determining unit in which a plurality of determining circuits are connected in the vertical direction; a random number adding unit in which a plurality of random number adding circuits to which the outputs of the random number determining circuits in the random number determining unit are connected in the vertical direction; And a probability setting unit that inputs a logical “0” or “1” to each random number addition circuit in the unit to set the final occurrence probability of the logical “1”, and the random number determination unit determines each random number. In the circuit, when the logic "0" is supplied from the preceding basic random number generating circuit, a means for outputting the logic "0" to the random number adding unit and the logic "1" are supplied from the preceding basic random number generating circuit. Vertical Only the first random number determining circuit in the direction outputs a logical "1" to the random number adding unit, and all the random number determining circuits in the subsequent vertical direction are logical "0" regardless of the output of the basic random number generating circuit in the previous stage. For outputting to the random number addition section, the random number addition section outputs the AN of the output of the random number determination circuit and the output of the probability setting section in each random number addition circuit.
A random number generator having means for generating a logical "1" at the final occurrence probability by taking D and taking all ORs thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7128938A JPH08305551A (en) | 1995-04-27 | 1995-04-27 | Random number generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7128938A JPH08305551A (en) | 1995-04-27 | 1995-04-27 | Random number generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08305551A true JPH08305551A (en) | 1996-11-22 |
Family
ID=14997125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7128938A Pending JPH08305551A (en) | 1995-04-27 | 1995-04-27 | Random number generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08305551A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002037260A1 (en) * | 2000-10-24 | 2002-05-10 | Hmi Co., Ltd. | Random number generator |
| JP2005086670A (en) * | 2003-09-10 | 2005-03-31 | Toshiba Corp | Encryption / decryption module |
| JP2016071862A (en) * | 2014-09-22 | 2016-05-09 | 株式会社東芝 | String processor |
-
1995
- 1995-04-27 JP JP7128938A patent/JPH08305551A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002037260A1 (en) * | 2000-10-24 | 2002-05-10 | Hmi Co., Ltd. | Random number generator |
| US7124157B2 (en) | 2000-10-24 | 2006-10-17 | Hmi Co., Ltd. | Random number generator |
| KR100845928B1 (en) * | 2000-10-24 | 2008-07-11 | 가부시키가이샤 에이치.에무.아이 | Random number generator |
| JP2005086670A (en) * | 2003-09-10 | 2005-03-31 | Toshiba Corp | Encryption / decryption module |
| JP2016071862A (en) * | 2014-09-22 | 2016-05-09 | 株式会社東芝 | String processor |
| US10095661B2 (en) | 2014-09-22 | 2018-10-09 | Kabushiki Kaisha Toshiba | String processor |
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