JPH08306871A - Method for manufacturing dielectric capacitor - Google Patents
Method for manufacturing dielectric capacitorInfo
- Publication number
- JPH08306871A JPH08306871A JP7129783A JP12978395A JPH08306871A JP H08306871 A JPH08306871 A JP H08306871A JP 7129783 A JP7129783 A JP 7129783A JP 12978395 A JP12978395 A JP 12978395A JP H08306871 A JPH08306871 A JP H08306871A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask
- sio
- etching
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
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Abstract
(57)【要約】
【目的】 誘電体キャパシタによる段差を少なくし且つ
この誘電体キャパシタを低コストで製造する。
【構成】 下部電極のパターンのSiO2 膜36をマス
クにしてPt膜35及びPZT膜34をエッチングした
後、SiO2 膜36を上部電極のパターンにし、このS
iO2 膜36をマスクにしてPt膜35をエッチングす
ると共に、PZT膜34をマスクにしてPt膜33及び
TiN膜32をエッチングする。つまり、SiO2 膜3
6をマスクとして共用しており、両方のエッチングによ
ってSiO2 膜36の膜厚が減少し、SiO2 膜36が
残る範囲も狭い。また、SiO2 膜36の形成工程も1
回でよい。
(57) [Abstract] [Purpose] To reduce the step due to a dielectric capacitor and to manufacture this dielectric capacitor at low cost. [Structure] The Pt film 35 and the PZT film 34 are etched using the SiO 2 film 36 having the pattern of the lower electrode as a mask, and then the SiO 2 film 36 is patterned as the upper electrode.
The Pt film 35 is etched using the iO 2 film 36 as a mask, and the Pt film 33 and the TiN film 32 are etched using the PZT film 34 as a mask. That is, the SiO 2 film 3
6 is shared as a mask, the film thickness of the SiO 2 film 36 is reduced by both the etching, narrow range SiO 2 film 36 is left. Further, the step of forming the SiO 2 film 36 is also 1
It's enough.
Description
【0001】[0001]
【産業上の利用分野】本発明は、上部電極、下部電極及
び誘電体膜を有する誘電体キャパシタの製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dielectric capacitor having an upper electrode, a lower electrode and a dielectric film.
【0002】[0002]
【従来の技術】各種の膜等のパターニングに際しては、
従来から、リソグラフィでレジストを所望のパターンに
加工し、このレジストをマスクにしてエッチングを行う
ことが多用されている。2. Description of the Related Art When patterning various films,
Conventionally, it is often used to process a resist into a desired pattern by lithography and perform etching using this resist as a mask.
【0003】しかし、誘電体膜としてペロブスカイト型
誘電体膜を用いる誘電体キャパシタでは、その電極とし
て一般に高融点貴金属膜が用いられており、高融点貴金
属膜のエッチングに際しては、レジストとの選択比が低
く、エッチング種と高融点貴金属との反応性を高めるた
めにウェハを300℃程度の高温にする必要もある。こ
のため、レジストはエッチングのマスクに適しておら
ず、SiO2 膜やSOG膜等の無機膜がエッチングのマ
スクとして用いられている。However, in a dielectric capacitor using a perovskite type dielectric film as a dielectric film, a refractory noble metal film is generally used as an electrode of the dielectric capacitor. It is low, and it is necessary to raise the temperature of the wafer to a high temperature of about 300 ° C. in order to enhance the reactivity between the etching species and the high melting point noble metal. For this reason, the resist is not suitable as an etching mask, and an inorganic film such as a SiO 2 film or an SOG film is used as an etching mask.
【0004】図2は、上述の様な誘電体キャパシタの製
造方法の一従来例を示している。この一従来例では、図
2(a)に示す様に、下地の層間絶縁膜11上に、層間
絶縁膜11に対する密着層12、高融点貴金属膜13、
誘電体膜14、高融点貴金属膜15及び無機膜16を順
次に堆積させる。FIG. 2 shows a conventional example of a method of manufacturing the dielectric capacitor as described above. In this conventional example, as shown in FIG. 2A, an adhesion layer 12, a high melting point noble metal film 13 with respect to the interlayer insulating film 11 is formed on the underlying interlayer insulating film 11.
The dielectric film 14, the high melting point noble metal film 15 and the inorganic film 16 are sequentially deposited.
【0005】次に、図2(b)に示す様に、無機膜16
上でリソグラフィによってレジスト17を上部電極のパ
ターンに加工し、このレジスト17をマスクにして無機
膜16をエッチングする。そして、図2(c)に示す様
に、レジスト17を除去した後、無機膜16をマスクに
して高融点貴金属膜15をエッチングする。Next, as shown in FIG. 2B, the inorganic film 16
The resist 17 is processed into the pattern of the upper electrode by lithography, and the inorganic film 16 is etched using the resist 17 as a mask. Then, as shown in FIG. 2C, after removing the resist 17, the high melting point noble metal film 15 is etched using the inorganic film 16 as a mask.
【0006】次に、図2(d)に示す様に、無機膜16
とは別の無機膜21を堆積させ、この無機膜21上でリ
ソグラフィによってレジスト22を下部電極のパターン
に加工する。そして、図2(e)に示す様に、レジスト
22をマスクにして無機膜21をエッチングし、レジス
ト22を除去した後、無機膜21をマスクにして誘電体
膜14、高融点貴金属膜13及び密着層12を連続的に
エッチングして、この誘電体キャパシタ23を完成させ
る。Next, as shown in FIG. 2D, the inorganic film 16
An inorganic film 21 other than the above is deposited, and the resist 22 is processed into a pattern of the lower electrode on the inorganic film 21 by lithography. Then, as shown in FIG. 2E, the inorganic film 21 is etched by using the resist 22 as a mask to remove the resist 22, and then the dielectric film 14, the high melting point noble metal film 13 and the inorganic film 21 are used as a mask. The adhesion layer 12 is continuously etched to complete the dielectric capacitor 23.
【0007】[0007]
【発明が解決しようとする課題】ところで、無機膜1
6、21はレジスト17、22の様には容易に除去する
ことができないので、通常は、誘電体キャパシタ23上
に残される。しかし、2層の無機膜16、21が誘電体
キャパシタ23上に残っていると、この誘電体キャパシ
タ23による段差が大きい。このため、上述の一従来例
では、後のCVD法による層間絶縁膜(図示せず)の堆
積やその平坦化が容易でなかった。By the way, the inorganic film 1
Since the resists 6 and 21 cannot be easily removed like the resists 17 and 22, they are usually left on the dielectric capacitor 23. However, if the two layers of inorganic films 16 and 21 remain on the dielectric capacitor 23, the step due to the dielectric capacitor 23 is large. For this reason, in the above-described conventional example, it is not easy to deposit an interlayer insulating film (not shown) or planarize the interlayer insulating film by the CVD method.
【0008】[0008]
【課題を解決するための手段】請求項1の誘電体キャパ
シタの製造方法は、第1の導電膜、誘電体膜及び第2の
導電膜を順次に積層させる工程と、下部電極のパターン
の無機膜を前記第2の導電膜上に形成する工程と、前記
無機膜をマスクにして前記第2の導電膜及び前記誘電体
膜をエッチングする工程と、前記エッチングの後に前記
無機膜を上部電極のパターンに加工する工程と、前記上
部電極のパターンの前記無機膜をマスクにして前記第2
の導電膜をエッチングすると共に、前記誘電体膜をマス
クにして前記第1の導電膜をエッチングする工程とを具
備することを特徴としている。According to a first aspect of the present invention, there is provided a method of manufacturing a dielectric capacitor, which comprises a step of sequentially laminating a first conductive film, a dielectric film and a second conductive film, and an inorganic layer of a lower electrode pattern. A step of forming a film on the second conductive film, a step of etching the second conductive film and the dielectric film using the inorganic film as a mask, and a step of etching the inorganic film as an upper electrode after the etching. A step of processing into a pattern, and the second film using the inorganic film of the pattern of the upper electrode as a mask
And etching the first conductive film using the dielectric film as a mask.
【0009】請求項2の誘電体キャパシタの製造方法
は、請求項1の誘電体キャパシタの製造方法において、
前記誘電体膜としてペロブスカイト型誘電体膜を用いる
ことを特徴としている。A method of manufacturing a dielectric capacitor according to a second aspect is the method of manufacturing a dielectric capacitor according to the first aspect,
A feature is that a perovskite type dielectric film is used as the dielectric film.
【0010】請求項3の誘電体キャパシタの製造方法
は、請求項2の誘電体キャパシタの製造方法において、
前記ペロブスカイト型誘電体膜としてPZT膜を用い、
前記第1及び第2の導電膜としてPt膜を用いることを
特徴としている。A method of manufacturing a dielectric capacitor according to a third aspect is the method of manufacturing a dielectric capacitor according to the second aspect,
A PZT film is used as the perovskite type dielectric film,
A Pt film is used as the first and second conductive films.
【0011】[0011]
【作用】本発明による誘電体キャパシタの製造方法で
は、上部電極及び下部電極のエッチングに際して同一の
無機膜をマスクとして共用しており、しかも、上部電極
及び下部電極の両方のエッチングによって無機膜の膜厚
が減少するので、エッチングの終了後に残る無機膜の膜
厚が薄い。In the method of manufacturing a dielectric capacitor according to the present invention, the same inorganic film is shared as a mask when etching the upper electrode and the lower electrode, and the film of the inorganic film is formed by etching both the upper electrode and the lower electrode. Since the thickness is reduced, the inorganic film remaining after the etching is thin.
【0012】また、無機膜は当初は下部電極のパターン
にするが後に上部電極のパターンにするので、上部電極
のパターンでしか無機膜が残らず、エッチングの終了後
に残る無機膜の範囲が狭い。Further, since the inorganic film initially has the pattern of the lower electrode, but later has the pattern of the upper electrode, the inorganic film remains only in the pattern of the upper electrode, and the range of the inorganic film remaining after the etching is narrow.
【0013】また、上部電極及び下部電極のエッチング
に際して同一の無機膜をマスクとして共用しているの
で、マスクとしての無機膜の形成工程が1回でよく、工
程数が少ない。Further, since the same inorganic film is used as a mask when etching the upper electrode and the lower electrode, the inorganic film as a mask may be formed only once, and the number of steps is small.
【0014】[0014]
【実施例】以下、本発明の一実施例を、図1を参照しな
がら説明する。本実施例では、図1(a)に示す様に、
下地の層間絶縁膜31上に、膜厚が200nmであり層
間絶縁膜31に対する密着層としてのTiN膜32、膜
厚が200nmのPt膜33、膜厚が200nmのPZ
T膜34、膜厚が200nmのPt膜35及び膜厚が1
μmでありCVD法によるSiO2 膜36を順次に堆積
させる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In this embodiment, as shown in FIG.
A TiN film 32 having a thickness of 200 nm and serving as an adhesion layer to the interlayer insulating film 31, a Pt film 33 having a thickness of 200 nm, and a PZ having a thickness of 200 nm are formed on the underlying interlayer insulating film 31.
T film 34, Pt film 35 with a film thickness of 200 nm, and film thickness 1
A SiO 2 film 36 having a thickness of μm is sequentially deposited by the CVD method.
【0015】次に、図1(b)に示す様に、SiO2 膜
36上でリソグラフィによってレジスト37を下部電極
のパターンに加工し、このレジスト37をマスクにして
SiO2 膜36をエッチングする。Next, as shown in FIG. 1B, a resist 37 is processed into a pattern of a lower electrode on the SiO 2 film 36 by lithography, and the SiO 2 film 36 is etched using the resist 37 as a mask.
【0016】次に、図1(c)に示す様に、レジスト3
7を除去した後、SiO2 膜36をマスクにして、O2
/Cl2 混合ガスでPt膜35をエッチングし、更に、
Cl2 /Ar混合ガスで及びPZT膜34をエッチング
する。なお、これらのエッチングによってSiO2 膜3
6も膜厚方向へある程度までエッチングされるが、後に
行うエッチングに対するマスクとしての十分な膜厚は残
っている。Next, as shown in FIG. 1C, the resist 3
After removing 7, the SiO 2 film 36 is used as a mask to remove O 2
Etching the Pt film 35 with a mixed gas of / Cl 2 and
The PZT film 34 is etched with a Cl 2 / Ar mixed gas. The SiO 2 film 3 is formed by these etchings.
6 is also etched to some extent in the film thickness direction, but a sufficient film thickness remains as a mask for etching performed later.
【0017】次に、図1(d)に示す様に、SiO2 膜
36上でリソグラフィによってレジスト42を上部電極
のパターンに加工し、このレジスト42をマスクにして
SiO2 膜36をエッチングする。Next, as shown in FIG. 1D, a resist 42 is processed into a pattern of an upper electrode on the SiO 2 film 36 by lithography, and the SiO 2 film 36 is etched using the resist 42 as a mask.
【0018】次に、図1(e)に示す様に、レジスト4
2を除去した後、O2 /Cl2 混合ガスで、SiO2 膜
36をマスクにしてPt膜35をエッチングすると共に
PZT膜34をマスクにしてPt膜33をエッチング
し、更に、PZT膜34をマスクにしてF系ガスでTi
N膜32をエッチングして、この誘電体キャパシタ43
を完成させる。Next, as shown in FIG. 1E, the resist 4
After removing 2, Pt film 35 is etched with O 2 / Cl 2 mixed gas using SiO 2 film 36 as a mask, Pt film 33 is etched with PZT film 34 as a mask, and PZT film 34 is further removed. Use the F-based gas as a mask and Ti
The dielectric film 43 is etched by etching the N film 32.
To complete.
【0019】以上の様な実施例では、SiO2 膜36
は、図1(c)の工程におけるPt膜35及びPZT膜
34のエッチングと、図1(e)の工程におけるPt膜
35のエッチングとの、両方のマスクになっている。こ
のため、既述の一従来例のうちで図2(c)の工程にお
ける高融点貴金属膜15のエッチングのマスクにしかな
っていない無機膜16の最終的な膜厚よりも、SiO2
膜36の最終的な膜厚の方が薄い。In the above embodiment, the SiO 2 film 36 is used.
Serves as a mask for both the etching of the Pt film 35 and the PZT film 34 in the step of FIG. 1C and the etching of the Pt film 35 in the step of FIG. Therefore, in the above-mentioned conventional example, the SiO 2 film is more than the final film thickness of the inorganic film 16 which only serves as a mask for etching the refractory noble metal film 15 in the step of FIG.
The final film thickness of the film 36 is thinner.
【0020】しかも、図1(e)からも明らかな様に、
誘電体キャパシタ43全体のパターンつまり下部電極の
パターンではなく、上部電極のみのパターンで、1層の
SiO2 膜36が残るだけである。従って、本実施例で
は、誘電体キャパシタ43による段差が少なく、後のC
VD法による層間絶縁膜(図示せず)の堆積やその平坦
化が容易である。Moreover, as is clear from FIG. 1 (e),
The entire pattern of the dielectric capacitor 43, that is, the pattern of the lower electrode, but the pattern of only the upper electrode, leaves only one layer of the SiO 2 film 36. Therefore, in this embodiment, the step due to the dielectric capacitor 43 is small, and C
It is easy to deposit an interlayer insulating film (not shown) and flatten it by the VD method.
【0021】[0021]
【発明の効果】本発明による誘電体キャパシタの製造方
法では、上部電極及び下部電極のエッチングの終了後に
残るマスクとしての無機膜の膜厚が薄く且つその範囲が
狭いので、誘電体キャパシタによる段差が少なく、その
後の層間絶縁膜の堆積やその平坦化が容易である。ま
た、マスクとしての無機膜の形成工程が1回でよく、工
程数が少ないので、誘電体キャパシタを低コストで製造
することができる。In the method of manufacturing a dielectric capacitor according to the present invention, since the thickness of the inorganic film as a mask remaining after the etching of the upper electrode and the lower electrode is thin and its range is narrow, a step due to the dielectric capacitor is not generated. It is small, and the subsequent deposition of the interlayer insulating film and its flattening are easy. Further, since the step of forming the inorganic film as the mask only needs to be performed once and the number of steps is small, the dielectric capacitor can be manufactured at low cost.
【図1】本発明の一実施例を工程順に示す側断面図であ
る。FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.
【図2】本発明の一従来例を工程順に示す側断面図であ
る。FIG. 2 is a side sectional view showing a conventional example of the present invention in the order of steps.
32 TiN膜 33 Pt膜 34 PZT膜 35 Pt膜 36 SiO2 膜 43 誘電体キャパシタ32 TiN film 33 Pt film 34 PZT film 35 Pt film 36 SiO 2 film 43 Dielectric capacitor
Claims (3)
膜を順次に積層させる工程と、 下部電極のパターンの無機膜を前記第2の導電膜上に形
成する工程と、 前記無機膜をマスクにして前記第2の導電膜及び前記誘
電体膜をエッチングする工程と、 前記エッチングの後に前記無機膜を上部電極のパターン
に加工する工程と、 前記上部電極のパターンの前記無機膜をマスクにして前
記第2の導電膜をエッチングすると共に、前記誘電体膜
をマスクにして前記第1の導電膜をエッチングする工程
とを具備することを特徴とする誘電体キャパシタの製造
方法。1. A step of sequentially laminating a first conductive film, a dielectric film, and a second conductive film; a step of forming an inorganic film having a pattern of a lower electrode on the second conductive film; A step of etching the second conductive film and the dielectric film using an inorganic film as a mask; a step of processing the inorganic film into a pattern of an upper electrode after the etching; the inorganic film having a pattern of the upper electrode And etching the second conductive film using the mask as a mask, and etching the first conductive film using the dielectric film as a mask.
電体膜を用いることを特徴とする請求項1記載の誘電体
キャパシタの製造方法。2. The method of manufacturing a dielectric capacitor according to claim 1, wherein a perovskite type dielectric film is used as the dielectric film.
ZT膜を用い、 前記第1及び第2の導電膜としてPt膜を用いることを
特徴とする請求項2記載の誘電体キャパシタの製造方
法。3. The P as the perovskite type dielectric film
3. The method of manufacturing a dielectric capacitor according to claim 2, wherein a ZT film is used and a Pt film is used as the first and second conductive films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12978395A JP3348564B2 (en) | 1995-04-28 | 1995-04-28 | Method for manufacturing dielectric capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12978395A JP3348564B2 (en) | 1995-04-28 | 1995-04-28 | Method for manufacturing dielectric capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08306871A true JPH08306871A (en) | 1996-11-22 |
| JP3348564B2 JP3348564B2 (en) | 2002-11-20 |
Family
ID=15018120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12978395A Expired - Fee Related JP3348564B2 (en) | 1995-04-28 | 1995-04-28 | Method for manufacturing dielectric capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3348564B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002094019A (en) * | 2000-09-18 | 2002-03-29 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| KR100321721B1 (en) * | 1998-12-30 | 2002-06-20 | 박종섭 | Ferroelectric Capacitor Manufacturing Method for Etching Ferroelectric Film and Electrode Double Film Simultaneously |
| KR100353807B1 (en) * | 1999-12-28 | 2002-09-26 | 주식회사 하이닉스반도체 | A method for forming lower electrode of high dielectrics capacitor |
| EP1305824A4 (en) * | 2000-06-06 | 2007-07-25 | Univ Fraser Simon | METHOD FOR MANUFACTURING ELECTRONIC MATERIALS |
-
1995
- 1995-04-28 JP JP12978395A patent/JP3348564B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100321721B1 (en) * | 1998-12-30 | 2002-06-20 | 박종섭 | Ferroelectric Capacitor Manufacturing Method for Etching Ferroelectric Film and Electrode Double Film Simultaneously |
| KR100353807B1 (en) * | 1999-12-28 | 2002-09-26 | 주식회사 하이닉스반도체 | A method for forming lower electrode of high dielectrics capacitor |
| EP1305824A4 (en) * | 2000-06-06 | 2007-07-25 | Univ Fraser Simon | METHOD FOR MANUFACTURING ELECTRONIC MATERIALS |
| JP2002094019A (en) * | 2000-09-18 | 2002-03-29 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3348564B2 (en) | 2002-11-20 |
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Legal Events
| Date | Code | Title | Description |
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| LAPS | Cancellation because of no payment of annual fees |