JPH08307236A - Drive device and semiconductor device using the drive device - Google Patents

Abstract

(57) [Abstract] [Purpose] The level conversion circuit that converts a small signal amplitude to a full amplitude reduces variations in the delay time between rising and falling, and operates at high speed. [Structure] Two sets of CMOS current mirror type level conversion circuits 10p and 10n are provided, and an input signal of the level conversion circuit is twisted between the two sets so that the outputs of the two sets of level conversion circuits become complementary signals. The pull-up circuit 40 is driven by the output of one level conversion circuit, and the pull-down circuit 50 is driven by the output of the other level conversion circuit. Since the number of stages for driving the pull-up circuit 40 and the pull-down circuit 50 is the same, it is possible to suppress variations in delay time between rising and falling.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device and a semiconductor device equipped with this drive device, and more particularly, it is suitable for driving a heavy load by converting a small signal amplitude into a CMOS level by mixing bipolar and CMOS. Drive device and semiconductor device.

[0002]

2. Description of the Related Art A level conversion circuit based on a CMOS current mirror is widely used as a method for converting a signal having a small amplitude into a signal having a full amplitude. Generally, a CMOS current mirror type level conversion circuit causes a DC current to flow, and therefore, there is a problem that the consumption current remarkably increases when the driving force is increased. Therefore, a method is adopted in which a driver is provided in the subsequent stage of the level conversion circuit to increase the driving force. BiCM
In OS LSI, as a driver for driving a high load,
A BiCMOS driver, which has a higher driving force than the CMOS driver, is used. With the recent decrease in power supply voltage, a BiCMOS driver has been replaced as a driver circuit, and as shown in FIG.
-NMOS inverters have been used.

Incidentally, there is "Electronics Technical Report" Vol.93, No.75, p.42, which is related to the prior art.

[0004]

According to the above-mentioned conventional technique, a heavy load can be driven by the level-converted output signal even when the power supply voltage becomes low. However, Bi
-NMOS inverter is a pull-down means NMO
Although S is directly driven, the NPN bipolar transistor (hereinafter referred to as NPN transistor) which is the pull-up means is driven through the CMOS inverter, so the pull-up delay time is longer than the pull-down delay time. There is a problem of being late.

Further, after the NMOS of the pull-down means is turned on, the NPN transistor is turned off before the NPN transistor is turned off.
The delay time of the CMOS inverter for driving the transistor is required. Therefore, during this delay time, the NPN transistor and the pull-down NMOS are both turned on and a through current flows.

An object of the present invention is to provide a drive device having a small through current and a semiconductor device using the same, by speeding up the control of the pull-up means of the driver circuit provided in the output stage of the level conversion to suppress the imbalance of the delay time. To provide.

[0007]

The above object is to provide two sets of CMOS current mirror type level conversion circuits,
One set is used for positive signal output and the other set is used for negative signal output, and two sets of level conversion circuits generate complementary signals of amplitude.
This is achieved by comprising a MOS and an NPN transistor for pull-up, inputting a negative signal to the gate of the NMOS, and inputting a positive signal to the base of the NPN transistor to drive the output load.

[0008]

Since the driving of the pull-up NPN transistor is directly driven by the output of the level conversion circuit, the pull-up delay time can be shortened. Also, for pull-down N
Since the driving timings of the MOS and the pull-up NPN transistor can be made uniform, it is possible to suppress the imbalance of the delay time of the rise and fall of the driver output. Furthermore, NPN transistor and pull-down N
It is possible to reduce the through current flowing between it and the MOS.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram of a drive device according to an embodiment of the present invention. 1 is a small amplitude complementary signal, 10
p is a level conversion circuit for outputting a positive signal, 10n is a level conversion circuit for outputting a negative signal, and 20p is a level conversion circuit 1.
0p is a positive signal output, 20n is a negative signal output of the level conversion circuit 10n, and 30 is a driver circuit for inputting complementary signals to control the pull-up means and the pull-down means to drive the load 2.

The small-amplitude complementary signal 1 is supplied to the level conversion circuit 10
Complementary signals (20p and 2) amplified by p and 10n
Level converted to 0n). The level-converted complementary signal is input to the driver circuit 30 and directly controls the pull-up means 40 and the pull-down means 50 in the driver circuit 30. Since the pull-up means 40 and the pull-down means 50 are simultaneously controlled in this manner, the driver circuit 3
The difference in the delay time between the rise and fall of the 0 output is suppressed.

By suppressing the difference in delay time, the delay time on the slow side can be shortened and the speed can be increased. Further, since the pull-up means 40 and the pull-down means 50 are not turned on at the same time, the through current can be suppressed and the consumption current can be reduced.

FIG. 2 is a specific circuit diagram in which the drive device shown in FIG. 1 is used for single-ended output. Reference numeral 1 is a small amplitude complementary signal, 10p and 10n are CMOS current mirror type level conversion circuits, 30 is an NPN transistor 40 as a pull-up means, and NM is a pull-down means 50.
It is a driver circuit configured by the OS.

In order to generate complementary signals 20p and 20n of full amplitude in phase (with no switching timing deviation) from the complementary signal 1 of small amplitude, the level conversion circuit 1 is used.
It is necessary to match the rising and falling delay times of the outputs of 0p and 10n. Therefore, it becomes possible by matching the driving forces of the pull-up means (Mp2 in 10p) and the pull-down means (Mn2 in 10p) at the output stage of the level conversion circuit.

At 10p, in order to match the driving force of Mn2, the device constants of the CMOS level conversion circuit may be set in the relationship as shown in the following equation (1). Driving force of Mp1 × driving force of Mn2 = driving force of Mp2 × driving force of Mn1 (1) Here, the driving force is W (gate width) of the MOS device.
/ L (gate length). In this way, by matching the delay times of the rise and fall of the level conversion circuit, the timing of control by the complementary signals of the driver 32 is matched, so high-speed control of load driving and reduction of current consumption can be achieved.

FIG. 3 is a specific circuit diagram of still another drive device of the present invention. 3 is an ECL input signal, 4 is a reference signal, 60 is an ECL current switch, 70 is an emitter follower pair, 1 is a small amplitude complementary signal, 10p and 1
0n is a level conversion circuit, and 31p and 31n are driver circuits.

The ECL input signal 3 and the reference signal 4 are input to the ECL current switch 60, and the output of the current switch 60 is downshifted by 1 Vbe by the emitter follower pair 70 to generate the complementary signal 1 having a small amplitude. The small amplitude complementary signal 1 is input to the level conversion circuits 10p and 10n. The input signals of 10p and 10n are input in a twisted relationship, and the output signals of 10p and 10n are in an inverted signal relationship with each other. Output 2 of level conversion circuit
0p and 20n are amplified to almost full amplitude level. The driver circuits 31p and 31n are controlled by 20p and 20n which are complementary signals of full amplitude.

Here, the control of the driver circuit 31p will be described. First, consider the case where 20p rises and 20n falls. Before switching the signal, 20p is "L".
At the "o" level, 20p is at the "Hi" level. In the driver circuit 31p, Qp and 41p which are pull-up means.
Is off and only the pull-down means 51p is on. Therefore, the load 2p of the drive circuit 31p is Vee.
It has been pulled down to a level. 20p rises,
When 20n falls, the pull-up means and the pull-down means are controlled at the same time, so the pull-down means is turned off and the pull-up means is turned on to drive the drive circuit 31.
The load 2p of p is pulled up to the Vcc level. 20
When p falls and 20n rises, the reverse operation is performed.

According to this embodiment, the pull-up means and the pull-down means are directly controlled by the output signal of the level conversion circuit and at the same timing, so that the load driving can be controlled at high speed. Further, since the pull-up means and the pull-down means are not turned on at the same time, the shoot-through current can be suppressed and the current consumption can be reduced.

FIG. 4 is a diagram showing an example of a driver circuit that can be used in the drive device of the embodiment of the present invention.
As the driver circuit for driving a load that is controlled using complementary signals, there are three types of circuits. Reference numeral 33 is an example in which NPN transistors are used for both pull-up means and pull-down means, which is effective when the power supply voltage is as high as about 5.0V. Reference numeral 34 is an example in which NMOS is used for both the pull-up means and the pull-down means, and is effective when the threshold value of the next stage is determined from the low potential power supply. Reference numeral 35 is an example in which PMOS is used for both the pull-up means and the pull-down means, which is effective when the threshold voltage of the next stage is determined from the high potential power supply.

Since the drive device described above can control the pull-up means and the pull-down means at the same timing, it is possible to convert the level of a small amplitude signal into a full amplitude signal having a uniform phase.

FIG. 6 is a block diagram of a synchronous SRAM in which the drive device according to the embodiment of the present invention is used as a clock buffer. A0 to An are address signal input terminals, D1 to Dm are data input terminals, WE is a write enable signal input terminal, CS is a chip selector signal input terminal, CLK is a clock signal input terminal, and Q1 to Qm are data output terminals. 101 is an input register for address,
102 is a data input register, 103 is a WE register, 104 is a CS register, 105 and 106 are clock buffer circuits, 107 is a row decoder, 108 is a column decoder, 109 is a memory cell matrix, 11
2 is a write amplifier, 113 is a sense amplifier, 114 is an output register, and 115 is an output buffer.

The synchronous SRAM controls the fetching of an input signal with a clock signal. Further, when the input / output specifications are register-register (RR) type, the output of the output data is also controlled by the clock signal. In this embodiment, the clock input signal is a small signal amplitude (eg PEC).
L) level, input / output other than clock is LV-CMOS
The case of the level will be described as an example.

The clock signal is supplied to the clock buffer circuit 10.
5 and 106 into the chip. In this embodiment, clock signals of complementary signals are used for the WE register, SS register and output register. A single-phase clock is supplied from the clock buffer 106, and complementary clock signals are supplied from the clock buffer 105. The signal of the address register is supplied to the row decoder 107 and the column decoder 10 by the single-phase clock signal 121.
8 is supplied. A memory cell in the memory matrix 109 is selected by the row decoder 107 and the column decoder 108. In the read state, the sense amplifier 1
The read signal is amplified by 13 and output to the output register 114. In the write state, the write amplifier 1
Data is written in the memory cell by 12. The output register 114 takes in the data from the sense amplifier 113 and then is controlled by the complementary clock signal 120 to output the data to the output buffer.

In the present embodiment, by using the circuit shown in FIG. 3 as the clock buffer circuit 105 for outputting a complementary signal, the write enable system control signal can be controlled at high speed. Further, by speeding up the complementary signals for controlling the output register, the access time from the rising edge of the clock to the data output can be speeded up. The circuit shown in FIG.
Although it is a complementary signal input, by applying a reference potential to one end of the input, it also corresponds to a single-ended input clock buffer of the memory shown in FIG. Further, although the single end output is used for the clock signal from the outside in the present embodiment, the complementary signal (double end) input may be used. Further, although the present embodiment shows an example of the I / O separate type in which the input and output are divided, the present invention is not limited to the I / O common type.

[0025]

According to the present invention, since the pull-up circuit and the pull-down circuit of the drive device can be controlled at the same timing, the NPN transistor which is the pull-up means can be controlled at a higher speed than the driver circuit using the Bi-NMOS inverter. The drive device can be speeded up and the through current can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a drive device according to an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the drive device shown in FIG.

FIG. 3 is a specific circuit diagram of a drive device according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of a driver circuit that can be used in the drive device according to the embodiment of the invention.

FIG. 5 is a synchronous S in which the drive device according to the embodiment of the present invention is applied to a clock buffer for outputting a complementary signal.
It is a block diagram of RAM.

FIG. 6 is a configuration diagram of a conventional drive device.

[Explanation of symbols]

Vcc ... High potential power supply, Vee ... Low potential power supply, 1 ... Small amplitude complementary signal, 2, 2p, 2n ... Driver circuit output, 3 ...
ECL input signal, 4 ... Reference signal, 10, 10
p, 10n, 11p, 11n ... Level conversion circuit, 20
p, 20n ... Level conversion circuit output, 30, 31p, 31
n ... Driver circuit, 40 ... Pull-up means, 50 ... Pull-down means, 60 ... ECL current switch, 70 ... Emitter follower, Q, Qp, Qn ... NPN bipolar transistor, Mp, Mp # ... PMOS transistor, M
n, Mn # ... PMOS transistor, 105 ... Clock buffer for outputting complementary signal.

Claims (11)

[Claims] 1. A small-amplitude complementary signal, a first level conversion circuit that inputs the complementary signal, amplifies the amplitude, and outputs a single-phase signal, and a signal that is out of phase with the first level conversion circuit. A drive device, comprising: a second level conversion circuit for controlling the load; and a driver circuit for inputting the output of the first level conversion circuit and the output of the second level conversion circuit to drive a load. 2. A small-amplitude complementary signal, a first level conversion circuit that inputs the complementary signal, amplifies the amplitude, and outputs a single-phase signal, and a signal that is out of phase with the first level conversion circuit. A second level conversion circuit, a first driver circuit for inputting the first level conversion circuit output and the second level conversion circuit output to drive a load, the second level conversion circuit output and the first level And a second driver circuit that inputs a conversion circuit output and drives a load with a signal of a reverse phase of the first driver circuit. 3. The pull-up means and the pull-down means of the driver circuit according to claim 1 or 2,
A drive device characterized by being a MOS. 4. The pull-up means and the pull-down means of a driver circuit according to claim 1 or 2,
A drive device characterized by being a MOS. 5. The pull-up means and the pull-down means of the driver circuit according to claim 1 or 2, are both N.
A drive device characterized by being a PN bipolar transistor. 6. A drive device according to claim 1, wherein the pull-up means of the driver circuit is an NPN bipolar transistor and the pull-down means is an NMOS. 7. The drive device according to claim 1, wherein the pull-up means of the driver circuit is an NPN bipolar transistor and a PMOS, and the pull-down means is an NMOS. 8. The drive device according to claim 1, further comprising a unit that generates the complementary signal from a single-phase signal. 9. The driver circuit according to claim 1, further comprising a pull-up means and a pull-down means, wherein the input signal is a complementary signal. 10. A semiconductor device having a load driven by complementary signals, wherein the drive device according to any one of claims 1 to 8 is incorporated. 11. A synchronous SRAM comprising a clock buffer which receives a clock input and generates a complementary clock signal from the clock, a memory matrix, and a register which is driven based on the complementary clock signal to read and write the memory matrix, The synchronous SR, wherein the drive device according to any one of claims 1 to 8 is provided as the clock buffer.
AM.