JPH08307833A - Image data interpolation circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] When a frame image is generated from a field image by pixel interpolation, the purpose is to continuously generate interpolated pixel data at the time of image data input to reduce the number of access to the field memory. To do. A memory 2 for storing input image data, a shift register 4, which holds a pixel data group of pixels surrounding interpolation pixels based on the input image data and the image data read from the memory 2. 5, a group of arithmetic units 6 to 9 which outputs the arithmetic result as a judgment material of the surrounding pixel pattern from the outputs of the shift registers 4 and 5, and a group of flags 10 which holds the arithmetic result of the arithmetic units 6 to 9.
13, an interpolation determination unit 14 that determines an interpolation method based on the outputs of the flag groups 10 to 13, and a unit that generates interpolation pixel data by the determined interpolation method and stores the interpolation pixel data in the memory 2 (interpolation calculation unit). 15 and a switching unit 16).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data interpolation circuit.

[0002]

2. Description of the Related Art A video signal such as an NTSC broadcasting system adopts an interlace system, and one frame screen is composed of two field screens. Since there is a time difference of 1/60 seconds in this field screen, when a frame image is printed out by a video printer, in the case of a moving image, the quality of the printout image deteriorates due to the time difference. is there.

Therefore, it is considered that a frame screen is generated by performing scanning line interpolation processing on one field screen and the frame image is printed out by a video printer.

The scanning line interpolation process is as follows.
An adaptive scanning line interpolation process has been proposed in order to eliminate the jaggedness at the contour portion due to the linear interpolation process. In this adaptive scanning line interpolation processing, for example, six interpolation reference pixels that are close to the interpolation pixel are extracted, an average value of the maximum value and the minimum value is calculated from the extracted interpolation reference pixels, and the average value is calculated. Is set as a threshold value, the interpolation reference pixel is binarized, the binarized result is collated with a predetermined pattern table to determine the interpolation direction, and the average value of pixel pairs in the decided interpolation direction is calculated. Is used to generate interpolated pixel data.

[0005]

However, when the above-mentioned interpolation pixel data is generated, for example, if the pixel data in the field memory is sequentially accessed, it is necessary to access the memory six times to generate one interpolation pixel. Therefore, the power consumption increases and the circuit becomes complicated. Further, in Japanese Laid-Open Patent Publication No. 4-188987, six interpolation reference pixels that are close to the interpolation pixel are extracted, and average values are obtained in the cross interpolation direction and the upper and lower interpolation directions of the six pixels. , An image processing apparatus has been proposed in which these average values are subjected to predetermined weighting or the like to generate interpolated pixel data, and the circuit configuration thereof is shown. When inputting data, it is necessary to access the field memory separately.

In view of the above circumstances, it is an object of the present invention to continuously generate interpolation pixel data when inputting image data and reduce the number of times of access to the field memory.

[0007]

An image data interpolation circuit according to the present invention comprises a storage means for storing input image data, an interpolation pixel for storing the input image data and the image data read from the storage means. Shift register held as a pixel data group of surrounding pixels, an arithmetic unit group that outputs an operation result that is a judgment material of the peripheral pixel pattern from the output of the shift register, and a flag group that holds the operation result of the arithmetic unit group And an interpolation method determination unit that determines an interpolation method based on the flag contents of the flag group, and a unit that generates interpolation pixel data by the determined interpolation method and stores the interpolation pixel data in the storage unit. To do.

Further, the image data interpolation circuit of the present invention stores the input image data and the input image data and the image data read from the storage unit in the surrounding pixels of the interpolation pixel. A current pixel shift register held as a pixel data group, a temporary interpolation pixel shift register holding a temporary interpolation pixel data group,
An arithmetic unit group that outputs an arithmetic result serving as a judgment material of the surrounding pixel pattern from the outputs of the current pixel shift register and the temporary interpolation pixel shift register, a flag group that holds the arithmetic result of the arithmetic unit group, and the flag The interpolation method for generating the temporary interpolation pixel data is determined as the first processing based on the flag content of the group, and the interpolation method for generating the final interpolation pixel data is also used as the second processing by using the temporary interpolation pixel data. And a temporary interpolation pixel data is generated as the first processing by the determined interpolation method and stored in the temporary interpolation pixel shift register, and the final interpolation pixel data is stored as the second processing. Means for generating and storing in the storage means.

[0009]

According to the first configuration, when the image data is input, each pixel data that is sequentially input is stored in the register,
Since the flag information is sequentially generated from the pixel data stored in this register, the interpolation method is sequentially determined by this flag information, and the sequential interpolation pixel data is generated, it is not necessary to access the memory one by one when generating the interpolation pixel data. , The number of memory accesses can be reduced.

Further, in the case where the temporary interpolation pixel data is generated in the first processing and the final interpolation pixel data is generated using the temporary interpolation pixel data in the second processing as in the second configuration. Also, similarly to the above, since the number of times of accessing the memory can be reduced and it is not necessary to increase the storage means by one scanning line for processing twice, a high quality image can be obtained with less pixel data without increasing power consumption. Can be obtained.

[0011]

【Example】

(Embodiment 1) The present invention will be described below with reference to the drawings showing the embodiment.

FIG. 1 is a block diagram showing an image data interpolation circuit of this embodiment. The input switching unit 1 inputs pixel data read from a field memory (not shown), for example, and alternately switches and supplies the pixel data to either the first memory unit 2a or the second memory unit 2b in the memory 2. .

The memory 2 includes a first memory section 2a and a second memory section 2a.
It comprises a memory unit 2b and a third memory unit 2c, and each of these memory units 2a to 2c has a memory capacity capable of storing pixel data for one line. First memory unit 2
a and the second memory unit 2b store current pixel data,
Interpolation pixel data is stored in the third memory unit 2c as described later. The outputs of the memory units 2a to 2c are
It is adapted to be supplied to the output switching unit 3.

The output switching unit 3 includes the memory units 2a to 2c.
The pixel data stored in is sequentially selected and output.
The order of selection is as follows: first memory unit 2a → third memory unit 2c →
Second memory section 2b → third memory section 2c → first memory section 2
It is performed like a, ....

Further, of the pixel data read from the field memory (not shown), the first memory unit 2
The pixel data input to a is also supplied to the first shift register 4, and the pixel data input to the second memory unit 2b is also supplied to the second shift register 5. However, when the pixel data from the field memory is input to the first shift register 4, the pixel data stored in the second memory unit 2b is read and input to the second shift register 5, When the pixel data from the field memory is input to the 2 shift register 5, the pixel data stored in the first memory unit 2 a is read and input to the first shift register 4. When the pixel data stored in the memories 2a and 2b is read, this pixel data is output via the output switching unit 3.

The shift registers 4 and 5 each have 3
It is configured in stages, and data shift is performed to the next stage every time pixel data is input.
That is, in the present embodiment, six interpolated reference pixels that are close to the interpolated pixel are extracted to generate interpolated pixel data. The three current pixel data a to c on the line will be stored, and the second shift register 5 will store the three current pixel data d to f on the post-scan line of the interpolation pixel.

The first to fourth calculators 6 to 9 are circuits (for example, comparators) for calculating the magnitude relation between two data inputs, and the calculation results showing the magnitude relation by this calculation are the first to fourth flags. It is designed to be stored in 10 to 13.

Specifically, the first calculator 6 inputs the pixel data a of the first stage and the pixel data b of the second stage of the first shift register 4, and calculates the magnitude relationship (shade relationship) between them. Then, the result is stored in the first flag 10, and the second computing unit 7
The pixel data b of the second stage and the pixel data c of the third stage of the first shift register 4 are input, the magnitude relationship between them is calculated, the result is stored in the second flag 11, and the third computing unit 8 ,
The pixel data d of the first stage and the pixel data e of the second stage of the second shift register 5 are input, the magnitude relation between them is calculated, the result is stored in the third flag 12, and the fourth computing unit 9 ,
The pixel data e of the second stage and the pixel data f of the third stage of the second shift register 5 are input, the magnitude relationship between them is calculated, and the result is stored in the fourth flag 13.

The interpolation judging section 14 judges the contents of the first to fourth flags 10 to 13 to decide the interpolation direction. For example, with the contents of the first to fourth flags 10 to 13, it is possible to judge whether the data string of the pixel data def gradually becomes brighter or darker, or there is a point of a peak or a valley in e, In this case, the same determination is made for the data row of the pixel data abc, and if both data rows become brighter, the interpolation direction is the vertical direction, the pixel data e and b are averaged to obtain the data of the pixel data def. The rows get brighter,
If the data string of the pixel data abc gradually darkens, the interpolation direction is set to cross.

As described in the conventional example, the interpolation direction is the first cross direction from the upper left stage to the lower right stage, the second cross direction from the upper right stage to the lower left stage, and the vertical direction from the middle upper stage to the middle lower stage. It is set. Here, the interpolation in the first cross direction means the average value of the pixel data a and the pixel data f ((a
+ F) / 2) is the interpolated pixel data, and the interpolation in the vertical direction means that the average value ((b + e) / 2) of the pixel data b and the pixel data e is the interpolated pixel data. The interpolation in the two-cross direction is to use the average value ((c + d) / 2) of the pixel data c and the pixel data d as the interpolated pixel data.

The switching unit 16 selects one of the three different outputs (three types of interpolation pixel data) of the interpolation calculation unit 15 based on the determination output of the interpolation determination unit 14 and selects the third output. It is supplied to the memory unit 2c.
Although it seems that the interpolation calculation unit 15 is composed of three calculation units in the drawing, in reality, the interpolation calculation unit 15 is composed of one calculation unit and the data (a ...
By switching f), three types of interpolation pixel data are switched and output.

With the above configuration, for example, when pixel data is written in the second memory section 2b, this pixel data is also written in the second shift register 5, and at the same time, stored in the first memory section 2a. The pixel data that has been read is read and written to the first shift register 4. Then, an interpolation determination is made based on the pixel data stored in the first and second shift registers 4 and 5, and based on this determination, the interpolated pixel data is processed by the interpolation calculation unit 15 and the switching unit 16 to the third memory unit 2c. Written in.

When the pixel data is written in the first memory section 2a, this pixel data is also written in the first shift register 4, and at the same time, the pixel data stored in the second memory section 2b is read out. It is written in the second shift register 5. Then, an interpolation determination is made based on the pixel data stored in the first and second shift registers 4 and 5, and based on this determination, the interpolated pixel data is processed by the interpolation calculation unit 15 and the switching unit 16 to the third memory unit 2c. Written in.

That is, when the image data is input, each pixel data that is sequentially input is stored in the shift registers 4 and 5, flag information is sequentially generated from the pixel data stored in the registers 4 and 5, and this flag information is used as the flag information. Since the sequential interpolation method is determined to sequentially generate the interpolated pixel data, it is not necessary to access the memory one by one when generating the interpolated pixel data, and the number of memory accesses can be reduced.

FIG. 2 is a timing chart showing the relationship between the input pixel data, the read / write timing of the memory 2 and the shift of the shift registers 4 and 5. As can be seen from this figure, the interpolated pixel data is generated and written in the third memory unit 2c every time the pixel data is input from the field memory. As described above, the output of the pixel data in the memory 2 is the data of the first memory unit 2a → the data of the third memory unit 2c → the data of the second memory unit 2b → the data of the third memory unit 2c → the data of the third memory unit 2c. The data of one memory section 2a is output.

(Embodiment 2) Another embodiment of the present invention will be described below. For convenience of explanation, the same components as those in the first embodiment will be designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, the output of the switching unit 16 is used as it is as the interpolated pixel data in the first embodiment, whereas the second step is performed after the two-step interpolation is performed to generate the interpolated pixel data. It is different in that it is stored in the memory unit 2c.

FIG. 3 is a block diagram showing the image data interpolation circuit of this embodiment. The flag for storing the calculation results of the calculators 31 to 37 is omitted. The image data interpolating circuit includes first to third shift registers 20, 21 and 22. The first shift register 20 has four stages and second and third shift registers 21 and 22.
Are each configured in three stages. The third shift register 22 performs data shift to the next stage i → j → k every time the output of the interpolation calculation unit 15 (in the present embodiment, it becomes provisional interpolation pixel data) is input. .

The first multiplexer 23, which selects four flag outputs among the seven flags (not shown) and outputs them to the interpolation determination unit 14, and the temporary interpolation pixel data are third-shifted. The second interpolating operation is performed such that the final interpolated pixel data supplied to the register 22 and obtained by the two-step interpolation is supplied to the third memory unit 2c.
The multiplexer 27 is provided. Further, an interpolation calculation unit 26 is provided in addition to the interpolation calculation unit 15 of the first embodiment. The interpolation calculation unit 26 uses the pixel data b and the temporary interpolation pixel data k.
Average value ((b + k) / 2), average value of pixel data c and provisional interpolation pixel data j ((c + j) / 2), average value of pixel data d and provisional interpolation pixel data i ((d + i) / 2)
Is configured to output.

Next, the operation of the image data interpolating circuit will be described separately for the first step processing and the second step processing.

(First Stage Processing) First Shift Register 20
In accordance with the pixel data a to c and the pixel data f to h of the second shift register 21, as in the first embodiment, the interpolation determination unit 1 is generated.
Reference numeral 4 determines the interpolation direction by judging the content of a flag (not shown). At this time, the first multiplexer 23
Performs a switch operation so that the outputs of four flags (not shown) connected to the computing units 31, 32, 34, and 35 are supplied to the interpolation determination unit 14.

On the basis of the interpolation direction determined by the interpolation determination unit 14, the second multiplexer 27 operates the interpolation calculation unit 1
One of the five different outputs (three types of temporary interpolation pixel data) is selected as one temporary interpolation pixel data.
At this time, the second multiplexer 27 performs a switching operation so as to supply the selected one provisional interpolation pixel data to the third shift register 22.

That is, the above-mentioned first stage processing is as shown in FIG.
, The pixel data a to c and the pixel data f to
This is a process of generating the temporary interpolation pixel data i to k from h and storing them in the third register 22.

(Second Stage Processing) After the temporary interpolation pixel data i is stored in the third register 22, next, the pixel data b to d of the first shift register 20 and the temporary interpolation pixel data i to the third shift register 33. interpolation determination unit 1 according to k
Reference numeral 4 determines the interpolation direction by judging the content of a flag (not shown). At this time, the first multiplexer 23
Performs a switch operation so that the outputs of four flags (not shown) connected to the computing units 32, 33, 36, and 37 are supplied to the interpolation determination unit 14.

On the basis of the interpolation direction determined by the interpolation determination unit 14, the second multiplexer 27 operates the interpolation calculation unit 2
6 different outputs (3 types of interpolated pixel data)
One of the interpolated pixel data is selected from the above. At this time, the second multiplexer 27 performs a switching operation so as to supply the selected one interpolated pixel data to the third memory unit 2c.

That is, the above-mentioned second stage processing is performed as shown in FIG.
, The pixel data b to d and the pixel data i to
This is a process of generating interpolated pixel data from k and storing it in the third memory unit 2c.

Even when the interpolated pixel data is generated by such a two-step process, the image data interpolating circuit of this embodiment generates the interpolated pixel data every time the pixel data is input from the field memory, and the third Since the data is written in the memory unit 2c, it is possible to eliminate the need to separately access the field memory for generating the interpolated pixel data. Further, since it is not necessary to increase the memory portion of the memory 2 by one scanning line for the processing twice, it is possible to obtain a high-quality image with less pixel data without increasing the power consumption.

In the above embodiment, the interpolation calculation unit 15
Alternatively, the interpolation calculation unit 26 is configured to generate the interpolated pixel data or the tentative interpolated pixel data by the average value of the pixel data in the three types of interpolation directions, but the three types of pixel data are appropriately weighted for interpolation. You may do it,
Further, peripheral pixels other than six may be used as the peripheral pixels near the interpolation pixel.

[0039]

As described above, according to the present invention, interpolation pixel data is continuously generated when image data is input, and the number of times of accessing the memory can be reduced. Further, even when the final interpolated pixel data is generated by the two-time processing, the same effect as described above can be obtained, and since it is not necessary to increase the storage means for one line for the two-time processing, the power consumption is increased. The effect is that a high quality image can be obtained with less pixel data.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an image data interpolation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing timings of memory access and the like in the circuit of FIG.

FIG. 3 is a circuit diagram showing an image data interpolation circuit according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining operation contents in the circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 input switching unit 2 memory 3 output switching unit 4 first shift register 5 second shift register 6 to 9 computing unit 10 to 13 flag 14 interpolation determination unit 15 interpolation computing unit 16 switching unit

Claims (2)

[Claims] 1. A storage unit for storing input image data, and a shift register for storing the input image data and the image data read from the storage unit as a pixel data group of pixels surrounding an interpolation pixel. , An arithmetic unit group that outputs an arithmetic result that is a material for determining a surrounding pixel pattern from an output of the shift register, a flag group that holds the arithmetic result of the arithmetic unit group, and an interpolation method based on flag contents of the flag group An interpolation method determination unit that determines
An image data interpolating circuit, comprising: means for generating interpolated pixel data by the determined interpolating method and storing the interpolated pixel data in a storage means. 2. A storage unit for storing input image data, and a current pixel for storing the input image data and the image data read from the storage unit as a pixel data group of pixels surrounding the interpolation pixel. A shift register, a temporary interpolating pixel shift register that holds a temporary interpolating pixel data group, and an operation that outputs an operation result that is a material for determining surrounding pixel patterns from the outputs of the current pixel shift register and the temporary interpolating pixel shift register. Device group, a flag group that holds the calculation result of the arithmetic unit group, and an interpolation method for temporary interpolation pixel data generation as the first processing based on the flag contents of the flag group,
An interpolation method determination unit that determines an interpolation method for generating final interpolation pixel data by using the temporary interpolation pixel data as the second processing, and a temporary interpolation pixel data is generated as the first processing by the determined interpolation method. Then, the image data interpolating circuit is further provided with means for storing the temporary interpolating pixel shift register in the temporary interpolating pixel shift register and generating the final interpolating pixel data in the storage means as the second processing.