JPH08317010A - Modulator for digitally modulated waves - Google Patents

Abstract

(57) [Abstract] [Purpose] Digital satellite broadcasting, digital CATV,
Provided is a versatile digital modulator as a device for communication and digital terrestrial broadcasting. [Structure] 2n + 1 0 values are alternately inserted into each of I and Q data input at a symbol rate to perform band limiting of desired frequency characteristics and filter processing for forming 0-value interpolated data. The output data is multiplied by the coefficients of +1 and -1, and the select circuit alternately outputs the data multiplied by the coefficients of +1 and -1, and the data from the I and Q select circuits are MUXed to perform D / A. By converting, a quadrature modulated wave is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in satellite communications, digital satellite broadcasting, digital CATV, terrestrial communications, digital terrestrial broadcasting and the like, and more particularly to a modulator for digitally modulated waves.

[0002]

2. Description of the Related Art Various communication systems have been developed with the increase of communication needs and the development of communication technology. Among them, in a system for transmitting digitally processed video signals and audio signals, high quality transmission is possible. Also, there are digital modulation techniques that are effective in improving frequency utilization efficiency.

Conventionally, in terrestrial digital microwave communication and the like, QAM (Quadrature Amplitude Modulation) having high frequency utilization efficiency,
QPSK (4-phase phase modulation) system and the like have been generally used in satellite communication, and VSB (Residual Sideband) modulation has been generally used in terrestrial broadcasting.

In recent years, this digital transmission technique has come to be widely used also for consumer use such as mobile communication, digital CATV service, digital satellite broadcasting, ATV (advanced television), and high quality signal transmission characteristics and frequency utilization efficiency. It is expected that it will become even more popular in the future even from the viewpoint of its excellent compatibility with other media. As a consumer system, the hardware configuration is simple and the scale is small, and there are few adjustment points and temperature drift.
The most important thing is that it is suitable for C conversion.

FIG. 7 is a block diagram of a conventional demodulation circuit using a digital signal processing technique. Input terminals 700, 7
The digital I, Q data input to 01 are input to filters (roll-off filters) 702 and 703 that perform frequency limitation and spectrum shaping. I / Q data that is frequency limited and spectrum shaped by the filter is D / A
The signals are input to the converters 704 and 705, converted into analog I and Q signals, and output. The I and Q converted into analog signals are input to amplification circuits 706 and 707, amplified and buffered, and output. The signal output from the amplifier circuit is input to LPF circuits 708 and 709, subjected to band limitation, and output to amplifier circuits 710 and 711. The I and Q signals are amplified and buffered again by the amplifier circuits 710 and 711 and input to the mixers 712 and 713. The signal of the local oscillator (IF carrier) 714 is 0
As a local oscillation signal having a degree (in-phase) phase, it is further input to the 90-degree phase shifter 715 to become a local oscillation signal having a 90-degree (quadrature) phase, and is input to the mixers 712 and 713, respectively. In the mixer, the input I and Q signals are multiplied by the local oscillation signal and frequency-converted to an IF (intermediate frequency) frequency. The modulated waves each converted to the IF frequency are input to the adder 716 and are output as IF quadrature modulated waves. The quadrature modulated wave from the adder is input to the BPF circuit 717, frequency-limited so as to have a channel band characteristic, and output. The output signal of the BPF circuit 717 is input to the amplifier 718, amplified, buffered, and IF.
The quadrature modulated wave is output from the output terminal 719.

[0006]

However, in the conventional configuration, the D / A converters 704, 705, the amplification buffer circuits 706, 707, 710, 711 and the LPF circuit 7 are used.
08, 709, mixers 712, 713, and adder 716 are all processed by analog signal processing up to I and Q quadrature modulation signal processing. Active elements (transistors, diodes, operational amplifiers) and the like used in analog signal processing are easily affected by temperature drift, aging, power supply voltage fluctuations, etc., and are insufficient in terms of stability. Particularly, it is difficult to stably maintain the quadrature (phase difference) of the quadrature modulated wave at 90 °, and if the phase difference deviates from 90 °, the modulated wave interferes with the data.

The present invention solves the above-mentioned conventional problems,
An object of the present invention is to provide a digital modulation processing circuit having versatility as a device for mobile communication, digital broadcasting, digital CATV service, satellite communication, satellite broadcasting and the like.

[0008]

In order to achieve this object, the modulation circuit of the present invention comprises a means for inserting 0 values in the input digital I and Q signals alternately with data, and a means for inserting 0 values alternately. Filter means to which the inserted data is supplied for frequency limitation and spectrum shaping, means for multiplying the output data of the filter by +1, -1, and means for select-switching the data multiplied by +1, -1; Means for latching both the I and Q signals that have been select-switched,
A D / A conversion means for obtaining a quadrature modulation wave whose center frequency is equal to the symbol frequency by converting the latched digital signal into an analog signal, and an amplification circuit for amplifying and buffering the modulation output signal from the D / A converter. , An LPF circuit for band-limiting the signal from the amplifier circuit, a frequency converting means for frequency-converting the signal of the LPF circuit by a local oscillation signal from a local oscillator, and a band-limiting and spectrum for the frequency-converted signal. A BPF circuit for shaping,
It comprises an amplifying means for amplifying and buffering the signal from the BPF circuit and outputting it.

[0009]

The operation of the modulation circuit of the present invention constructed as above will be described.

In the digital modulation circuit of the present invention, first, a 0 value is alternately inserted into the I digital data input at the symbol frequency (Fsym) to convert it into a double symbol rate, and the spectrum is obtained by the roll-off filter. Shape. The output of the roll-off filter is multiplied by +1, -1 and then the select switch circuit alternately switches and outputs the data. One Q data is subjected to the same processing with an inverted clock delayed by 180 ° from the I data processing timing. The I, Q data multiplied by +1, -1 is latched at a symbol frequency of 4 times to form interleaved I, Q data. Interleaved I and Q signals at 4Fs
By performing D / A conversion with ym, a quadrature modulated wave whose center frequency is equal to the symbol frequency is obtained.

[0011]

(Embodiment 1) An embodiment of the first digital modulation circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. The digital I and Q signals input from the input terminals 100 and 101 are inserted with 0 values alternately in the 0 insertion circuits 102 and 103, and converted into a double symbol rate. The data in which the 0 value is inserted is set to the roll-off filter 104 or 1
It is input to 05, frequency limited, and output.

The output data of the roll-off filter is +
Multiplying circuits 106, 107, 108 for multiplying 1, −1,
109 is input. The signal multiplied by +1, -1 is 2Fs
The data input to the select switch circuits 110 and 111 that alternately switch at the frequency of ym and multiplied by +1 and -1 are alternately output. The switched data of both I and Q has a 4 times symbol frequency (4Fsym) and latch circuit 1
It is latched by 12 and forms interleaved I and Q data.

The interleaved digital data is D
It is input to the / A converter 113 and converted into an analog quadrature modulated wave whose center frequency is equal to the symbol frequency and output. The quadrature modulated wave passes through the amplifier / buffer circuit 114, is band-limited by the LPF circuit 115, and is then mixed by the mixer circuit 11
6 is input. The mixer circuit multiplies the signal from the local oscillator 117 and frequency-converts it to IF (intermediate frequency) for output. The frequency-converted quadrature modulated wave is subjected to band limitation by the channel BPF 118, passes through the amplifier / buffer circuit 119, and is output from the output terminal 120.

The operation of the demodulator having the above structure will be described below. FIG. 8 shows a signal waveform of the zero value insertion processing. FIG.
A waveform of digital data input at a symbol rate (Fsym) is shown in (A). In the symbol rate data, 0 values are inserted alternately with the data by the 0 value insertion circuit, and as shown in FIG. 8B, the symbol rate data is converted into data having a double symbol rate (2Fsym). The data converted into the 2Fsym velocity is input to the roll-off filter and filtered to output a signal by interpolating the zero value portion as shown in FIG. 8 (C).

The roll-off filter output obtained by interpolating the 0-valued portion of each of I and Q is multiplied by +1 and -1, and the data obtained by multiplying +1 and -1 by the select switch is alternately switched at the 2Fsym clock and output. . For I data, switch with the 2Fsym clock shown in FIG. 9 (D).
Output in the order of I (+1), I (-1), I (+1) shown in (F). The Q data is also switched by the inverted clock of 2Fsym of (E) and output in the order of Q (+1), Q (-1), Q (+1) shown in (G).
The data obtained by multiplying I and Q by +1 and -1, respectively,
It is latched by the 4Fsym clock shown in (H) and converted into a symbol rate data string four times as large as I (+1), Q (+1), I (-1), Q (-1) as shown in (I). And is input to the D / A converter.

The analog signal output from the D / A converter is shown in FIG.
The waveform is a composite of I and Q signals shown in (J). (J)
Is a modulated wave quadrature-modulated to the symbol frequency (Fsym),
It is a signal waveform shown divided into Q signals. The data sampled with 4 Fsym clock is digitally converted into Fsym.
The quadrature modulation to the speed is performed by adding 0, + 1,0, -1 to the I data as Q.
The data will be sequentially multiplied by -1,0, + 1,0. Here, the data obtained by latching the I and Q signals modulated at the symbol rate with the 4Fsym clock is Q (-1), I (+1), Q (+1), I (-
1) and Q (-1) data strings, which are the same as the data strings shown in FIG. 9 (I). Therefore, the output signal of the D / A converter is output as a modulated wave that is quadrature-modulated so that the center frequency is equal to the symbol rate.

The quadrature modulated wave from the D / A converter passes through an amplifier and a buffer circuit, is band-limited by an LPF, and is input to a mixer circuit. The quadrature modulated wave input to the mixer circuit is frequency-converted into an IF frequency by the IF oscillation frequency signal from the local oscillation circuit, and the BPF circuit performs spectrum shaping to pass only the desired modulated wave component. BP
The modulated wave that has passed through the F circuit passes through the amplifier and the buffer circuit and is output from the output terminal as an IF quadrature modulated wave.

(Embodiment 2) FIG. 2 is a block diagram of another embodiment of the digital modulation circuit device according to the first embodiment of the present invention. 2, the same parts as those of the circuit of FIG. 1 are designated by the same reference numerals. The ROM 20 having the same functions as the +1, −1 multiplication circuits 106, 107, 108, 109 and the select switch circuits 110, 111 shown in FIG.
0 and 201 are arranged, and other circuit configurations are the same as those described in the first embodiment.

The operation will be described below. The same parts described in the first embodiment will be omitted.

Roll-off filter 104, 105 0
The I, Q data and the Fsym clock, which are interpolated by the value part and converted into the 2Fsym speed, are supplied to the ROMs 200 and 201. Data is converted based on the relationship between the timing of the I data signal input to the ROM 200 and the High / Low of the symbol frequency Fsym clock (K). As shown in (F) and (K) of FIG. 9, data in the period when the Fsym clock is High is multiplied by +1.

That is, the data is output as it is. Fsym
The data in the period when the clock is low is multiplied by -1 and output. It is programmed to invert the sign of the data and output it. As a result, data obtained by multiplying I data by +1 and -1 is output alternately at the 2Fsym clock timing. Similarly, for the Q data input to the ROM 201, the data obtained by multiplying the data by +1 and -1 is alternately output at the inversion timing of the 2Fsym clock.

Considering the delay of the circuit and the circuit that constitutes the Fsym clock, the timing of multiplying by +1 and -1 in the ROM does not change the operating principle even if the relationship between the high and low of the Fsym clock is reversed. Absent. + For each I and Q
The configuration and operation after latching the data multiplied by 1 and −1 with the 4Fsym clock, converting it to the 4 times the symbol rate data string shown in FIG. 9 (I) and supplying it to the D / A converter are:
Since it is the same as that already described in (Example 1), description thereof will be omitted.

(Embodiment 3) FIG. 3 is a block diagram of a digital modulator according to a third embodiment of the present invention. A description will be given below with reference to the drawings. 3, the same parts as those of the circuit of FIG. 1 are designated by the same reference numerals. The 0 value which is alternated with the symbol rate data input by the 0 insertion circuit is inserted.
A digital filter 300, 3 which is a digital filter to which speed-converted data is supplied to Fsym and performs quadrature modulation to a frequency whose center frequency is equal to the symbol speed simultaneously with spectrum shaping for preventing interference between data.
01 is arranged. The other circuit configuration is the same as that shown in FIG. The operation will be described below.
The same parts described in the first embodiment of FIG. 1 will be omitted.

The digital filters 300 and 301 shown in FIG.
Uses a filter tap coefficient obtained by calculating a tap coefficient of a desired roll-off characteristic for preventing intersymbol interference of input data and alternately multiplying the tap coefficient by +1 and -1. As described above, in order to perform quadrature modulation at a frequency where the center frequency is equal to the symbol rate, 0, + is applied to the input I data by the 4Fsym processing.
For 1,0, -1 to Q data, -1,0, + 1,
It will be sequentially multiplied by 0.

Here, the I data filter of the filter 300 is set to 2 Fsym clocks, and the Q data filter 301 is set to 2 Fsym clocks.
Considering to operate with the inverted clock of Fsym, from the input data timing, I and Q are +1 and -1, respectively.
Output data multiplied by is latched with 4Fsym clock and 4
If converted into a doubled symbol speed data string, FIG.
It is the same as the data string shown in. This means that the input I and Q data are orthogonally modulated to a frequency equal to the symbol rate. The circuit configuration and operation after the D / A converter are the same as those already described, and the description thereof is omitted here.

(Embodiment 4) FIG. 4 is a block diagram of a digital modulator according to a fourth embodiment of the present invention.

A description will be given below with reference to the drawings. 4, the same parts as those of the circuit of the first embodiment shown in FIG. 1 are designated by the same reference numerals. Alternating 0 with I data input at symbol rate
A digital filter 400 in which a value is inserted and speed-converted data is supplied to 2Fsym, spectrum shaping is performed to prevent interference between data, and band limitation is performed on the vestigial sideband (VSB) characteristic. , 40
1 is arranged, and other circuit configurations are the same as those in the first embodiment.
The configuration is the same as that described in.

The operation will be described below. Input terminal 10
A 0 value is alternately inserted into the I data input from 0 at the symbol rate by the 0 insertion circuit. 0 value is inserted and 2
The data subjected to speed conversion into Fsym is supplied to digital filters 400 and 401 which band-limit the desired VSB characteristic. Here, the filter 400 is the desired VSB.
It is a filter with the coefficient of the in-phase component (Real) of the characteristic, and operates with 2Fsym clock. The filter 401 is a filter having a coefficient of a quadrature component (Imag) of a desired VSB characteristic, and operates with an inversion clock of 2Fsym.

The processing after filtering the in-phase component and the quadrature component of the VSB characteristic and multiplying them by +1 and -1, respectively, is the same as that described in the above embodiment and will not be repeated here. The data processed by each filter is latched by 4Fsym clock to form a 4 times symbol speed data string,
The D / A converted analog signal becomes a vestigial sideband modulated wave signal centered on the symbol frequency as shown in FIG.

(Embodiment 5) FIG. 5 is a block diagram of another embodiment of the digital modulator according to the fourth embodiment of the present invention. 5, the same parts as those of the circuit of FIG. 4 are designated by the same reference numerals. ROMs 200, 2 having the same functions as the multipliers 106, 107, 108, 109 and the data switch circuits 110, 111 shown in FIG.
01 is arranged, and other circuit configurations are the same as those described in the fourth embodiment.

The operation will be described below. The same parts described in Examples 1 and 4 are omitted. The data from the digital filters 400 and 401, which performs spectrum shaping to prevent intersymbol interference of data while simultaneously band limiting the vestigial sideband characteristics, is stored in the ROM 200,
The data is input to 201, the data is multiplied by +1, -1 in the ROM, and the data is output at the 2Fsym speed. The operation in the ROM is the same as the ROM configuration of the second embodiment, and the description thereof is omitted here. R multiplied by +1 and -1 alternately with the data
D / A by latching data from OM with 4Fsym clock
By converting, a VSB modulated wave having the symbol frequency as the center frequency is obtained.

(Embodiment 6) FIG. 6 is a block diagram of a digital modulator according to a sixth embodiment of the present invention. A description will be given below with reference to the drawings. 6, the same parts as those of the circuit of FIG. 4 are designated by the same reference numerals. A digital filter in which 0 values are inserted alternately with the I data input by the 0 insertion circuit, and the speed-converted data is supplied to 2Fsym. This is a configuration in which digital filters 600 and 601 are arranged to perform vestigial sideband (VSB) band modulation with the frequency at the center frequency.

The other circuit configuration is the same as that shown in FIG. The operation will be described below. Example 4 of FIG.
The same parts described in 1 are omitted. The digital filter 600 of FIG. 6 calculates the tap coefficient of the in-phase component (Real) of the roll-off characteristic for preventing intersymbol interference of the input I data and the desired VSB characteristic, and the tap coefficient is +1, −1. Is used as the filter tap coefficient. The digital filter 601 is
Orthogonal component of roll-off characteristic and desired VSB characteristic (Imag
The tap coefficient of e) is calculated, and as in the filter 600, a value obtained by alternately multiplying the coefficient by +1 and −1 is used as the filter tap coefficient.

In order to perform VSB modulation with the symbol frequency as the center frequency, 0, +1, 0, -1 is added to the VSB characteristic orthogonal to the filtered data of the in-phase component of the VSB characteristic with respect to the input data by the 4Fsym processing. The component filtered data will be sequentially multiplied by -1, 0, +1, 0. In-phase component filter 60 of VSB characteristic
0 is 2 Fsym clock, and quadrature component filter 601 is 2
Considering the operation with the inverted clock of Fsym, as described in the third embodiment, the input data timing is changed to + from the in-phase component of the VSB characteristic and the quadrature component of the filter output.
If the output data obtained by alternately sequentially multiplying 1 and -1 is latched by the 4Fsym clock and converted into a quadruple symbol rate data sequence, the same data sequence as shown in FIG. 9 (I) is obtained. This means that a VSB modulated wave centered on the symbol frequency can be obtained by D / A converting the filtered data of the in-phase component and the quadrature component of the VSB characteristic of 4 Fsym speed.

[0036]

As described above, according to the present invention, in a modulator of digitally modulated waves, analog signal processing from the D / A converter used in the conventional analog quadrature modulation to the addition of I and Q modulated waves. By performing all digital processing, there is no adjustment due to digital signal processing, the degree of orthogonality during quadrature modulation, temperature drift, aging, and power supply voltage stability are good, and a modulator suitable for IC implementation can be obtained. .

[Brief description of drawings]

FIG. 1 is a block diagram of a digital modulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the first digital modulator of the present invention using a ROM.

FIG. 3 is a block diagram of a digital modulator according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a digital modulator according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the third digital modulator of the present invention using a ROM.

FIG. 6 is a block diagram of a digital modulator according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram of a conventional modulator for digitally modulated waves.

8 is an explanatory diagram of a filter processing operation by inserting 0 in FIG.

9 is an explanatory diagram of the operation principle of digital quadrature modulation in FIG.

FIG. 10 is an explanatory diagram of a VSB modulated wave in the third embodiment of the digital modulator of the present invention.

[Explanation of symbols]

102, 103 0 Insertion circuit 104, 105 Finite impulse response type digital filter 106, 107, 108, 109 Multiplier 110, 111 Data switch circuit 112 Latch circuit 113 D / A converter 114, 119 Amplifier, buffer circuit 115 Low pass filter 116 Mixer circuit 117 Local oscillator 118 Bandpass filter 200, 201 ROM

Claims (8)

[Claims] 1. A first 0 insertion means for use in a modulator for quadrature modulation of a digital modulated wave, for inserting 2n + 1 zero values alternately with I data input at a symbol rate, and Q. Second 0 insertion means for inserting 2n + 1 0 values alternately with the data, and band-limited to the I signal in which 2n + 1 0 values are alternately inserted with the data to form 0-value interpolated data. A first filter means, a second filter means for band-limiting the Q signal in which 2n + 1 0 values are inserted to form 0-value interpolated data, and I output data of the filter means of +1 and-. A first multiplication means for obtaining two outputs by multiplying by a coefficient of 1, a second multiplication means for obtaining two outputs by multiplying the Q output data of the filter means by a coefficient of +1 and -1, and the I data multiplication means. Select one from 2 output data 1, means for alternately outputting the I data coefficients are multiplied -1, 2 of the Q data multiplication means
A means for selecting one of the output data and alternately outputting Q data multiplied by a coefficient of +1 and -1, and a latch means for alternately latching the I and Q data to form quadrature-modulated data. And a D / A means for D / A converting the output data of the latch means. 2. The ROM (Read Only Memor) function of the multiplication means and the means for selecting a switch of the output signal of the multiplication means is selected.
2. The device for modulating a digitally modulated wave according to claim 1, characterized in that it is constituted by y). 3. A first zero inserting means for alternately inserting 2n + 1 zero values with I data inputted at a symbol rate, and Q.
The second 0 insertion means for alternately inserting 2n + 1 0 values and the I signal in which 2n + 1 0 values are inserted are input, and the coefficients of +1 and -1 are alternately multiplied while band limiting is applied. First filter means for outputting data and 2n +
A second filter means for inputting a Q signal in which one 0 value is inserted and outputting data obtained by alternately multiplying coefficients of +1 and -1 while performing band limitation, and I, of the filter means.
Digitally modulated wave characterized by comprising latch means for alternately latching Q output data to form quadrature-modulated data, and D / A means for D / A converting the output data of the latch means. Modulator. 4. The first and second filter means are constituted by a finite impulse response type digital filter, and a tap coefficient of the filter for forming a frequency characteristic is +1.
The modulator for digitally modulated waves according to claim 3, wherein the filter processing is performed using a coefficient obtained by alternately multiplying and -1. 5. 2n + to one symbolized data
The 0 insertion means for alternately inserting one 0 value and the digital data and the digital data in which the 2n + 1 0 values are alternately inserted are input, and the common mode component of the VSB (Residual Sideband) characteristic is frequency-limited to 0. A first filter means for constructing interpolated data of values, a second filter means for constructing zero-value interpolated data by frequency limiting orthogonal components of VSB characteristics, and +1 for output data of first in-phase component filter -1
Of the second output data of the first multiplying means, the second multiplying means of multiplying the output data of the second quadrature component filter by the coefficients of +1 and -1, Means for alternately outputting the data of the in-phase component, which is selected and multiplied by the coefficients of +1 and -1, and one of the two output data of the second multiplication means, is multiplied by the coefficients of +1 and -1. A means for alternately outputting the data of the quadrature component and a means for alternately latching the data of the in-phase and the quadrature component for V
An apparatus for modulating a digitally modulated wave, comprising: latch means for forming SB-modulated data, and D / A means for D / A converting output data of the latch means. 6. A ROM (Read) function of the multiplying means for multiplying and the means for selectively outputting the output signals of the multiplying means and alternately outputting the data multiplied by the coefficients of +1 and -1.
A device for modulating a digitally modulated wave according to claim 5, characterized in that it is configured by only a memory. 7. A means for alternately inserting 2n + 1 0 values with one system of data input at a symbol rate, and a signal with 2n + 1 0 values inserted alternately with data are input and V
Alternately while frequency limiting the in-phase component of SB characteristics +
The first filter means for multiplying the coefficient of 1 and -1 to output the data, and the signal in which 2n + 1 0 values are inserted alternately with the data are input and alternated while frequency-limiting the orthogonal component of the VSB characteristic. And a second filter means for outputting data by multiplying by +1 and -1 coefficients, and a latch means for alternately latching the data of the in-phase component and the quadrature component of the VSB characteristic to form the VSB-modulated data. And a D / A unit for receiving data from the latch unit and performing D / A conversion. 8. The first and second filter means are constituted by a finite impulse response type digital filter, and VS
8. The digital modulated wave modulator according to claim 7, wherein the filtering process is performed using a coefficient obtained by alternately multiplying the tap coefficient of the filter forming the in-phase component and the quadrature component of the B characteristic by +1 and -1. .