JPH0831936A - Wiring formation method - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a method for forming a wiring that achieves planarization while taking advantage of the self-aligned contact method. [Structure] Gate electrode 13, offset SiO ₂ film 14
Then, an interlayer insulating film 16 is formed, and an interlayer film 17 serving as a wet etching stopper is formed thereon. A reflow film 18 is formed on the interlayer film 17, a resist 19 is patterned, wet etching is performed to perform isotropic processing on the reflow film 18, and then a contact hole 20 is formed by anisotropic etching. As a result, flattening is achieved in portions other than the contact, and processing problems such as a short circuit between upper layer wirings are eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method, and more particularly to a wiring technique for surely forming a contact by a self-aligned contact method.

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor memory devices, the self-aligned contact (SAC) method is becoming the mainstream as a technique for opening a contact between wirings. The self-aligned contact method is a technique in which a stepped shape of a lower layer wiring is used to open a fine contact by self-alignment between the wirings. However, the lower layer step due to the contact opening causes a problem such as a short circuit between wirings and an increase in wiring capacitance when forming the upper layer wiring, which is a problem to be solved in the process in addition to securing the interlayer breakdown voltage. In addition, the self-aligned contact method has an advantage that it is possible to open a fine contact below the exposure limit by utilizing the step difference between wirings without any alignment. Increased capacity and difficulty in processing pose problems.

A conventional structure and forming method will be described below. That is, first, as shown in FIG. 3A, the inter-element isolation film 2 is formed on the silicon substrate 1 by using the LOCOS technique.
To form. Then, the gate electrode 3 to be the word line
Are patterned together with the offset SiO ₂ film 4.
The gate electrode 3 is usually formed of polysilicon or tungsten polycide, and its film thickness is set to about 200 nm. The offset SiO ₂ film 4 is formed by atmospheric pressure CVD, low pressure CVD, HTO, etc., and its film thickness is set to about 200 nm. Then, after depositing a SiO ₂ film on the entire surface, the entire surface is etched back by reactive ion etching (RIE) to form the gate electrode 3
A sidewall 5 is formed on the sidewall of the laminated film including the offset SiO ₂ film 4. In addition, this sidewall 5
Is formed by low pressure CVD or HTO, and its film thickness is set to about 200 nm. Next, the interlayer insulating film 6 is deposited on the entire surface. Thereafter, the resist 7 is patterned into a contact pattern as shown in FIG. 3A, and anisotropically processed by RIE using this resist as a mask to expose the impurity diffusion layer 1a formed on the silicon substrate 11 in the contact hole 8. To open a hole. In addition, this RIE
Owing to the step due to the gate electrode 3 and the offset SiO ₂ film 4, the hole is formed substantially in the center between the gate electrodes 3 without depending on the alignment of the resist 7. This is the reason why it is called self-aligned.

Next, after removing the resist 7, FIG.
As shown in (B), the bit line 9 is processed. The bit line 9 is usually made of a low resistance material such as tungsten polycide, and the film thickness of the bit line 9 is 2
It is set to about 00 to 250 nm. However, the bit line 9 has a gate electrode 3 and an offset SiO _{2 on it.}
Due to the step due to the film 4, there is a problem that wirings are short-circuited unless a considerable over-etching is performed during RIE. Further, in the DRAM, the ratio of the capacitance between the bit line and the storage node directly affects the reading of data, so it is desirable to make the capacitance of the bit line as small as possible.
However, in the self-aligned contact method, since the step difference of the base is large, the total wiring length of the bit line becomes long, and as a result, the capacity of the bit line is increased.

The problem to be solved by the present invention is to utilize the advantage of the self-aligned contact method in which fine contacts are opened by self-alignment by utilizing the steps of the lower layer wiring, and in addition to opening the contacts. Then, what measures should be taken to obtain a method for forming a wiring that achieves planarization, prevents the occurrence of processing problems such as short-circuiting of upper layer wiring, and suppresses an increase in wiring capacitance? is there.

[0006]

Therefore, the present invention includes the steps of forming a gate electrode on a semiconductor substrate, depositing an insulating film on the gate electrode, and forming a contact hole using a self-aligned contact method. In the method of forming wiring, after forming the gate electrode, an interlayer film serving as a stopper for wet etching is formed, a reflow film is formed on the interlayer film for planarization, and then a resist is patterned for etching. A contact hole is formed as a solution to this problem.

[0007]

According to the present invention, when the contact is opened by using the self-aligned contact method, the step of the lower wiring is used to open the contact by self-alignment, and at the same time, the reflow film is formed on the portion other than the contact. As a result, it is possible to flatten as much as possible to improve the workability of the upper layer wiring and reduce the wiring capacitance. In particular, by performing wet etching on the reflow film, the step difference in the contact formation portion can be reproduced, so that the contact can be formed by self-alignment.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the wiring forming method according to the present invention will be described below with reference to the embodiments shown in the drawings. In this embodiment,
It is an example in which the present invention is applied to a process of forming a bit line of a DRAM memory cell. Needless to say, the present invention is not limited to this embodiment and can be applied to the wiring forming process in various other semiconductor devices.

In this embodiment, first, as shown in FIG. 1A, an element isolation film 12 is formed on a silicon substrate 11 by using the LOCOS technique. Next, the gate electrode 13 to be the word line is patterned together with the offset SiO ₂ film 14. The gate electrode 13 is usually formed of polysilicon or tungsten polycide, and its film thickness is set to about 200 nm. Also, offset SiO
_{The 2} film 14 is formed by atmospheric pressure CVD, low pressure CVD, HTO, etc., and its film thickness is set to about 200 nm. Then, after depositing a SiO ₂ film on the entire surface, the entire surface is etched back by reactive ion etching (RIE) to form a sidewall 15 on the side wall of the laminated film including the gate electrode 13 and the offset SiO ₂ film 14. The sidewalls 15 are formed by low pressure CVD or HT.
It is formed of O, and its film thickness is set to about 200 nm. Next, the interlayer insulating film 16 is deposited on the entire surface. And
An interlayer film 17 serving as a wet etching stopper is deposited. The interlayer film 17 is made of SiN formed by the low pressure CVD method.
A film is preferable, and the film thickness is set to 20 to 30 nm.
Next, the reflow film 18 is deposited to a film thickness of, for example, about 300 to 500 nm, and reflow is performed to planarize the inside of the memory cell as shown in FIG. This reflow film 1
8 uses atmospheric pressure BPSG, O ₃ -TEOS BPSG, or the like. The purpose of forming the reflow film thickness 18 is to fill the step difference of the gate, and it is desirable that the film thickness is as thin as possible so as not to worsen the step difference of the subsequent memory cell formation. Furthermore, the reflow film 18 can be etched back to further improve the flatness of the surface of the memory cell. However, in this case, it is necessary to adjust the etch back conditions so as not to damage the underlying interlayer film 17.

After that, the resist 19 is patterned to serve as a mask for contact opening. Next, as shown in FIG. 1B, only the reflow film 18 in the contact portion is removed with diluted hydrofluoric acid. At this time, as described above, the interlayer film 17 serves as a stopper for wet etching. By this wet etching, the step due to the underlying gate electrode 3 is reproduced only inside the contact. Anisotropic etching (eg RI
By E), the contact hole 20 to the impurity diffusion layer 11a is self-aligned.

Then, after removing the resist 19, FIG.
As shown in FIG. 5, if the bit line 21 is formed, a flat bit line can be realized except for the contact with the impurity diffusion layer 11a.

Although the embodiment has been described above, the present invention is not limited to this, and various design changes accompanying the gist of the configuration can be made. For example, although the present invention is applied to the DRAM in the above embodiments, it is needless to say that the present invention is also applicable to a device in which wiring is formed on the gate electrode, such as SRAM.

[0013]

As is apparent from the above description, according to the present invention, the advantage of the self-aligned contact method in which fine contacts are opened by self-alignment by utilizing the steps of the lower wiring can be utilized as it is. Flattening is achieved in portions other than the portions where the contacts are opened, and processing problems such as short-circuiting of the upper layer wiring can be prevented. Further, the effective total wiring length of the upper layer wiring is short, and it is possible to suppress an increase in wiring capacitance.

[Brief description of drawings]

1A and 1B are cross-sectional views showing an embodiment of a wiring forming method of the present invention.

FIG. 2 is a cross-sectional view showing an embodiment of the wiring forming method of the present invention.

3A and 3B are cross-sectional views showing a conventional example.

[Explanation of symbols]

11 ... Silicon substrate 12 ... Element isolation film 13 ... Gate electrode 14 ... Offset SiO ₂ film 15 ... Sidewall 16 ... Interlayer insulating film 17 ... Interlayer film 18 ... Reflow film 19 ... Resist 20 ... Contact hole

Claims (2)

[Claims] 1. A method for forming a wiring, comprising: forming a gate electrode on a semiconductor substrate; depositing an insulating film on the gate electrode; and forming a contact hole using a self-aligned contact method. After that, an interlayer film that serves as a stopper for wet etching is formed, a reflow film is formed on the interlayer film to perform planarization, and then the resist is patterned and etched to form a contact hole. Method for forming wiring. 2. The wiring forming method according to claim 1, wherein in the etching, first, the reflow film is wet-etched, and then the contact hole is self-aligned by anisotropic etching.