JPH08321853A - Two signal system mixed data reception circuit - Google Patents

Abstract

PURPOSE: To receive data with the minimum load of a CPU with respect to an SPL(split phase) system data signal following an NRZ system synchronizing signal. CONSTITUTION: A clock C1 corresponding to NRZ is converted into a clock C2 corresponding to SPL in a clock generation part 10. When a synchronizing signal detection part 20 detects the synchronizing signal, the part 20 outputs a data start signal D2, executes data discrimination and accumulation of an input signal D1 in a FIFO memory part as an SPL signal, starts a timer part 40 and counts a time required fro accumulating a necessary quantity of data. The timer part 40 outputs an interruption signal D3 to a CPU part 50 at the time of time-out and the CPU inputs all data accumulated in the FIFO memory part 30 as NRZ system parallel data in a byte unit by one time of interruption concerned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-signal type mixed data receiving circuit, and more particularly to a serial type in which NRZ type serial data and split phase (SPL) type serial data having the same unit time of signal level change are mixed. When the mixed data signal is received and it is detected that the NRZ format serial data is a predetermined synchronization signal, the subsequent SP
The present invention relates to a two-signal format mixed data receiving circuit for incorporating L format serial data as NRZ format parallel data into a CPU that performs control processing based on software by using a hardware interrupt function.

[0002]

2. Description of the Related Art A conventional two-signal type mixed data receiving circuit of this kind is shown in FIG. 3 (see Japanese Patent Laid-Open No. 64-23650). This circuit has a transmission rate of 2 Tbps as shown in FIG.
A serial mixed data signal D1 composed of a synchronization signal D11 of (bit / sec) NRZ (non-return to zero) code and a data signal D12 of SPL (split phase) code of transmission rate Tbps is input and a synchronization signal D1 is input.
1 to detect the subsequent data signal D12 data by the CPU
And an interrupt generation section 90 having a SYNC circuit 91 and a 16-bit counter circuit 92 for detecting the synchronization signal D11, a data conversion section 93 using a shift register circuit, and 8-bit data ( It is composed of a data storage unit 94 for temporarily storing in 1-byte units, and a CPU 95 for performing control processing of circuits and devices under its control based on set software and fetching data in response to a hardware interrupt. It The SYNC circuit 9 based on the clock C1 corresponding to the transmission rate of the NRZ code
1 reads the sync signal D11 (sync bit pattern: 0001, for example) from the serial mixed data D1. After the detection of the synchronization signal D11, the detection signal d2 is output and the 16-bit counter circuit 92 and the data conversion unit 93 start operating. The data conversion unit 93 determines the signal level (data identification) with the clock C1 corresponding to 2 Tbps for the serial mixed data signal D1 and accumulates the signal level while shifting.
Get format parallel data. 16-bit counter circuit 9
2 generates an interrupt signal d3 each time counting 16 bits and sends it to the CPU 95 and the data storage unit 94. The data storage unit 94 fetches the 8-bit parallel data d4 every other bit from the first bit to the 16th bit of the accumulated data of the data conversion unit 93 every time the interrupt signal d3 is received. The format parallel data is converted to NRZ format parallel data and stored. On the other hand, the CPU 9 which has received the interrupt signal d3 (INT)
5 sends a read signal (RD) to the data storage unit 94,
NRZ format parallel data d for 8 bits (1 byte)
Take in 5.

[0003]

In the above-mentioned conventional two-signal format mixed data receiving circuit, the CPU is interrupted each time one byte of data is received, and only one byte of data is fetched each time. Can not. Therefore, the longer the data length to be received, the more the number of interrupts to the CPU, the larger the load of software processing on the CPU, and the lower the processing speed.

Therefore, an object of the present invention is to provide a two-signal type mixed data receiving circuit capable of taking in a large amount of data only by interrupting the CPU once.

[0005]

The present invention receives a serial mixed data signal in which NRZ format serial data and split phase format serial data having the same unit time of signal level change are mixed, and the NRZ format is used. In the two-signal format mixed data receiving circuit for taking in the subsequent split phase format serial data as NRZ format parallel data to the CPU which performs control processing based on software when it is detected that the serial data is a predetermined synchronization signal, A clock creating unit for creating a second clock corresponding to the bit transmission rate of the split phase format serial data from a first clock corresponding to the bit transmission rate of the NRZ format serial data; and the clock generation unit based on the first clock. Monitor serial mixed data signals The sync signal detection unit that outputs a data start signal when a predetermined sync signal is detected, and the serial mixed data signal is regarded as the split phase format serial data based on the second clock when the data start signal is received. A FIFO memory unit that identifies and stores data in units of 1 bit and outputs the stored data as NRZ format parallel data in units of a predetermined bit length, and a transmission data amount of the split phase format serial data when the data start signal is received. Correspondingly, start the time measurement of the preset time value,
A timer unit that outputs an interrupt signal when the time measurement is completed, and a CPU unit that reads all the accumulated data from the FIFO memory unit when the interrupt signal is received are provided.

[0006]

Next, the present invention will be described with reference to the drawings. 1 is a block diagram of an embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a serial mixed data signal and an example of waveforms of signals of respective parts. The two-signal format mixed data receiving circuit of the present embodiment has a bit transmission rate (2Tbp) of an NRZ coded signal.
s), the bit transmission rate (Tb) of the SPL (split phase) encoded signal from the 2 CHz clock C1
ps) and a clock generation unit 10 that generates a THz clock C2 and a synchronization signal D11 (NRZ format serial data) by an NRZ (non-return to zero) code.
And a serial mixed data signal D1 consisting of a data signal D12 (SPL format serial data) based on the SPL code, based on a clock C1 for data identification (signal level determination).
The sync signal detecting section 20 which outputs the data start signal D2 indicating the detection of the sync signal D11 when it coincides with the previously designated and stored sync pattern, and the serial mixed data D1 is regarded as the SPL format serial data based on the clock C2. A FIFO that erases the stored data when the data start signal D2 is received after the data is identified and stored
(First-in / First-out) Memory section 30
And a timer start time value t, which has a timer counter and a timer memory, and which stores in advance a timer time value t corresponding to the amount of transmission data (transmission time) of the data signal D12.
When the timer signal 40 is received, the timer unit 40 which starts timing of the time value t and outputs an interrupt signal D3 when the timing is completed, and when the interrupt signal D3 is received, continuous read access in byte units to the FIFO memory unit 30 is performed through the external bus 60. CPU unit 5 that takes all the accumulated data
It has 0 and.

The CPU section 50 has an internal bus 51 for connecting internal circuits, a ROM 54 for storing programs and data for processing, a RAM 53 for storing temporary data and programs, and an external bus 60. An external bus controller 55 that transmits and receives (RD) data to and from external circuits and devices that are addressed (A) via
It has an interrupt controller 56 that receives an interrupt signal (INT) from the outside, and a processor 52 that operates based on programs and data in the ROM 54 and RAM 53 to control the inside and outside of the CPU unit 50.

Next, the operation will be described. The serial mixed data signal D1 is transmitted by mixing the NRZ format serial data and the SPL format serial data having the same unit time of signal level change. That is, the significant data to be captured by the CPU unit 50 is transmitted at a transmission rate T for each predetermined number of bytes.
It is divided into data signals D12 by SPL code of bps, and the transmission rate is 2 Tbps prior to each data signal D12.
A predetermined bit pattern (for example, 00
01) sync signal D11 is added. The clock C1 input together with the serial mixed data D1 has a frequency (2 THz) corresponding to the unit time of signal level change, that is, the bit unit time of the NRZ code.
The clock creating unit 10 divides the clock C1 to create a clock C2 having a frequency (THz) corresponding to the bit unit time of the SPL code and supplies the clock C2 to the FIFO memory unit 30. F
The IFO memory unit 30 regards the serial mixed data signal D1 as SPL format serial data based on the clock C2, and only the latter half portion of each bit signal is data-identified by the level determination similar to the NRZ code and sequentially accumulated. For example, in the case of the timing relationship as shown in FIG.
At the falling edge of 2, the bit values “0” and “1” are determined.

On the other hand, the synchronization signal detector 20 uses the clock C1.
Based on the above, the serial mixed data signal D1 is regarded as NRZ format serial data, the level of each bit signal is determined, and the data is identified. For example, in the case of the timing relationship shown in FIG. 2, the bit values “0” and “1” are determined at the rising edge of the clock C1. The identified bit pattern is the synchronization bit pattern (000
When it coincides with 1), it is recognized as the synchronization signal D11, and the data start signal D2 is output to the FIFO memory unit 30 and the timer unit 40 in order to notify that the subsequent data signal D12 should be taken into the CPU unit 50. When the FIFO memory unit 30 receives the data start signal D2, it resets the memory and erases all the data accumulated so far, and the significant data after the synchronization signal D11 (data signal D1
2) Start capturing.

When the timer section 40 receives the data start signal D2, the timer section 40 starts timing, and after the time (t) required for receiving the significant data in the FIFO memory section 30 elapses, an interrupt signal D3 for notifying the CPU is sent. Part 50
Output to. The counting of the time t in the timer unit 40 can be realized by various methods other than directly counting the time value. For example, the number of bits of significant data that should be transmitted as the data signal D12 is used as the initial value of the counter, and the clock C2 is used. This counter value is decremented by 1 every 1 cycle of
When, the timing can be completed. C
The processor 52 of the PU unit 50 uses the interrupt controller 5
When the interrupt signal D3 is received through 6, the processing so far is temporarily suspended, and the external bus controller 55 and the external bus 60
All the necessary significant data accumulated from the FIFO memory unit 30 are fetched as byte-unit NRZ format parallel data, and the process is resumed after the fetching is completed to process the fetched data. As described above, the CPU unit 50 has one
A large amount of data can be processed in byte units with each interruption, and the processing speed can be increased.

By connecting the timer unit 40 to the external bus 60, the timer measurement time value t can be arbitrarily set from the CPU unit 50. In the above embodiment, the timer section 40 is provided separately from the CPU section 50, but a timer counter unit is built in (connected to the internal bus).
By using the CPU described above, the external timer unit 40 becomes unnecessary. In this case, the data start signal D2 output from the synchronization signal detector 20 is used as an interrupt signal for the CPU.
Enter into the department. When the CPU controller receives the interrupt signal by the interrupt controller, the built-in timer / counter unit starts counting the required time t, and when the timeout occurs, the data is fetched from the FIFO memory unit 50.

[0012]

As described above, according to the present invention, when a sync signal which is NRZ format serial data is detected by the sync signal detector, the following SPL (split phase)
The format serial data is sequentially stored in the FIFO memory, and the CPU is interrupted when the timer is started and the required amount of data is stored. Therefore, the CPU only interrupts once regardless of the amount of data. Thus, all the necessary data in the FIFO memory unit can be retrieved, the load of software processing can be reduced, and the reduction in processing speed can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a serial mixed data signal and a waveform example of each part signal.

FIG. 3 is a block diagram of a conventional two-signal format mixed data receiving circuit.

[Explanation of symbols]

 10 clock generation unit 20 synchronization signal detection unit 30 FIFO memory unit 40 timer unit 50 CPU unit

Claims (1)

[Claims] 1. A serial mixed data signal in which NRZ format serial data and split phase format serial data having the same unit time of signal level change are mixed is received, and the NRZ format serial data is a predetermined synchronization signal. In the two-signal format mixed data receiving circuit for taking in the subsequent split phase format serial data as NRZ format parallel data to a CPU that performs control processing based on software when it is detected that there is a bit transmission rate of the NRZ format serial data. A clock generating unit for generating a second clock corresponding to the bit transmission rate of the split phase format serial data from the first clock corresponding to, and monitoring the serial mixed data signal based on the first clock. Detect predetermined sync signal Then, a sync signal detection unit that outputs a data start signal; and, when the data start signal is received, the serial mixed data signal is regarded as the split phase format serial data based on the second clock, and data identification is performed in 1-bit units. F and outputs the accumulated data as NRZ format parallel data in units of a predetermined bit length.
An IFO memory section, and a timer section that, when receiving the data start signal, starts counting a preset time value corresponding to the transmission data amount of the split phase format serial data, and outputs an interrupt signal when the timing is completed, A two-signal format mixed data receiving circuit, comprising: a CPU unit that reads all the data accumulated from the FIFO memory unit when the interrupt signal is received.