JPH0832408A - Delay line filter - Google Patents

Abstract

(57) [Abstract] [Purpose] A variety of filters with characteristics equal to or higher than ordinary analog filters are realized by obtaining coefficient values based on the same Z conversion technique as digital filters, even though they are analog filters. (EN) A filter that can be used in a wide frequency range from a low frequency to a high frequency without causing a decrease in operating speed due to repeated addition for convolutional operations found in digital filters. [Structure] A device for delaying and outputting an analog signal stepwise, and a means for arbitrarily determining the output amplitude is connected to each delayed output, and each output whose output amplitude is determined by the means is synthesized as an analog signal. The first feature is that the delay device outputs two analog signals in a stepwise manner, one delay device being a positive phase of the analog signal, and the other delay device being an analog signal. The second feature is that the driving is performed in the opposite phase of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter device for removing an unnecessary signal from an input signal or adjusting a phase characteristic in an electronic device used for communication or measurement, which is particularly called Z conversion. The present invention relates to a filter whose characteristics are determined by a design technique.

[0002]

2. Description of the Related Art Conventionally, as a filter for processing an analog signal, in addition to a traditional analog filter composed of an inductor and a capacitor, a digital signal converted by an AD converter and then designed by a Z conversion technique is used. A method of returning to an analog signal with a DA converter after processing with a filter has been used.

[0003]

However, although an analog filter can realize a filter that can be used even at high frequencies, it is difficult to design a filter that meets high design specifications.
On the other hand, although a digital filter can obtain characteristics that cannot be realized by an analog filter, in order to use it at a high frequency, it is necessary to use an arithmetic unit for executing multiplication and convolution operation at higher speed, which is often impossible. It is an object of the invention to provide a filter which does not have such drawbacks of the prior art.

[0004]

According to the present invention, an apparatus for delaying and outputting an analog signal in a stepwise manner is connected to a means for arbitrarily determining the output amplitude for each delayed output. The first feature is that the device comprises a device for synthesizing the determined outputs as analog signals.

In this structure, two sets of devices for delaying and outputting an analog signal in stages are provided, one delay device is driven in a positive phase of the analog signal, and the other delay device is driven in a reverse phase of the analog signal. This is the second feature.

[0006]

Next, the operation of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the present invention. In the figure, 1 is an analog signal source, 2 and 3 are terminating resistors adapted to the characteristic impedance of a delay line consisting of a winding 4 for generating a distributed inductance and a polar plate 5 for generating a distributed capacitance, and 6 to 9 are delays. A buffer amplifier that improves the load drive capability of the line and determines the output polarity, 10 to 1
3 is a device that determines the magnitude of the current flowing out from each buffer amplifier, and 14 is an operational amplifier that constitutes an adder together with the resistor 15.

Explaining in a little more detail with reference to FIG. 1,
Since the delay line consisting of the winding wire 4 and the pole plate 5 is terminated by the resistors 2 and 3 having a resistance value equal to the characteristic impedance, each tap of the winding wire 4 has the same waveform as that of the signal source 1 and an amplitude of Half of the signals are output, and each signal is shifted stepwise on the time axis. Further, each signal is added with a polarity by a buffer amplifier, weighted by a device that determines the magnitude of current, and then combined by an adder. In the simplest example, a resistor can be used as a device for determining the magnitude of the current, and the weighting coefficient can be determined by the resistance value, and the coefficient can be determined by the gain of the buffer amplifier while keeping the resistance value constant. You can also decide. In such a configuration, even though the circuit is an analog circuit, by replacing the gradual delay time with the sampling time in the digital filter, it becomes possible to design the filter by the Z-transform technique like the digital filter, and the weighting coefficient is used. It is possible to obtain filters with various characteristics simply by changing. Note that although FIG. 1 shows a format called an FIR system in the Z-transform technique, it is also possible to construct a filter in the IIR system format.

[0008]

FIG. 2 shows an embodiment of the present invention in which 16 is a delay line, 17 to 21 are coefficient setting resistors, and 22 is an output buffer amplifier. This embodiment is applicable when the coefficients of the taps are all positive and the resistance values of the resistors 17 to 21 can be selected to be much larger than the characteristic impedance of the delay line. At this time, if one tap is focused, the coefficient setting resistors of the other taps work as load resistances, so addition and synthesis are performed without using a complete adder by an operational amplifier, and the output can be taken out by a simple buffer amplifier. You can

FIG. 3 shows a second embodiment of the present invention, in which 23 is an input buffer amplifier for supplying a positive phase output and a negative phase output, and 2.
4 is a delay line driven by a positive phase output, 25 is a delay line driven by a negative phase output, 26 and 27 are termination resistors thereof, 28 is a buffer amplifier for output, and a resistor 29.
˜33 and 34, 35 are resistors that set the coefficient of each tap. The taps T1 to T5 of the delay line 24 and the taps T1 to T5 of the delay line 25 have the same delay in stages and output signals of opposite phases. As a result, in this embodiment, the coefficients set by the resistors 29 to 33 act as positive values, and the coefficients set by 34 and 35 act as negative values. Thus, if the polarities and magnitudes of the coefficients are given by the Z conversion, the present invention can be realized as an analog filter.

FIG. 4 shows a third embodiment of the present invention, in which 36 is A.
D converter, 40 to 43 are DA converters, 37 to 3
Reference numeral 9 is a shift register, and 44 to 47 are resistors for setting the coefficient of each tap. This embodiment is realized by introducing a digital circuit into the analog delay line portion, and has the characteristic that the filter band is determined by the clock frequency of the digital circuit portion.
The digital processing also has the feature of the present invention that the convolution operation that takes the longest time is executed instantaneously, and can be applied to the processing of high-speed signals such as video signals. The polarity of each coefficient can be determined by the DA converter, and the coefficient value itself can also be determined by the DA converter if a multiplying DA converter is used.

[0011]

As described above, according to the present invention, although it is an analog filter, it has characteristics equal to or higher than those of a normal analog filter only by obtaining coefficient values based on the Z conversion technique similar to a digital filter. It is possible to realize various filters, and it is possible to provide a filter that can be used in a wide frequency range from low frequency to high frequency without causing a decrease in operating speed due to repeated addition for convolutional operation found in digital filters. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a first embodiment of the present invention.

FIG. 3 is a second embodiment of the present invention.

FIG. 4 is a third embodiment of the present invention.

[Explanation of symbols]

1 Analog signal source. 2,3,26,27 Termination resistors. 4 Windings that make up the delay line. 5 A capacitor that forms a delay line. 6, 7, 8, 9 Buffer amplifier. 10, 11, 12, 13 A device for determining the magnitude of electric current. 14 Operational amplifier. 15 Feedback resistor. 16, 24, 25 delay lines. 17, 18, 19, 20, 21 Resistors that set coefficient values. 22 Output buffer amplifier. 23 Input buffer amplifier. 29, 30, 31, 32, 33, 34, 35 Resistors for setting coefficient values. 36 AD converter. 37, 38, 39 shift registers. 40, 41, 42, 43 DA converter. 44, 45, 46, 47 Resistors that set coefficient values.

Claims (2)

[Claims] 1. A device for delaying and outputting an analog signal stepwise, and a means for arbitrarily determining an output amplitude is connected to each delayed output, and each output whose output amplitude is determined by the means is connected to an analog signal. A delay line filter consisting of a device that synthesizes as it is. 2. The apparatus according to claim 1, wherein two sets of devices for delaying and outputting the analog signal in stages are provided, one delay device being in a positive phase of the analog signal, and the other delay device being an analog signal. A delay line filter that is driven in reverse phase.