JPH0832941A - High-definition TV receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a high-definition television receiver in which the capacity of an image memory and the circuit scale of a signal processing circuit are reduced. In the inter-frame interpolation circuit 112, the digital MUSE signal is first encoded by the encoder 401, and the encoded signal in which the number of bits per pixel is reduced is written in the field memories 402a and 402b. Be done. Decoder
The signal of the current field is obtained from 403a, and the signal of the previous field is obtained from the decoder 403b and supplied to the multiplexer 420. The time-division multiplexed signal in the multiplexer 420 is processed in the low-pass filter 421 and the sampling frequency conversion circuit 422 of one system, and the demultiplexer 4
At 23, the signal is separated into the signal corresponding to the current field and the signal one field before, and processed and output by the inter-field interpolation circuit 20. Since the signals are encoded and processed in a time-division multiplexed state, the memory capacity and circuit scale can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition television receiver for decoding a high-definition television signal which has been band-compressed and transmitted into an original high-definition television signal, and particularly to a memory capacity and a circuit required for decoding processing. The present invention relates to a signal processing circuit capable of reducing the scale and capable of decoding a high-definition television signal transmitted using a digital modulation method.

[0002]

2. Description of the Related Art One of the methods for compressing and transmitting a wide band high-definition television signal into a practical level band that can be transmitted is a multiple sub-sampling transmission system using offset sub-sampling between frames and fields, for example, MUS
There is an E (Multiple Sub-Nyquist Sampling Encoding) method. Signals band-compressed using the MUSE method (hereinafter,
The MUSE signal) is transmitted as a satellite broadcast wave using, for example, an FM (frequency modulation) system, and a test broadcast using a broadcasting satellite has already been carried out (Ninomiya, et al., “High-definition television satellite”). 1-channel transmission system ”Technical Report of the Television Society TEBS 95-2 VOL7 No.44).

FIG. 17 is a block diagram of a high-definition television receiver for receiving the broadcast wave. In FIG. 17, 1 is an FM demodulator, 2 is a MUSE decoder, and 3 is a display.
The satellite broadcast wave transmitted in the SHF band is converted into an intermediate frequency signal via a frequency converter (not shown) and input to the FM demodulator 1. The intermediate frequency signal supplied to the FM demodulator 1 is demodulated to the original baseband MUSE signal.
The demodulated baseband MUSE signal is supplied to the MUSE decoder 2. In the MUSE decoder 2, the input baseband MUSE signal is digitized by the A / D converter 201, and then the waveform equalizer 202 and the non-linear de-emphasis circuit 203 respectively perform the waveform equalization process and the non-linear de-emphasis process. ,
It is supplied to the MUSE decoding processing circuit 210.

FIG. 18 is a diagram showing the configuration of the MUSE decoding processing circuit 210. In FIG. 18, the input digital MU
The SE signal is supplied to the interframe interpolation circuit 11. The interframe interpolating circuit 11 has a switch 12 to which the digital MUSE signal is supplied to one input terminal, and a field memory 13 having a storage capacity capable of writing the digital MUSE signal output from the switch 12 for two fields.
And a field memory 14 having a storage capacity capable of writing the digital MUSE signal read from the field memory 13 for two fields. The digital MUSE signal read from the field memory 14 is supplied to the other input terminal of the switch 12.

Here, the inter-frame interpolation circuit 11 uses the two field memories 13 and 14 to sequentially interpolate digital MUSE signals for a total of four fields. The switch 12 operates in accordance with the sub-sampling phase control signal transmitted together with the digital MUSE signal. That is, with respect to the supplied digital MUSE signal, a signal obtained by interpolating a signal of the current field and a signal of two fields before the frame is obtained from the switch 12, and 1 from the field memory 13.
A signal obtained by interpolating the signal before the field and the signal before the three fields between frames is obtained.
Signals obtained by interpolating the signal before the field and the signal before the four fields are obtained respectively.

The signal interpolated between frames output from the switch 12 is a static area processing circuit 15 and a moving area processing circuit 30.
And the motion detection circuit 35, respectively. Further, the static area processing circuit 15 is supplied with the interpolated signal from the field memory 13 which is delayed by one field.

First, in the static region processing circuit 15, the inter-frame interpolated signal from the switch 12 is passed through the low-pass filter 17 and the sampling frequency conversion circuit 19 to one input terminal of the inter-field interpolating circuit 20. Supplied. Further, the inter-frame interpolated signal from the field memory 13 is similarly supplied to the other input terminal of the inter-field interpolating circuit 20 via the low-pass filter 16 and the sampling frequency converting circuit 18. Here, the two signals supplied to the inter-field interpolation circuit 20 are delayed by one field, and the inter-field interpolation circuit 20 performs inter-field interpolation processing using the two signals, and An interpolation signal is generated. As a result, the inter-field interpolating circuit 20 interpolates the signals of four fields and outputs them as a still area processed signal. The static region processing signal is supplied to one input terminal of the mixing circuit.

On the other hand, in the moving area processing circuit 30, the switch 12
The inter-frame interpolated signal from the subsample circuit 31
Is supplied to. The sub-sampling circuit 31 is the digital M
According to the control signal of the sub-sampling phase transmitted together with the USE signal, only the signal component of the current field is extracted. The current field signal output from the sub-sampling circuit 31 is supplied to the field interpolation circuit 32. The field interpolation circuit 32 is a horizontal and vertical two-dimensional filter, and performs field interpolation processing on the current field signal to generate an intrafield interpolation signal. The intra-field interpolated signal is supplied to the other input terminal of the mixing circuit 36 as a moving area processing signal after the sampling frequency is converted by the sampling frequency conversion circuit 33.

The motion detection circuit 35 is for generating a motion detection signal corresponding to the motion component of the picture based on the signal interpolated from the switch 12 between the frames.

In the mixing circuit 36, the stationary area processing signal and the moving area processing signal are mixed at a ratio based on the motion detection signal and output as a mixed signal. The mixed signal is separated into a Y signal, an RY signal and a BY signal in a TCI (Time Compressed Integration) decoding circuit 21. The Y signal is supplied to the inverse matrix circuit 41. The RY signal and the BY signal are supplied to the inverse matrix circuit 41 via the low-pass filters 39 and 40, respectively. The R signal, G signal, and B signal obtained as the output signals of the inverse matrix circuit 41 are gamma-corrected by the gamma correction circuits 42, 43, and 44, respectively, and M shown in FIG.
It is output as an output signal of the USE decoding processing circuit 210. The output signal of each D / A converter 204, 205,
At 206, it is converted to an analog signal and displayed on the display 3 as the original broadband high-definition television signal.

[0011]

However, as described above, the MUSE decoding processing circuit used in the high-definition television receiver currently in practical use has a large capacity for still area processing or motion detection processing. Has a problem that it requires a memory (for convenience, about 8 Mbits in the above configuration), which has been an obstacle to the price reduction of high-definition television receivers.

Further, the low-pass filter, the sampling frequency conversion circuit, the gamma correction circuit, and the like in the static region processing or the moving region processing have a configuration in which a plurality of similar circuits are provided, and there is a problem that the circuit scale increases. It was

Further, the high-definition television broadcasting currently put into practical use is a broadcast using an analog modulation system such as an FM system or an AM system (hereinafter referred to as analog high-definition television broadcasting), and transmission line distortion, noise, etc. It is easily affected and image quality deterioration is likely to occur. Therefore, in the advanced information society of the future, a broadcast (hereinafter, referred to as a broadcast that transmits a band-compressed signal using the MUSE method using the digital modulation method)
Naturally, a form called digital high-definition television broadcasting) is also conceivable. However, the conventional high-definition television receiver has a problem that it is not configured in consideration of such support for digital high-definition television broadcasting.

The present invention solves the above-mentioned problems of the prior art, and provides a high-definition television receiver capable of receiving a digital high-definition television broadcast by significantly reducing the memory capacity and the circuit scale. Is.

[0015]

To achieve this object, the present invention is a decoder for demodulating a transmitted image signal to obtain a high-definition television signal, which has an encoding means for encoding the image signal. It is characterized by

Further, the encoding means is characterized by using a predictive encoding means.

Further, in a decoder for demodulating the transmitted image signal to obtain a high-definition television signal, an encoding means for encoding the image signal and an output signal encoded by the encoding means are inter-frame interpolated. And inter-frame interpolation means for

Further, in a decoder for demodulating a transmitted image signal to obtain a high-definition television signal, an interframe interpolating means for interpolating the image signal between frames, and an output signal of the interframe interpolating means for one field. It is characterized by comprising delay means for delaying by a period and multiplexing means for time division multiplexing the output signal of the interframe interpolation means and the output signal of the delay means.

Further, in a decoder for demodulating a transmitted image signal to obtain a high-definition television signal, an interframe interpolating means for interpolating the image signal between frames, and an output signal of the interframe interpolating means for one field. Delay means for delaying by a period, field interpolation means for field interpolation of the image signal, output signal of the interframe interpolation means, output signal of the delay means and output signal of the field interpolation means And a multiplexing means for time-division multiplexing.

The interframe interpolating means includes an encoding means for encoding the input image signal, an interframe interpolating means for interframe interpolating the encoded signal output from the encoding means, and the frame. And a decoding means for decoding the coded signal interpolated between the frames output from the interpolating means.

Further, in a decoder for demodulating the transmitted image signal to obtain a high-definition television signal, multiplexing means for time-division multiplexing the demodulated R signal, G signal and B signal, and an output signal from the multiplexing means. And a separating means for separating the R signal, the G signal, and the B signal from the output signal of the nonlinear converting means, respectively.

Further, the non-linear conversion means is characterized by correcting the gamma characteristic of the display.

Further, high-definition television broadcasting in which a band-compressed signal obtained by band-compressing a high-definition television signal using a multiple subsampling method is transmitted using an analog modulation method, and the band-compressed signal is transmitted using a digital modulation method. A high-definition television receiver for receiving high-definition television broadcasts, wherein analog demodulation means for demodulating a band-compressed signal transmitted using the analog modulation method into an original band-compressed signal, and the digital modulation method are provided. A digital demodulation means for demodulating the band-compressed signal transmitted using the original band-compressed signal; a selection means for selectively outputting the output signal from the analog demodulation means and the output signal from the digital demodulation means; And a decoding means for demodulating the band compressed signal selected by the selecting means into an original high-definition television signal. Accordingly and controlling said selection means.

Further, a high-definition television broadcast in which a band-compressed signal obtained by band-compressing a high-definition television signal using a multiple sub-sampling method is transmitted using an analog modulation method, and the band-compressed signal is transmitted using a digital modulation method. A high-definition television receiver for receiving high-definition television broadcasts, wherein analog demodulation means for demodulating a band-compressed signal transmitted using the analog modulation method into an original band-compressed signal, and the digital modulation method are provided. A digital demodulation means for demodulating the band-compressed signal transmitted using the original band-compressed signal; a selection means for selectively outputting the output signal from the analog demodulation means and the output signal from the digital demodulation means; Decoding means for demodulating the band-compressed signal selected by the selecting means into the original high-definition television signal, and the analog demodulating means The detecting the synchronization state of the force signal 1
Synchronization detecting means and second synchronization detecting means for detecting the synchronization state of the output signal from the digital demodulating means, and the selecting means is selected according to the detection results from the first and second synchronization detecting means. It is configured so that it is controlled.

[0025]

According to the above construction, the number of bits per pixel can be reduced by encoding the input image signal.

Further, since the input image signal is coded by the coding means and the inter-frame interpolation processing is performed in the coded signal state, the capacity of the field memory and the scale of the inter-frame interpolation processing circuit can be reduced.

Further, a circuit required for the processing is provided for time-division-multiplexing the inter-frame interpolated signal and the inter-frame interpolated signal delayed by one field by the delaying means by the multiplexing means, and performing the processing in the multiplexed signal state. Only one system is required and the circuit scale can be reduced.

Further, the interframe interpolated signal, the interframe interpolated signal delayed by one field, and the field interpolated signal for interpolating the image signal in the field are time-division-multiplexed to perform processing in a multi-signal state. The number of circuits required for processing is one, and the circuit scale can be reduced.

Further, multiplexing means for time-division-multiplexing the demodulated R signal, G signal, and B signal, nonlinear conversion means for performing nonlinear correction in the multiplexed signal state, and R signal, G from its output
The circuit scale of the gamma correction circuit can be reduced by the separating means for separating the signal into the B signal.

Furthermore, digital high-definition television broadcasting can also be performed by digital demodulating means for demodulating a high-definition television signal transmitted using a digital modulation method and selecting means for selecting the output signals of the digital demodulating means and the analog demodulating means. Can be received.

Further, by the synchronization detecting means for detecting the synchronization state of the received signal whether it is of the analog modulation system or the digital modulation system, whichever system is used, the optimum reception mode is automatically switched. be able to.

[0032]

Embodiments of the present invention will now be described in detail with reference to the drawings.

The operation of the field memory unit according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the field memory unit of the first embodiment. In FIG. 1, 401 is an encoder, 402 is a field memory, and 403 is a decoder.

The image signal input in FIG. 1 is first encoded by the encoder 401, and the encoded signal in which the number of bits per pixel is reduced is written in the field memory 402. The signal read from the field memory 402 is supplied to the decoder 403. The decoder 403 has an inverse relationship with the encoder 401, and an original image signal delayed by a desired period (in this case, one field period) is obtained as an output signal.

As described above, according to the present embodiment, since the coded signal in which the number of bits per pixel of the image signal is reduced by coding is written in the memory, the memory capacity required for delaying for a desired period is obtained. It can be reduced significantly. For example, if the number of bits per pixel is reduced to 1 / N, the memory capacity required for delaying for a desired period can also be reduced to 1 / N.

FIG. 2 shows an example of the configuration of the encoder 401 shown in FIG. In FIG. 2, 411 is a subtractor, 412 is a quantizer, and 413
Is a local decoder, 414 is a predictor, 415 is an adder, and 416 is an inverse quantizer. This is a well-known predictive encoder, in which the value of the input pixel signal of interest is predicted by using the predictor 414, and the prediction error obtained by the subtractor 411 is encoded by using the quantizer 412. . In the local decoder 413, a prediction error is obtained in the output of the dequantizer 416. Therefore, the adder 415
In, the decoded signal corresponding to the pixel signal of interest is obtained as the addition result by sequentially adding to the predicted value. By thus incorporating the decoder into the encoder for operation, it is possible to prevent the accumulation of quantization distortion.

FIG. 3 shows an example of the configuration of the decoder 403 shown in FIG. 1. In FIG. 3, 414 is a predictor, 415 is an adder, and 416 is an inverse quantizer. This has the same configuration as the local decoder 413 shown in FIG. 2, and supplies the encoded signal read from the field memory 402 as the input signal of the dequantizer 416 and outputs the output signal of the dequantizer 416. By sequentially adding the prediction error and the prediction value from the predictor 414 in the adder 415, a decoded signal corresponding to the pixel signal delayed by the desired period is obtained as the addition result.

When the input image signal is, for example, a MUSE signal, since the MUSE signal is a band-compressed signal using the multiple offset subsampling method, the correlation between pixels is high, and the predictive coding method is the coding method. It is suitable.

The coding method is not limited to predictive coding, and transform coding such as discrete cosine transform may be used. Further, if reversible coding such as variable length coding is used as a coding method, there is an advantage that image quality deterioration due to coding / decoding does not occur at all. Also, a combination of predictive coding and variable length coding may be used. In this case, the memory capacity can be further reduced.

FIG. 4 is a structural example of an interframe interpolating circuit in the MUSE decoding processing circuit using the structure of the field memory section shown in FIG. 1 of the first embodiment. In FIG. 4, 111 is an interframe interpolating circuit, 12 is a switch, and 401
a, 401b are encoders, 402a, 402b are field memories, 403
Denoted at a and 403b are decoders. MUS shown in FIG. 18 of the conventional example
The difference from the inter-frame interpolation circuit 11 of the E decoding processing circuit is that the field memories 13 and 14 of FIG. 18 are replaced with the configuration of the field memory unit shown in the first embodiment. Therefore, it is the same that the delay operation is performed for each one field period, and if the configuration of the field memory unit shown in the first embodiment of the present invention is used, the inter-frame interpolation which greatly reduces the memory capacity is performed. The circuit 111 can be realized.

Next, the operation of the interframe interpolation circuit in the second embodiment of the present invention will be described. FIG. 5 is a block diagram showing an inter-frame interpolation circuit of the second embodiment.
, 112 is an interframe interpolating circuit, 12 is a switch, 401
Is an encoder, 402a and 402b are field memories, and 403a and 403b
Is a decoder. Inter-frame interpolation circuit 11 described in FIG.
The difference from 1 is that switch 12 and field memory 402
The point is that the encoder 401 and the decoders 403a and 403b are provided outside the inter-frame interpolation loop composed of a and 402b.

First, the input digital MUSE signal is encoded by the encoder 401 and supplied to one side of the switch 12. Switch 12 and field memory 40
The inter-frame interpolation processing realized by 2a and 402b is the same as the conventional example, except that the signal to be interpolated is replaced with a coded signal. Therefore, the coded signal interpolated between the frames of the current field is obtained from the switch 12, and the coded signal interpolated between the frames of one field before is obtained from the field memory 402a. The inter-frame interpolated coded signal is decoded by the decoders 403a and 403b into the inter-frame interpolated signal of the current field and the inter-frame interpolated signal of the previous field.

As described above, according to the second embodiment, by providing the encoder and the decoder outside the interframe interpolation processing loop, as in the interframe interpolation circuit 111 shown in FIG. The encoding and decoding processes are not repeated for the same signal in the loop, and the image quality deterioration due to the encoding / decoding can be minimized. Further, since inter-frame interpolation processing is performed using a coded signal in which the number of bits per pixel is reduced, it is possible to reduce the scale of the circuit required for the processing. Furthermore, when the field memory is provided as a separate chip outside the signal processing LSI, the number of pins required for input / output can be significantly reduced.

The method of reducing the memory capacity described in the first and second embodiments is not limited to the application to the interframe interpolating circuit, but the three-dimensional Y / N used in the NTSC television receiver. It goes without saying that the present invention can also be applied to a frame memory of a C separation circuit or a field memory of a scanning line conversion circuit.

Next, the MU in the third embodiment of the present invention.
The operation of the SE decoding processing circuit will be described. 6 is a block diagram of the MUSE decoding processing circuit of the third embodiment. In FIG. 6, 112 is an interframe interpolating circuit, 151 is a static area processing circuit, 420 is a multiplexer, 421 is a low-pass filter, and 422 is a sampling frequency. A conversion circuit, 423 is a demultiplexer, and 20 is an inter-field interpolation circuit.

First, the interframe interpolation circuit 112 is the same as that described in FIG. Therefore, the decoder 40
A signal interpolated between frames of the current field is obtained from 3a, and a signal interpolated between frames of one field before is obtained from the decoder 403b, and supplied to the multiplexer 420.

As an example, FIG. 7 shows signals for explaining the operation of the MUSE decoding processing circuit. Two input signals for each pixel shown in FIG. 7A are time-division multiplexed in the multiplexer 420 as shown in FIG. 7B and are supplied to the low-pass filter 421.

FIG. 8 is a structural example showing the circuit of the low-pass filter 421. In FIG. 8, 61 is a 1-pixel delay device, 62,
63, 64, 65 and 66 are coefficient multipliers and 67 is an adder. FIG.
As is clear from the configuration shown in Fig. 7, this is a transversal filter in which the tap interval is 2 pixels, but the input multiplexed signal is one that is multiplexed in 1 pixel units as shown in Fig. 7 (b). Therefore, as shown in FIG. 8, if processing is performed using pixel signals derived at two pixel (even number) intervals, crosstalk between multiple signals does not occur.

The sampling frequency of the filtered signal shown in FIG. 7C is converted by the sampling frequency conversion circuit 422. The sampling frequency conversion can also be basically configured based on the same idea as the low pass filter 421. The signal whose sampling frequency has been converted (FIG. 7D) is separated by the demultiplexer 423 into a signal corresponding to the current field and a signal corresponding to the previous field (FIG. 7E). The separated signals are inter-field interpolated by the inter-field interpolator 20 and output as a still area processed signal (FIG. 7 (f)).

As described above, according to the third embodiment, the signal interpolated between the frames of the current field and the signal interpolated between the frames one field before in the still region processing are time-division multiplexed. Since the processing is performed in step 1, the low pass filter 421 and the sampling frequency conversion circuit 422 may each be provided in one system, and the circuit scale can be significantly reduced.

Next, the MU in the fourth embodiment of the present invention.
The operation of the SE decoding processing circuit will be described. FIG. 9 is a block diagram of the MUSE decoding processing circuit of the fourth embodiment. In FIG. 9, 112 is an interframe interpolation circuit, 31 is a sub-sampling circuit, 32 is a field interpolation circuit, 425 is a multiplexer, and 426 is A low pass filter, 427 is a sampling frequency conversion circuit, 428 is a demultiplexer, 20 is an inter-field interpolation circuit, and 36 is a mixing circuit.

First, the operation of the inter-frame interpolation circuit 112 is the same as that described in FIG. 5, and the signal interpolated between the frames of the current field from the decoder 403a and the decoder
The signals interpolated between the frames one field before are obtained from 403b and supplied to the multiplexer 425. Further, the signal interpolated between the frames of the current field is transmitted via the sub-sampling circuit 31 to the field interpolation circuit.
It is also supplied to 32. As I explained the operation in the conventional example,
An in-field interpolation signal is obtained as an output signal of the field interpolation circuit 32 and supplied to the multiplexer 425. The multiplexer 425 is the same as the multiplexer 420 described in the third embodiment and is expanded to have three inputs. The three input signals supplied are time-division multiplexed for each pixel,
The multiplexed signal is supplied to the low pass filter 426.

FIG. 10 is a structural example showing the circuit of the low-pass filter 426. In FIG. 10, 61 is a one-pixel delay device, 70,
71, 72, 73 and 74 are coefficient multipliers, 75 is a coefficient generator and 67 is an adder. As is clear from FIG. 10, the low-pass filter 426 is a transversal filter having a tap interval of 3 pixels because the multiplexed signal to be processed is a multiplexed signal of three signals. The coefficient multipliers 70, 71, 72, 73 and 74 are controlled to switch the coefficients in synchronism with. That is, for the intra-field interpolated signal portion of the multiplexed signal, for example, the coefficient multiplier 72 is set to 1
In addition, the other coefficient multipliers are set to 0 so that the filtering process is not performed. Filtering processing is performed by setting the coefficient multiplier to a significant value in the other portions corresponding to the interpolated signals.

The multiplexed signal thus controlled is then supplied to the sampling frequency conversion circuit 427. The sampling frequency conversion circuit 427 is basically a low-pass filter 4 as well.
It can be configured based on the same idea as in 26. Therefore,
In the portion corresponding to the signal interpolated between frames in the input multiple signal, a coefficient for static region processing is generated to perform processing with optimum characteristics. In addition, in the portion corresponding to the signal interpolated in the field, a coefficient for moving area processing is generated to perform processing with optimum characteristics.

The sampling frequency-converted multiplex signal thus processed is demultiplexed by the demultiplexer 428.
Is separated into a signal corresponding to the current field, a signal corresponding to the immediately preceding field, and a motion area processing signal. The separated signal corresponding to the current field and the signal corresponding to the immediately preceding field are interpolated between the fields in the inter-field interpolating circuit 20 and used as a static region processing signal to be mixed by the mixing circuit 36.
Is supplied to one of the input terminals. The separated motion area processing signal is supplied to the other input terminal of the mixing circuit 36.
The mixing circuit 36 mixes the still area signal and the moving area signal according to the motion detection signal from the motion detecting circuit 35 described in the conventional example, and outputs the mixed signal as a decoded signal.

As described above, according to the fourth embodiment, the inter-frame interpolation signal of the current field, the inter-frame interpolation signal of the previous field and the intra-field interpolation signal of the current field are time-division multiplexed. Since the processing is performed, the low-pass filter 426 and the sampling frequency conversion circuit 427 can perform the static region processing and the dynamic region processing by one system, respectively, as in the third embodiment, and thus the circuit scale can be significantly reduced. Become.

Next, the operation of the gamma correction circuit according to the fifth embodiment of the present invention will be described. FIG. 11 is a block diagram of the gamma correction circuit of the fifth embodiment. In FIG.
Is a multiplexer, 431 is a non-linear conversion circuit, and 432 is a demultiplexer.

First, the multiplexer 430 of FIG. 11 is supplied with the R, G, and B signals output from the inverse matrix circuit 41 described in the conventional example. FIG. 12 shows signals for explaining the operation of the gamma correction circuit. In the multiplexer 430, the R signal, the G signal shown in FIG.
The B signal is time-division multiplexed for each pixel (FIG. 12B), and the multiplexed signal is supplied to the non-linear conversion circuit 431. The non-linear conversion circuit 431 has a gamma correction characteristic, for example, R
The demultiplexer 432 is composed of an OM (read only memory) and performs nonlinear conversion on the input multiplexed signal.
(FIG. 12 (c)). In the demultiplexer 432, the gamma-corrected multiplexed signal is converted into an R signal, as shown in FIG.
Separately output to G signal and B signal.

As described above, according to the fifth embodiment, since the gamma correction process is performed in the state where the R signal, the G signal, and the B signal are time-division multiplexed, the non-linear conversion circuit 43 for realizing the gamma correction.
1 is sufficient for 1 system, and it is possible to significantly reduce the circuit scale.

Next, the operation of the high-definition television receiver according to the sixth embodiment of the present invention will be described. FIG. 13 is a block diagram of the high-definition television receiver of the sixth embodiment. In FIG. 13, 1 is an FM demodulator, 2 is a MUSE decoder, 3 is a display, 510 is a digital demodulator, 520 is a digital decoder, Reference numeral 530 is a selection switch. The difference from the configuration of the conventional high-definition television receiver shown in FIG. 17 is that it has a digital demodulator 510, a digital decoder 520, and a selection switch 530.
Is newly provided to convert the input intermediate frequency signal to a digital demodulator 51.
0, to one input terminal of the selection switch 530 via the digital decoder 520, and to the non-linear de-emphasis circuit 20
The output signal from 3 is supplied to the other input terminal of the selection switch 530, and the output of the selection switch 530 is input to the MUSE decoding processing circuit 210.

First, in FIG. 13, the selection switch 530 is controlled according to the reception channel selection signal. For example, in the case of receiving a high quality television broadcast by the FM system, the selection switch 530 selects the output signal from the non-linear de-emphasis circuit 203. The digital MUSE signal is
MUSE decoding processing circuit 210 via selection switch 530
And is decoded into the original high definition television signal.

On the other hand, when receiving a digital high-definition television broadcast, the selection switch 530 selects the output signal from the digital decoder 520. Digital high-definition television broadcasting may be transmitted in the SHF band or a frequency band higher than that, but is supplied to the digital demodulator 510 after being converted into an intermediate frequency signal through a frequency converter (not shown). The digital demodulator 510 performs demodulation processing according to the digital modulation method on the transmission side, and the demodulated digital signal is supplied to the digital decoder 520.

The MUSE signal is about 13 in the baseband state.
It has a data rate of 0 Mbit / sec (16.2 MHz x 8 bits).
For example, when digital modulation is performed using QPSK (Quadrature Phase Shift Keying), the transmission efficiency of QPSK is 2 bits / sec / Hz in principle, so the bandwidth after modulation is about 6
It becomes 0MHz. As it is, it is not possible to transmit using the band of about 30 MHz of one channel of the current BS broadcasting. Therefore, using a digital encoding means such as DPCM (Differential PCM), the MUSE signal is further halved before digital modulation. It needs to be compressed to some extent. The processing of the digital decoder 520 corresponds to the digital encoding processing on the transmitting side used in this sense. When the digital modulation / demodulation means to be used fits within the band of one satellite channel, or when a sufficiently wideband channel is available, there may be a transmission form that does not require digital encoding / decoding processing.

By such processing, the digital decoder
A digital MUSE signal is obtained as an output signal from 520. The digital MUSE signal is supplied to the MUSE decoding processing circuit 210 via the selection switch 530 and decoded into the original high definition television signal.

As described above, according to the sixth embodiment, the FM
It is possible to receive not only analog high-definition TV broadcasts according to the system, but also digital high-definition TV broadcasts that are not easily affected by transmission line distortion and noise, and higher quality when receiving digital high-definition TV broadcasts. It is possible to obtain a clear image.

Next, the operation of the high-definition television receiver according to the seventh embodiment of the present invention will be described. FIG. 14 is a block diagram of the high-definition television receiver of the seventh embodiment. In FIG. 14, 1 is an FM demodulator, 2 is a MUSE decoder, 3 is a display, 510 is a digital demodulator, 520 is a digital decoder, Reference numeral 600 is a first synchronization detection circuit, 610 is a second synchronization detection circuit, and 620 is a determination circuit. The difference from the configuration of the high-definition television receiver in the sixth embodiment shown in FIG.
Sync detection circuit 600, second sync detection circuit 610, determination circuit 620
Is newly provided, and the output signal from the A / D converter 201 is the first
The output signal of the digital decoder 520 is supplied to the second synchronization detection circuit 610 to the synchronization detection circuit 600, and the output signals from the first synchronization detection circuit 600 and the second synchronization detection circuit 610 are supplied to the determination circuit 620. This is that the output signal from 620 controls the selection switch 530.

First, if the received signal is analog high-definition television broadcasting, the first sync detection circuit 600 connected to the A / D converter 201 outputs a signal A: 1 indicating that it is in the sync state. Meanwhile, the second connected to the digital decoder 520
The synchronization detection circuit 610 outputs a signal B: 0 indicating the asynchronous state. The judgment circuit 620 judges the states of the inputs A and B and obtains the judgment output C. The judgment output is C: 1 when the analog high-definition television broadcast is received, and C: 0 when the digital high-definition television broadcast is received. When the judgment output C is 1, the selection switch 530 selects the output signal from the non-linear de-emphasis circuit 203. When the judgment output is C: 0, the selection switch 530 selects the output signal from the digital decoder 520.

As described above, according to the seventh embodiment, it is determined whether the received signal is in the analog high-definition television broadcast or the digital high-definition television broadcast by detecting the presence or absence of the synchronization state. Since the processing can be automatically switched, the viewer does not have to manually switch the processing even when analog high-definition television broadcasting and digital high-definition television broadcasting are performed on the same channel.

FIG. 15 is a structural example showing the first synchronization detection circuit 600. The digital MUSE signal supplied to the first synchronization detection circuit 600 is supplied to the clock recovery circuit 601. The clock recovery circuit 601 receives the MUS from the input digital signal.
Regenerates the system clock required for E-decoding processing.
The input digital MUSE signal includes a horizontal synchronizing signal serving as a reference, and a phase locked loop is used to generate a system clock synchronized with this. At this time, a phase error between the sync signal obtained by dividing the internally generated system clock and the sync signal included in the input signal is detected, and the phase of the internal clock is controlled according to the error.
When the digital MUSE signal from the D converter 201 is not normal (corresponding to the case where a digital high definition television broadcast is received), a large error output is obtained and the digital MU is obtained.
If the SE signal is normal, the error output is small. By monitoring this error output, it is possible to determine whether or not the recovered clock is in the synchronization state, and the error output is supplied to the synchronization determination circuit 602. The synchronization determination circuit 602 outputs the determination output A: 1 when the error is small, and outputs the determination output A: 0 when the error is large.

The configuration of the second synchronization detection circuit 610 is also basically the same as that shown in FIG. 15, and the judgment output B is 1 when digital high-definition television broadcasting is received, and the judgment output B when analog high-definition television broadcasting is received. : Outputs 0.

FIG. 16 is a concrete example of the determination circuit 620. The decision circuit 620 is a well-known RS flip-flop,
When A: 1 and B: 0, C: 1, and A: 0 and B:
In the case of 1, it becomes C: 0. When both A and B are 0, the previous state is held as a synchronization detection error. This enables stable determination.

Although the judgment output B is detected by using the digitally decoded digital MUSE signal, the present invention is not limited to this. The frame synchronization signal and the internally generated frame included in the digital sequence after demodulation by the digital demodulator 510 are not limited to this. You may detect based on the phase error with a synchronizing signal. This processing is basically included in the digital demodulator 510, so that the second synchronization determination circuit is unnecessary.

In the description of the sixth and seventh embodiments, the high-definition television broadcasting is assumed to be via a satellite, but the present invention is not limited to this, and the present invention can be applied to wired transmission such as CATV. High-quality TV receivers can be used.

Further, although the analog high-definition television broadcasting is shown by using the FM system, the present invention is not limited to this, and the AM system may be used. In that case, an AM demodulator may be used instead of the FM demodulator.

[0075]

As described above, according to the first aspect of the present invention.
According to the described configuration, the number of bits per pixel can be reduced by the encoding unit that encodes the input image signal, and the required memory capacity can be reduced.

According to the third aspect of the present invention, the capacity of the field memory is provided by the encoding means for encoding the input image signal and the inter-frame interpolation means using the output signal of the encoding means. Also, the circuit scale of the interpolation processing circuit can be reduced.

According to the fourth aspect of the present invention, the output signals of the inter-frame interpolation means and the delay means for delaying the output signal of the inter-frame interpolation means for one field period are timed by the multiplexing means. By dividing and multiplexing, the circuit scale of the static region processing circuit can be reduced.

According to the fifth aspect of the present invention, the output signals of the interframe interpolating means, the delay means, and the field interpolating means for interpolating the input image signal in the field are multiplexed. By time-division multiplexing, the circuit scale of the static area processing circuit and the moving area processing circuit can be reduced.

According to the seventh aspect of the present invention, the multiplexing means for time-division multiplexing the R signal, the G signal, and the B signal, and the nonlinear conversion means for nonlinearly converting the output signal from the multiplexing means, The circuit scale of the gamma correction circuit can be reduced by the separation means for separating the R signal, the G signal, and the B signal from the output signal of the non-linear conversion means.

According to the ninth aspect of the present invention, the analog demodulation means for demodulating the transmission signal by the analog modulation method, the digital demodulation means for demodulating the transmission signal by the digital modulation method, the analog demodulation means, Selecting means for selecting an output signal from the digital demodulating means,
By the decoding means for demodulating the selected output signal into a high-definition television signal, it is possible to receive high-definition television broadcasting of either analog modulation method or digital modulation method.

According to the structure of claim 10 of the present invention, the analog demodulation means, the digital demodulation means, the selection means, the decoding means, and the first state for detecting the synchronization state of the output signals of the analog demodulation means are detected. Of the high-definition television broadcast of either the analog modulation system or the digital modulation system by the second synchronization detection means for detecting the synchronization state of the output signal of the digital demodulation means automatically. The effect that it is possible to switch to the optimum reception form is obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a field memory unit in a first embodiment of the present invention.

FIG. 2 is a block diagram showing an encoder in the first embodiment.

FIG. 3 is a block diagram showing a decoder in the first embodiment.

FIG. 4 is a configuration diagram showing an interframe interpolation circuit using the field memory unit of the first embodiment.

FIG. 5 is a configuration diagram showing an interframe interpolation circuit in a second embodiment of the present invention.

FIG. 6 is a configuration diagram showing a MUSE decoding processing circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram showing signals for explaining the operation of the MUSE decoding processing circuit in the third embodiment.

FIG. 8 is a configuration diagram showing a low-pass filter according to a third embodiment.

FIG. 9 is a configuration diagram showing a MUSE decoding processing circuit according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a low-pass filter according to a fourth embodiment.

FIG. 11 is a configuration diagram showing a gamma correction circuit according to a fifth embodiment of the present invention.

FIG. 12 is a diagram showing signals for explaining the operation of the gamma correction circuit in the fifth embodiment.

FIG. 13 is a configuration diagram showing a high-definition television receiver according to a sixth embodiment of the present invention.

FIG. 14 is a configuration diagram showing a high-definition television receiver according to a seventh embodiment of the present invention.

FIG. 15 is a configuration diagram showing a synchronization detection circuit according to a seventh embodiment.

FIG. 16 is a configuration diagram showing a determination circuit according to a seventh embodiment.

FIG. 17 is a configuration diagram showing a high-definition television receiver in a conventional example.

FIG. 18 is a configuration diagram showing a MUSE decoding processing circuit in a conventional example.

[Explanation of symbols]

1 ... FM demodulator, 2 ... MUSE decoder, 3 ... Display, 11, 111, 112 ... Inter-frame interpolation circuit, 12
… Switch, 13, 14, 402, 402a, 402b… Field memory, 15… Still area processing circuit, 16, 17, 39, 40…
Low-pass filter, 18, 19, 33, 422, 427 ... Sampling frequency conversion circuit, 20 ... Inter-field interpolation circuit,
21 ... TCI decoding circuit, 30 ... Moving area processing circuit, 31
… Subsample circuit, 32… Field interpolation circuit, 35
... Motion detection circuit, 36 ... Mixing circuit, 41 ... Inverse matrix circuit, 42, 43, 44 ... Gamma correction circuit, 61 ... 1 pixel delay device, 62, 63, 64, 65, 66, 70, 71, 72, 73 , 74 ... Coefficient multiplier, 67, 415 ... Adder, 75 ... Coefficient generator, 151
... static region processing circuit, 201 ... A / D converter, 202 ... waveform equalizer, 203 ... non-linear de-emphasis circuit, 2
04,205,206 ... D / A converter, 210 ... MUSE decoding processing circuit, 401, 401a, 401b ... Encoder, 403, 403
a, 403b ... Decoder, 411 ... Subtractor, 412 ... Quantizer,
413 ... Local decoder, 414 ... Predictor, 416 ... Inverse quantizer, 420, 425, 430 ... Multiplexer, 421, 426 ...
Low pass filter, 423, 428, 432 ... Demultiplexer, 431 ... Non-linear conversion circuit, 510 ... Digital demodulator,
520 ... Digital decoder, 530 ... Selection switch, 60
0 ... First sync detection circuit, 601 ... Clock recovery circuit, 60
2 ... Sync determination circuit, 610 ... Second sync detection circuit, 620 ...
Judgment circuit.

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Claims (10)

[Claims] 1. A high-definition television receiver, comprising: a decoder for demodulating a transmitted image signal to obtain a high-definition television signal, having encoding means for encoding the image signal. 2. The high-definition television receiver according to claim 1, wherein the encoding means uses a predictive encoding means. 3. A decoder for demodulating a transmitted image signal to obtain a high-definition television signal, coding means for coding the image signal, and interpolating an output signal coded by the coding means between frames. A high-definition television receiver characterized by having an inter-frame interpolating means. 4. In a decoder for demodulating a transmitted image signal to obtain a high quality television signal, an interframe interpolating means for interpolating the image signal between frames, and an output signal of the interframe interpolating means for one field. A high-definition television receiver, comprising: delay means for delaying for a period; and multiplexing means for time-division multiplexing the output signal of the interframe interpolation means and the output signal of the delay means. 5. In a decoder for demodulating a transmitted image signal to obtain a high quality television signal, inter-frame interpolation means for interpolating the image signal between frames, and an output signal of the inter-frame interpolation means for one field. Delay means for delaying by a period, field interpolation means for field interpolation of the image signal, output signal of the interframe interpolation means, output signal of the delay means and output signal of the field interpolation means A high-definition television receiver having a multiplexing means for time-division multiplexing. 6. The inter-frame interpolation means includes an encoding means for encoding an input image signal, an inter-frame interpolation means for inter-frame interpolating an encoded signal output from the encoding means, and the frame. The high-definition television receiver according to claim 4 or 5, further comprising: a decoding unit that decodes the coded signal interpolated between the frames output from the interpolating unit. 7. A demodulated R signal and G in a decoder for demodulating a transmitted image signal to obtain a high definition television signal.
Multiplexing means for time-division multiplexing the signal and the B signal, and non-linear conversion means for performing non-linear conversion of the output signal from the multiplexing means,
A high-definition television receiver, comprising: separating means for separating an R signal, a G signal, and a B signal from the output signal of the non-linear converting means. 8. The high quality television receiver according to claim 7, wherein the non-linear conversion means corrects the gamma characteristic of the display. 9. A high-definition television broadcast in which a band-compressed signal obtained by band-compressing a high-definition television signal using a multiple subsampling method is transmitted using an analog modulation method, and the band-compressed signal is transmitted using a digital modulation method. A high-definition television receiver for receiving high-definition television broadcasting,
An analog demodulation means for demodulating a band-compressed signal transmitted using the analog modulation method into an original band-compressed signal, and a digital device for demodulating a band-compressed signal transmitted using the digital modulation method into an original band-compressed signal Demodulation means,
Selection means for selectively outputting the output signal from the analog demodulation means and the output signal from the digital demodulation means, and decoding means for demodulating the band-compressed signal selected by the selection means into the original high-definition television signal. And a high-definition television receiver which controls the selecting means according to a reception channel selection signal. 10. A high-definition television broadcast in which a band-compressed signal obtained by band-compressing a high-definition television signal using a multiple sub-sampling method is transmitted using an analog modulation method, and the band-compressed signal is transmitted using a digital modulation method. A high-definition television receiver for receiving high-definition television broadcasts, wherein analog demodulation means for demodulating a band-compressed signal transmitted using the analog modulation method into an original band-compressed signal, and the digital modulation method are provided. A digital demodulation means for demodulating the band-compressed signal transmitted using the original band-compressed signal; a selection means for selectively outputting the output signal from the analog demodulation means and the output signal from the digital demodulation means; Decoding means for demodulating the band-compressed signal selected by the selecting means to the original high-definition television signal, and output from the analog demodulating means First to detect signal synchronization
Synchronization detecting means and second synchronization detecting means for detecting the synchronization state of the output signal from the digital demodulating means, and the selecting means is selected according to the detection results from the first and second synchronization detecting means. A high-definition television receiver characterized by being controlled.