JPH0836373A - Display controller - Google Patents

Abstract

PURPOSE:To make it possible to assign intensity levels without generating flickering in the state of reducing a production cost by assigning the intensity levels by putting signal driving ICs plural times into an output state in one scanning time on a scanning side. CONSTITUTION:The gradation signals b1 to b4 of 4 bits of respective pixels are converted to display data indicating on/off of one scanning time by a data decoder 5. The display data are stored in a memory 6. A display controller 8 for controlling display of a panel 1 is connected to signal side driving ICs 2a to 2c and scanning side driving ICs 3a, 3b of the display panel 1 and further, this controller 8 is connected to an address counter 7 as well. Then, the display data read 7 times 1 bit each in the one scanning time in accordance with the operation of a latch counter and decoder of the controller 8. Modulation within the scanning time is thus executed. The on/off signals of the prescribed pixels are obtd. in correspondence to the respective gradation signals in the one scanning time. The assigning of the intensity levels of 8 gradations is thus executed with high quality without generating the flickering.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a display controller.

[0002]

2. Description of the Related Art Display panels for displays are required to perform gradation display of images. To meet this demand, for example, taking a liquid crystal panel as an example, three types of gradation display of frame modulation, pulse width modulation, and voltage modulation are performed.

[0003]

The above-mentioned pulse width modulation,
The gradation display by voltage modulation has excellent display quality,
Each requires a dedicated drive IC, which is problematic in terms of manufacturing cost. On the other hand, in gradation display by frame modulation, a drive IC for binary display can be used and there is no problem in manufacturing cost, but flicker occurs in the display and a problem in display quality occurs. For this reason, at present, gradation display by frame modulation is adopted in low-priced products, and pulse width modulation,
Gradation display by voltage modulation is incorporated in high-priced products.

The present invention has been made in view of the current state of gradation display as described above, and an object thereof is a display controller capable of high-quality gradation display and manufactured at a low manufacturing cost. To provide.

[0005]

In order to achieve the above object, the invention according to claim 1 is a display controller using a driving IC for binary display as a signal driving IC, and one scanning on the scanning side. It is characterized in that it has a control means for displaying a gradation by making the signal drive IC output a plurality of times with respect to time.

[0006] Similarly, in order to achieve the above-mentioned object, the invention according to claim 2 is the invention according to claim 1, wherein the control means outputs the signal based on a gradation signal of each pixel displayed on a display. It is characterized in that the side IC is brought into an output state for a preset time to perform gradation display.

[0007] Similarly, in order to achieve the above-mentioned object, in the invention according to claim 3, in the invention according to claim 2, the control means sets the bit number n of the gradation signal of each pixel to n.
It is characterized in that the signal side IC is put into an output state at a maximum of 2 ⁿ -1 times.

Similarly, in order to achieve the above-mentioned object, the invention according to claim 4 is the invention according to claim 2, wherein the preset time tm is the number of bits of the gradation signal of each pixel.
Is n and a natural number smaller than n is m, tm = 2 ^(m-1)
It is characterized by being × T / (2 ⁿ −1).

[0009] Similarly, in order to achieve the above object, the invention according to claim 5 is the invention according to claim 2, wherein the time of the output state of the signal drive IC is the bit bm ( m = 1, 2 ...), where T is one scanning time, and n is the number of bits of the gradation signal input to each pixel,
Is {T / (2 ⁿ −1)} Σ (2 ^(m −1 ⁾ × b ^m ), where the output state is 1 when ON and 0 when OFF.

Similarly, to achieve the above object, in the invention according to claim 6, in the invention according to claim 5, the time of the output state of the signal side drive IC is set based on the data stored in the memory. It is characterized by that.

Similarly, in order to achieve the above object, the invention according to claim 7 is the invention according to claim 6, characterized in that the data stored in the memory is rewritable.

Similarly, in order to achieve the above object, the invention according to claim 8 is different from the invention according to any one of claims 3 to 7 in that the gradation display data of each pixel is set to one scanning line. It further comprises storage means for storing more than one minute, and display means for reading out and displaying the gradation display data, one bit for each pixel, from the storage means.

Similarly, in order to achieve the above-mentioned object, the invention according to claim 9 is the same as the invention according to claim 8, in which a hard carbon film is used as an insulating layer as a display, and a matrix array composed of MIM elements is used as an electrode. The liquid crystal panel used for the substrate is used.

[0014]

According to the invention of claim 1, in the display controller using the drive IC for binary display as the signal drive IC, the signal drive IC is output a plurality of times for one scanning time on the scanning side, Gradation display is performed.

According to a second aspect of the present invention, in the first aspect of the present invention, the signal side IC is set to an output state for a preset time based on the gradation signal of each pixel displayed on the display. Gradation display is performed.

According to a third aspect of the invention, in the second aspect of the invention, for the number of bits n of the gradation signal of each pixel,
Grayscale display is performed by setting the signal side IC to the output state at a maximum of 2 ⁿ -1 times.

According to a fourth aspect of the invention, in the second aspect of the invention, the preset time tm is such that the scanning time is T, the number of bits of the gradation signal of each pixel is n, and a natural number smaller than n is m. , ^Tm = 2 ^(m-1) * T / ( ^2n- 1).

According to a fifth aspect of the invention, in the second aspect of the invention, the time of the output state of the signal driving IC is 1 for each bit bm (m = 1, 2, ...) Of the gradation signal of the pixel.
Assuming that the scanning time is T, n is the number of bits of the gradation signal input to each pixel, and bm is 1 when the output state is ON and 0 when the output state is OFF, {T / (2 ⁿ -1)} Σ ( 2 ^(m-1) ×
bm).

According to a sixth aspect of the invention, in the fifth aspect of the invention, the time of the output state of the signal side drive IC is set based on the data stored in the memory.

According to the invention of claim 7, in the invention of claim 6, the data stored in the memory is rewritten as necessary.

According to an eighth aspect of the invention and a ninth aspect of the invention, in the invention according to any one of the third to seventh aspects, the gradation display data is stored by the storage means for one scanning line or more. Then, the display means reads out and displays the gradation display data, one bit for each pixel, from the storage means.

[0022]

【Example】

[First Embodiment] A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an explanatory diagram showing a configuration of a panel portion of a display according to a first embodiment of the present invention, FIG. 2 is a block diagram showing an overall configuration of the present embodiment, and FIG. 3 is a block showing a configuration of the display controller of FIG. FIG. 4 is an explanatory view showing the structure of the MIM (metal insulator metal) element of this embodiment, FIG. 5 is a time chart showing the gradation display operation of this embodiment, and FIG. 6 is a gradation signal of this embodiment. It is explanatory drawing which shows the relationship with a decoder output.

In the present embodiment, as shown in FIG. 1, in the display panel 1 of the flat panel display, the signal side is a binary value that outputs an ON / OFF signal to the display panel 1 based on the input data. Driving IC 2a ~
On the scanning side, scanning side driving ICs 3a and 3b for sequentially selecting one line by the input of a clock signal are mounted on the scanning side. The scan side drive ICs 3a and 3b sequentially scan line by line, and the ON / OFF signal corresponding to each pixel on the electrode being scanned is a binary drive IC 2a.
2 to 2c, an image is formed on the display panel 1. In the present embodiment, when displaying with n gradations, the signal side outputs n-1 times within one scanning time so that the ON output is performed within one scanning time.
Modulation is performed according to the number of signals to display n gradations.

The case where 8-gradation display is performed in this embodiment will be described. It is possible to express 8-gradation with 3 bits. In this embodiment, however, the peripheral circuit can easily manipulate data.
One bit is added to the invalid bit, 4 bits are assigned to each pixel, and the signal side drive ICs 2a to 2c output ON / OFF signals seven times in one operation time. For this reason, the input grayscale signals per pixel are b1, b2,
In the case of displaying with 4 bits of b2 and b4, if b1 is an invalid bit and the number of outputs within one operation time is represented by N, this embodiment performs the conversion represented by the equation (1) pixel by pixel and performs one scan. It has a function of outputting an ON / OFF signal N times in time. N = b2 × 4 + b3 × 2 + b4 × 1 (1)

As shown in FIG. 2, the present embodiment is provided with a data decoder 5 for inputting gradation signals b1 to b4 and creating display data, and the display data is stored in the data decoder 5. The memory 6 is connected, and the memory 6 is
It is connected to the signal side drive ICs 2a to 2c of the display panel 1. An address counter 7 to which a clock and an enable signal are input is connected to the memory 6. A display controller 8 for controlling the display of the display panel 1 is connected to the signal side driving ICs 2a to 2c and the scanning side driving ICs 3a and 3b of the display panel 1, and the display controller 8 is also connected to the address counter 7. There is.

As shown in FIG. 3, the display controller 8 is provided with a reference oscillator 10 for generating a clock. The reference oscillator 10 is connected to a signal side segment counter 11, and the segment counter 11 is provided with a decoder 12. Are connected. A latch counter 13 is connected to the decoder 12, a decoder 14 is connected to the latch counter 13, a common counter 15 on the scanning side is connected to the decoder 14, and a decoder 16 is connected to the common counter 15. There is.

In this embodiment, the entire circuit having the configuration shown in FIG. 2 including the display controller shown in FIG. 3 is constructed by using an FPGA (field programmable gate array). Further, as the display panel 1, an active matrix type liquid crystal panel formed by an MIM element using a hard carbon film as an insulating material is used. A method of manufacturing this active matrix type liquid crystal panel will be briefly described. Pyrex is used as the substrate 31,
8 is formed on the substrate 31 by the magnetron sputtering method.
An ITO film (indium oxide film) is formed with a thickness of 00Å and patterned to form the pixel electrode 32. Next, an MIM element using a hard carbon film is provided as an active element as follows. First, the lower electrode 33 is formed by depositing Al on the pixel electrode 32 of the substrate 31 by vapor deposition to a thickness of 1000 Å and patterning it. A hard carbon film 34 as an insulating film is deposited on the lower electrode 33 to a thickness of 1100Å by a plasma CVD method, and then patterned by dry etching. Further, Ni is deposited on each hard carbon film by the vapor deposition method to a thickness of 1000 Å, and then patterned to form the upper electrode 35.

Next, as the other transparent substrate (opposite substrate), ITO is formed on the Pyrex to a thickness of 1000 Å by the sputtering method and patterned into stripes to form a common pixel electrode. Then, a polyimide film is formed as an alignment film on both substrates, a lapping process is performed, these substrates are made to face each other with each pixel electrode side facing inside, and they are bonded together with a gap agent between them to form a cell inside the formed cell. A liquid crystal panel is formed by enclosing a liquid crystal material.
Signal side drive ICs 2a to 2c and scanning side drive ICs 3a3b
Is mounted on the display panel 1 by a thermocompression bonding method using a thermosetting anisotropic conductive film.

In the present embodiment, the 4-bit gradation signal of each pixel is turned on / off for one scanning time by the data decoder 5 of FIG.
The relationship between the gradation data and the display data which are converted into the display data indicating OFF and are input is as shown in FIG.
The display data from the data decoder 5 is stored in the memory 6, and this display data is read one bit at a time seven times based on the operation of the latch counter 13 and the decoder 14 in FIG. Internal modulation is performed. In this case, if a memory that stores gradation display data for one scan or more is used, high-speed drawing can be performed. As a memory used at this time, a rewritable memory such as a FIFO, a multi-port VRAM, an SRAM or a DRAM is optimal. In particular, the FIFO is convenient because peripheral circuits can be easily constructed when processing data for one scan.

As described above, according to this embodiment, the ON / OFF signal of the pixel as shown in FIG. 5 is obtained corresponding to each gradation signal in one scanning time, and 8 gradations without flicker occur. It becomes possible to perform high-quality gradation display. In addition, in the present embodiment, M having a hard carbon film as an insulating layer is used.
By using the IM active matrix liquid crystal display panel, it is possible to reduce the manufacturing cost and perform high quality gradation display.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIG. FIG. 7 is an explanatory diagram showing the relationship between the gradation signal and the decoder output of this embodiment.

In the present embodiment, the output on the signal side is divided by the decoder 12 connected to the segment counter 11 shown in FIG. 3 into three blocks which respectively output once, twice and four times. It is configured. The configuration of the other parts of this embodiment is the same as that of the first embodiment already described.

In this embodiment, the ON / OF of the pixel as shown in FIG. 7 is corresponded to each gradation signal in one scanning time.
An F signal can be obtained, and high-quality display of 8 gradations without flicker can be performed. Other operations and effects of this embodiment are the same as those of the first embodiment already described.

[Third Embodiment] A third embodiment of the present invention will be described with reference to FIG. FIG. 8 is an explanatory diagram showing the configuration of the display controller of the embodiment.

The display controller 8A of this embodiment is shown in FIG.
3, the register counter 41 is connected to the decoder 14 with respect to the display controller 8 of the first embodiment already described with reference to FIG.
A register 42 which is an EPROM is connected to the. The register 42 stores data on the output states of the signal side driving ICs 2a to 2c, and the stored data can be rewritten by ultraviolet rays or electric signals. The configuration of the other parts of this embodiment is the same as that of the second embodiment already described.

In this embodiment, the signal side driving ICs 2a to 2c
The output state, that is, the output interval, is set based on the data stored in the register 42, and the ON / OFF signal of the display panel 1 is output at a desired output interval in one scanning time to obtain the optimum display gradation. Is set. In addition, the register 42
If the optimum data does not exist in the stored data of, the data is rewritten and the optimum data is stored in the register 42. In order to adjust the latch signal interval by the display controller 8A, a method of counting clock signals with the register counter 41 and inputting a value for resetting the register counter 41 to the register 42 is used.

According to this embodiment, in addition to the effect of the second embodiment, the gradation display of the display panel 1 is selected according to the output state data of the signal side drive ICs 2a to 2c selected from the data stored in the register 42. However, it is possible to display a desired gradation. Further, it is possible to correct the relationship between the gradation signal and the display characteristic and set the optimum characteristic while actually displaying. In the above description, the case where the register 42 is provided in the controller to reduce the component cost has been described, but a register separate from the controller may be used.

It should be noted that the present invention is not limited to the description in each of the embodiments, and in general, by setting the signal side IC to the output state at a maximum of 2n -1 times for the bit number n of the gradation signal of each pixel. Gradation display can be performed. Similarly, in the present invention, the time tm during which the signal side IC is in the output state is tm = 2 ^(m-1) x T /, where n is the number of bits of the gradation signal of each pixel and m is a natural number smaller than n. It can be set to (2 ⁿ -1). Further, the time of the output state of the signal driving IC is as follows: 1 bit of scanning time of each bit bm (m = 1, 2 ...) Of the gradation signal of the pixel is T, and n is the gradation signal input to each pixel. Assuming that the output state is 1 when the output state is ON and 0 when the output state is OFF, {T / (2 ⁿ -1)} Σ (2 ^(m-1) × bm
) Can be set.

[0039]

According to the invention described in claim 1 to claim 5, the signal driving IC is a driving IC for binary display.
In the display controller using, the gradation display is performed with the signal drive IC being output multiple times for one scanning time on the scanning side. Therefore, in the state where the manufacturing cost is reduced, the gradation without flicker is generated. It becomes possible to display. According to the invention of claim 6, claim 1
In addition to the effects of the invention described in claim 5 and the invention of claim 5, since the time of the output state of the signal side drive IC is set based on the data stored in the memory, the characteristics of gradation display are selected and desired. It becomes possible to perform gradation display with the characteristics of. According to the invention described in claim 7, in addition to the effect of the invention described in claim 6, since the data stored in the memory is rewritten as necessary, a desired gradation display characteristic is written and the gradation is changed. It is possible to perform gradation display with display characteristics. According to the invention described in claim 8 and the invention described in claim 9, the gradation display data is stored by one or more scanning lines by the storage means, and the gradation display data is stored by the display means by one bit for each pixel. Since the data is read from the storage means and displayed, in addition to the effect of the invention described in any one of claims 3 to 7, it becomes possible to perform higher-speed gradation display.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a panel unit of a display according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of the same embodiment.

FIG. 3 is a block diagram showing a configuration of the display controller of FIG.

FIG. 4 is an explanatory diagram showing a structure of an MIM element of the same example.

FIG. 5 is a time chart showing a gradation display operation of the same example.

FIG. 6 is an explanatory diagram showing a relationship between a gradation signal and a decoder output according to the embodiment.

FIG. 7 is an explanatory diagram showing a relationship between a gradation signal and a decoder output according to the second embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a configuration of a display controller according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 display panel 2a-2c signal side drive IC 3a, 3b scanning side drive IC 5 data decoder 6 memory 7 address counter 8 display controller

Claims (9)

[Claims] 1. A display controller using a drive IC for binary display as a signal drive IC, comprising a scanning-side controller.
A display controller, characterized in that it has a control means for displaying the gradation by making the signal driving IC output a plurality of times for a scanning time. 2. The gray scale display is performed by the control means by causing the signal side IC to be in an output state for a preset time based on a gray scale signal of each pixel displayed on the display. The display controller according to claim 1. 3. The display according to claim 2, wherein the control means sets the signal side IC to an output state at a maximum of 2 ⁿ −1 times for the number of bits n of the gradation signal of each pixel. Controller. 4. The preset time tm is tm = 2 ^(m-1) * T / ( ^{2n -1)} where n is the number of bits of the gradation signal of each pixel and m is a natural number smaller than n. The display controller according to claim 2, wherein: 5. The time of the output state of the signal drive IC is
For each bit bm (m = 1, 2, ...) Of the gradation signal of the pixel, the one scanning time is T, n is the number of bits of the gradation signal input to each pixel, and bm is the output state of ON. 1, O
Assuming that FF becomes 0, {T / (2 ⁿ -1)} Σ
3. The display controller according to claim 2, wherein (2 ^(m-1) * bm). 6. The display controller according to claim 5, wherein the time of the output state of the signal side drive IC is set based on the data stored in the memory. 7. The display controller according to claim 6, wherein the data stored in the memory is rewritable. 8. A storage means for storing the gradation display data of each pixel for one scanning line or more, and a display means for reading and displaying the gradation display data for each pixel, one bit at a time, from the storage means. The display controller according to any one of claims 3 to 7, further comprising: 9. The display controller according to claim 8, wherein the display is a liquid crystal panel using a hard carbon film as an insulating layer and using a matrix array composed of MIM elements as an electrode substrate.