JPH0845271A - Storage device - Google Patents

Abstract

PURPOSE:To perform sure refresh operation without increasing a circuit scale. CONSTITUTION:A timer 6 generates a clock TC. An address counter 3 generates each address signal A0-A9 to which an input signal A (clock TC) is divided in frequency. A row address (refresh address ADD) for selecting a word line WL is specified by each address signal A0-A9 of ten figures. When a row address previously set (row address of a memory cell in which data holding possible time is insufficient) coincides with a refresh address ADD generated by the address counter 3, an address coincidence detecting circuit 4 outputs 'L' to an output terminal OUT, when does not coincide, the circuit 4 outputs 'H' to the output terminal OUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a semiconductor memory device requiring a refresh operation.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memo)
ry) and pseudo SRAM (Static RandomAccess Memory)
In semiconductor memory devices such as the above, data is stored depending on the presence or absence of signal charges accumulated in the memory cells. Since the signal charge leaks and disappears after a certain time, it is necessary to re-store the signal charge in the memory cell before it disappears. This operation is called a refresh operation and is performed regularly. Specifically, the word line is selected, the memory cell connected to the word line is activated, and the data stored in the memory cell is read to the bit line. Next, the data read to the bit line is amplified by the sense amplifier, and the amplified data is returned to the original memory cell again, so that the data is rewritten (refreshed) in one memory cell. When such a circuit operation is performed for all the word lines while sequentially changing the row address, data refresh is performed for all the memory cells in the semiconductor memory device.

Here, in order to specify a row address (refresh address) for selecting a word line, a method of inputting a refresh address from the outside (ROR; RA).
S Only Refresh) and a method of counting the refresh address by providing an address counter inside the semiconductor memory device. In the latter method, the address counter is controlled by an external signal (CBR; CAS Before RA).
S) and a method in which a timer is provided inside the semiconductor memory device to periodically operate the address counter (self-refresh method).

[0004]

The refresh interval of the self-refresh method is defined to be longer than the refresh interval of ROR and CBR. As the refresh interval becomes longer, the time required for the memory cell to hold the signal charge (data holding time) also becomes longer.

By the way, there is a certain amount of variation in the time during which signal charges can be held in an actual memory cell (data holdable time) for each memory cell in the semiconductor memory device. Such variations in the data holdable time occur in the manufacturing process and are difficult to avoid. Therefore, for some memory cells in the semiconductor memory device, the data holdable time may be short of the data hold required time. If there is any memory cell having such a shortage of data retention time, the semiconductor memory device must be discarded as a defective product. That is, the yield of the semiconductor memory device decreases due to the shortage of the data holdable time.

Therefore, in the self-refresh method, there has been proposed a method (hereinafter referred to as a redundant memory alternative method) for relieving a memory cell having a short data retention time by replacing it with a redundant memory cell. However, in the redundant memory alternative method, the number of memory cells having insufficient data retention time must not exceed the number of redundant memory cells.

Further, Japanese Patent Laid-Open No. 4-232688 (IP
C; G11C 11/401), a method of using SRAM memory cells as redundant memory cells has also been proposed in the redundant memory alternative method. In the SRAM memory cell, since the signal charge is statically held, the data stored in the memory cell is not lost unless the power is turned off. Therefore, by using the SRAM memory cell as the redundant memory cell, it is possible to reliably rescue the memory cell whose data retention time is insufficient.

However, in the redundant memory alternative system, since a redundant memory cell has to be added to the semiconductor memory device, the semiconductor memory device becomes large in size by the redundant memory cell, and the semiconductor chip on which the semiconductor memory device is formed. Area increases.

Further, the memory cell of the DRAM is one MO
Although it is composed of an S transistor and one MOS capacitor, an SRAM memory cell is composed of four MOS transistors. Therefore, the SRAM memory cell is D
It is larger than the memory cell of RAM. Therefore, in the method of using the SRAM memory cell as the redundant memory cell in the redundant memory alternative method, the size of the semiconductor memory device is further increased and the area of the semiconductor chip is significantly increased.

The present invention has been made to solve the above problems, and an object of the present invention is to remedy a memory cell whose data retention time is insufficient without increasing the size of the storage device. To provide a possible storage device.

[0011]

SUMMARY OF THE INVENTION The gist of the present invention is to carry out a refresh operation so that data stored in a memory cell is not lost.

According to a second aspect of the present invention, in a storage device that performs a refresh operation so that the data stored in a memory cell is not lost, the refresh operation of a specific address is performed more times than the refresh operation of another address. What to do is the gist.

According to a third aspect of the present invention, in a memory device that performs a refresh operation so that data stored in a memory cell is not lost, a memory having a short data retention time for one cycle of the refresh operation. The gist of the invention is to perform the cell refresh operation more times than the memory cell refresh operation in which the data retention time is not insufficient.

According to a fourth aspect of the present invention, in a memory device that performs a refresh operation so that data stored in a memory cell is not lost, a memory having a short data retention time for one cycle of the refresh operation. The gist of the present invention is to perform the refresh operation of the memory cell having the insufficient data retention time again before and after the refresh operation is performed a predetermined number of times after the cell refresh operation is completed.

According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the storage device is D
Its gist is that it is a RAM or a pseudo SRAM.

[0016]

According to the first aspect of the invention, the data stored in the memory cell can be prevented from being lost by performing the refresh operation.

According to the second aspect of the present invention, the refresh operation of the specific address is performed more times than the refresh operation of the other address, so that the data holdable time of the memory cell of the specific address is insufficient. Even if there is, it can be relieved. Further, since the redundant memory cell is not used to relieve the memory cell whose data retention time is insufficient, the memory device does not become large.

According to the third aspect of the invention, in one cycle of the refresh operation, the refresh operation of the memory cell in which the data holdable time is insufficient can be performed many times to relieve the memory cell. it can. Further, since the redundant memory cell is not used to relieve the memory cell whose data retention time is insufficient, the memory device does not become large. Here, if the number of memory cells whose data retention time is insufficient is sufficiently smaller than the number of all memory cells in the memory device, it is assumed that the refresh operation is performed several times or more for the memory cells. Also 1
The time required for the periodic refresh operation (refresh interval) does not increase significantly.

According to the fourth aspect of the invention, the refresh operation is performed again before the data stored in the memory cell whose data retention time is insufficient is lost, so that the memory cell is saved. can do.
Other functions are similar to those of the invention described in claim 3.

In the DRAM or the pseudo SRAM, the data is stored by dynamically accumulating the signal charges in the memory cells, so that the signal charges leak and disappear after a certain period of time. Therefore, the refresh operation is indispensable. According to the invention described in claim 5, even if there is a memory cell whose data retention time is insufficient, it is possible to repair the memory cell. Therefore, the yield of the DRAM or the pseudo SRAM can be improved.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in a self-refresh type D
An embodiment embodied in a RAM will be described with reference to the drawings.

FIG. 1 shows a circuit of a main part of this embodiment. The row address self-refresh circuit 1 includes a D flip-flop 2, an address counter 3, an address match detection circuit 4, a row address decoder 5, a timer 6, a latch 7, and N.
It is composed of MOS transistors 8 to 11 and inverters 12 to 14.

The D flip-flop 2 stores the data input to the input terminal D at the rising of the input terminal CK, and outputs the stored data from the rising of the input terminal CK to the next rising. Continue to output from. The output terminal Q of the D flip-flop 2 is connected to the gate of the transistor 11.

The timer 6 generates a clock TC having an appropriate cycle. The clock TC is output to the input terminal CK of the D flip-flop 2 and the address match detection circuit 4, and also to the address counter 3 via the transistors 10 and 11.

The address counter 3 is composed of ten D flip-flops 41 connected as shown in FIG. The D flip-flop 41 stores the data input to the input terminal D at the rising of the input terminal CK, and outputs the stored data from the output terminal Q from the rising of the input terminal CK to the next rising. to continue. Further, an inverted signal of the output terminal Q is output from the output terminal bar Q. Then, as shown in FIG. 3, the address counter 3 divides the input signal A (clock TC) to generate address signals A0 to A9. A row address (hereinafter referred to as a refresh address) for selecting the word line WL by the 10-digit address signals A0 to A9.
(ADD) is specified.

The address match detection circuit 4 includes a row address and an address counter 3 which are preset in the address match detection circuit 4.
Detects whether the refresh address ADD generated by has matched. Then, the address match detection circuit 4
Outputs "L" to the output terminal OUT when the preset row address and the refresh address ADD generated by the address counter 3 match, and outputs "H" to the output terminal OUT when they do not match. Output. The output terminal OUT of the address match detection circuit 4 is connected to each inverter 1
The gates of the transistors 9 and 10 are connected via 2 and 13. The output terminal OUT of the address match detection circuit 4 is connected to the gate of the transistor 8 and the input terminal D of the D flip-flop 2 via the inverter 12.

As shown in FIG. 4, the address coincidence detection circuit 4 is constructed by using a fuse element F. That is, the common node α connected to the output terminal OUT is connected to the precharge circuit 42. Precharge circuit 42
Is composed of PMOS transistors 43 and 44,
The common node α is pulled up and precharged according to the clock TC. The common node α is connected to each NMOS transistor 45 via each fuse element F. The node on the side opposite to the side connected to each fuse element F of each NMOS transistor 45 is grounded. Further, the address signals A0 to A9 are input to the gates of the NMOS transistors 45, respectively. If there is a memory cell whose data retention time is insufficient, the MS of the row address of that memory cell
The fuse element F corresponding to the address obtained by inverting B (Most Significant Bit) is cut.

Here, the row address of the memory cell whose data retention time is insufficient is set to "0110100101", and in FIG. 4, the address "1110100101" is obtained by inverting the address signal A9 which is the MSB of the row address. The corresponding fuse element F is shown blown. for that reason,
The address match detection circuit 4 uses the address "1110100101" and the refresh address AD generated by the address counter 3.
When D and D match, "L" is output to the output terminal OUT, and when they do not match, "H" is output to the output terminal OUT.

The row address decoder 5 activates the word line WL corresponding to the refresh address ADD generated by the address counter 3. However, the address signal A9 which is the MSB of the refresh address ADD generated by the address counter 3 is transferred to the row address decoder 5 via the transistor 9 or the inverter 14 and the transistor 8.

The latch 7 is provided with the address counter 3 when the signals applied to the gates of the transistors 10 and 11 (hereinafter referred to as signals B and C) become "L" and the transistors 10 and 11 are turned off. Is provided in order to prevent the level of the input signal A from becoming uncertain due to the floating input of the.

Next, the operation of this embodiment configured as described above will be described with reference to the time chart shown in FIG. The refresh address ADD is a 10-digit address signal A0-
It is defined by A9, and 2 ¹⁰ = 1024 word lines WL are provided. Then, as shown in FIG.
Is output for 1024 cycles, the address counter 3 makes one round. Therefore, when the refresh operation for each word line WL is performed 1024 times, which is the number of word lines WL, the data is refreshed for all the memory cells in the DRAM. Where clock T
If the cycle of C is 100 μsec, it takes 1024 × 100 μsec for the address counter 3 to make one round. In other words, the refresh interval is 1024 × 100 μsec =
It will be about 100 msec. Therefore, the data retention time required for each memory cell in the DRAM is about 100 msec, and the data retention time is required to be 100 msec or more.

Here, when the data holdable time of the memory cell with the row address "0110100101" is 50 msec or more, 100 msec.
Less than In this case, for the memory cell whose row address is "0110100101", extra refresh operation is performed in the middle of the refresh interval to prevent the stored data from being lost and can be relieved. That is, before and after the 512th refresh operation after the refresh operation for the word line WL having the row address "0110100101" is completed, the row address is again "0110100".
By performing the refresh operation on the 101 "word line WL, the memory cell having the row address" 0110100101 "can be relieved.

The address match detection circuit 4 uses the row address "1110100101" and the address counter 3 which are set in advance.
Detects whether the refresh address ADD generated by has matched. Here, the address match detection circuit 4
The row address "1110100101" that is set to is the same as the row address "0110100101" of the memory cell for which the data retention time is insufficient and the address "100000000" for 512 counts.
0 "is added.

When the row address "1110100101" and the refresh address ADD match, the next refresh operation is performed on the word line WL of the row address "0110100101" instead of the word line WL of the row address "1110100110". . Specifically, as shown in FIG. 5, by controlling the signals B and C, the row address "1"
For the next refresh operation in which 110100101 "matches the refresh address ADD, the address counter 3 is not operated, and the row address decoder 5 is controlled via the inverter 14 and the transistor 8.
The refresh operation is performed on the memory cell whose row address is "0110100101".

Subsequently, the next refresh operation is performed on the word line WL of the row address "1110100110" by operating the address counter 3 as usual.

That is, each word line W in this embodiment
Refresh operation for L is the first time; "000000000
1 ", 2nd time;" 0000000010 "………… 933 time;" 1110100
101 ", 934th;" 0110100101 ", 935th;" 111010011
0 ", 936th;" 1110100111 "………… 1024th;" 11111
The row address is 11111 ".

As described above, in this embodiment, in one cycle of the refresh operation, the refresh operation is performed once for each memory cell in which the data holdable time is not insufficient, and the data holdable time is insufficient. The memory cells that are in use are relieved by performing the refresh operation twice. Therefore, in this embodiment, when the refresh operation is performed 1025 times by adding the refresh operation once to the word line WL of the row address "0110100101" to the refresh operation 1024 times which is the number of the word lines WL, Data will be refreshed for all the memory cells in the DRAM. for that reason,
The refresh interval in this embodiment is longer by one refresh operation than in the conventional example in which 1024 refresh operations are performed, but the increment is very small and can be practically ignored.

As described above, according to the present embodiment, it is possible to relieve a memory cell whose data retention time is insufficient without adding a redundant memory cell unlike the redundant memory alternative method. Therefore, it is possible to prevent an increase in the area of the semiconductor chip in which the DRAM is formed.

The above embodiments may be modified as follows, and in that case, the same operation and effect can be obtained. (1) In one cycle of the refresh operation, the memory cells whose data holdable time is insufficient are repaired by performing the refresh operation three times or more. For example, in one cycle of the refresh operation, when the refresh operation is performed four times for a memory cell whose data retention time is insufficient, the data retention time of the memory cell whose data retention time is insufficient is usually 1/4 of the memory cells will be good.

(2) Even when there are two or more memory cells whose data retention time is insufficient, the memory cells whose data retention time is insufficient in one cycle of the refresh operation are similar to the above embodiment. The above is relieved by performing the refresh operation twice or more.

(3) As in the above embodiment, each circuit (2 to
The row address decoder 5 is controlled by causing the CPU to perform an operation similar to that of each of the circuits (2, 4, 6 to 14) described above, instead of providing the hardware configuration by providing 4, 6 to 14). That is, the above embodiment is embodied as software.

(4) C instead of the self-refresh method
Applies to BR. Alternatively, it applies to ROR. In this case, in the self-refresh method, the refresh interval is specified to be long, and the data retention required time also becomes long, so that the effect of the present invention is more clearly exhibited. However, it goes without saying that the same effect as the self-refresh method can be obtained in CBR and ROR.

(5) The present invention is applied to a semiconductor memory device such as a pseudo SRAM which requires a refresh operation instead of a DRAM. (6) A magnetic bubble storage device, not a semiconductor storage device,
It is applied to various storage devices that require refresh operations, such as magnetic core storage devices and wire storage devices.

Although the respective embodiments have been described above, the technical ideas other than the claims which can be understood from the respective embodiments will be described.
The effects will be described below. (A) The memory device according to any one of claims 1 to 5, wherein the refresh operation is performed by one refresh system selected from the group of self-refresh system, CBR, and ROR.

By doing so, a reliable refresh operation can be performed. In particular, the refresh interval of the self-refresh method is specified to be longer than the refresh interval of ROR and CBR. The longer the refresh interval, the longer the data retention time required for the memory cell. Therefore, the effect of the present invention is more apparent in the self-refresh method.

(B) In the storage device according to any one of claims 1 to 5, the storage device is a semiconductor storage device,
One storage device selected from a magnetic bubble storage device, a magnetic core storage device, and a wire storage device.

By doing so, a reliable refresh operation can be performed in various storage devices.

[0048]

As described in detail above, according to the present invention, it is possible to provide a memory device capable of relieving a memory cell having a short data retention time without increasing the size of the memory device. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of an embodiment.

FIG. 2 is an internal circuit diagram of an address counter 3.

FIG. 3 is a time chart of an address counter 3.

FIG. 4 is an internal circuit diagram of an address match detection circuit 4.

FIG. 5 is a time chart showing the circuit operation of one embodiment.

Claims (5)

[Claims] 1. A storage device which performs a refresh operation so that data stored in a memory cell is not lost. 2. A storage device that performs a refresh operation so that data stored in a memory cell is not lost, and a refresh operation of a specific address is performed more times than a refresh operation of another address. 3. A memory device that performs a refresh operation to prevent the data stored in the memory cell from being lost. A memory device that performs more times than the refresh operation of a memory cell in which the holdable time is not insufficient. 4. A memory device that performs a refresh operation so that the data stored in the memory cell is not lost, for one cycle of the refresh operation, after the refresh operation of the memory cell whose data holdable time is insufficient is completed. A memory device that performs a refresh operation again on a memory cell whose data retention time is insufficient before and after a predetermined number of refresh operations. 5. The invention according to claim 1, wherein the memory device is a DRAM or a pseudo SRA.
A storage device that is M.