JPH0845940A - Solder wire and solder bump electrode - Google Patents

Solder wire and solder bump electrode

Info

Publication number
JPH0845940A
JPH0845940A JP6176916A JP17691694A JPH0845940A JP H0845940 A JPH0845940 A JP H0845940A JP 6176916 A JP6176916 A JP 6176916A JP 17691694 A JP17691694 A JP 17691694A JP H0845940 A JPH0845940 A JP H0845940A
Authority
JP
Japan
Prior art keywords
solder
chip
electrode
weight
solder bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6176916A
Other languages
Japanese (ja)
Inventor
Takatoshi Arikawa
孝俊 有川
Toshinori Kogashiwa
俊典 小柏
Hiroshi Murai
博 村井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP6176916A priority Critical patent/JPH0845940A/en
Publication of JPH0845940A publication Critical patent/JPH0845940A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】ICチップAl電極上の半田バンプをリフロー
処理するに際して、Al電極上に別工程で皮膜形成を行
う工程を省略し、且つ350℃でリフロー処理を行って
も接合強度の劣化が小さい半田バンプ電極を提供する。 【構成】Cu(0.01〜5.0重量%),Ni(0.
01〜5.0重量%),Zn(0.01〜5.0重量
%)から選ばれる2種以上、及び0.001〜1.0重
量%Tiを含有し、残部がSn又はPb−Snである半
田ワイヤを用いて、ICチップ1のAl電極2上に半田
バンプ3を形成し、この半田バンプ3を介してICチッ
プ1と基板4の電極2,5を接合した。この時、半田バ
ンプ3を350℃でリフロー処理して電極2,5間の位
置ずれを修正し、ICチップ1と基板4の接合不良を防
止する。半田バンプ3はリフロー処理を行っても剪断強
度の劣化を低く抑えることが出来、実用可能な剪断強度
を得ることが出来た。
(57) [Abstract] [Purpose] When reflowing solder bumps on an Al electrode of an IC chip, the process of forming a film on the Al electrode is omitted in a separate step, and the reflow process is performed at 350 ° C. (EN) Provided is a solder bump electrode with little deterioration in strength. [Constitution] Cu (0.01 to 5.0% by weight), Ni (0.
01 to 5.0% by weight), 2 or more kinds selected from Zn (0.01 to 5.0% by weight), and 0.001 to 1.0% by weight Ti, with the balance being Sn or Pb-Sn. The solder bump 3 was formed on the Al electrode 2 of the IC chip 1 by using the solder wire, and the IC chip 1 and the electrodes 2 and 5 of the substrate 4 were bonded via the solder bump 3. At this time, the solder bump 3 is subjected to a reflow treatment at 350 ° C. to correct the positional deviation between the electrodes 2 and 5 and prevent a defective joint between the IC chip 1 and the substrate 4. Even if the solder bump 3 was subjected to the reflow treatment, the deterioration of the shear strength could be suppressed to a low level, and the practical shear strength could be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はICチップの半田バンプ
電極及びそれに用いる半田ワイヤに関し、詳しくは、バ
ンプを介したワイヤレスボンディング法によりICチッ
プを基板に接続する半田バンプ電極、及びそれに用いる
半田ワイヤに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder bump electrode for an IC chip and a solder wire used for the same, and more particularly to a solder bump electrode for connecting an IC chip to a substrate by a wireless bonding method via a bump, and a solder wire used therefor. Regarding

【0002】[0002]

【従来の技術】近年、ICチップの高機能化に伴いLS
Iの入出力端子が増大する傾向にある。このため、IC
チップと基板を接続する方法として、フリップチップボ
ンディング等のバンプを介したワイヤレスボンディング
方法が注目を集めている。この方法は、ワイヤボンディ
ング方法がICチップの周辺しか電極パッドを設けるこ
とが出来ないのに対して、その全面に電極パッドを形成
出来るため、電極パッド数を増やし実装密度を高める方
法に適している。
2. Description of the Related Art In recent years, as IC chips have become more sophisticated, LS
The number of I / O terminals tends to increase. Therefore, IC
As a method for connecting a chip and a substrate, a wireless bonding method using bumps such as flip chip bonding has attracted attention. This method is suitable for the method of increasing the number of electrode pads and increasing the mounting density because the electrode bonding can be formed only on the periphery of the IC chip in the wire bonding method, while the electrode pads can be formed on the entire surface. .

【0003】ここで、バンプを介したワイヤレスボンデ
ィング方法の代表例としてフリップチップボンディング
について説明する。この方法は図1に示す通り、ICチ
ップ1のAl電極2に半田バンプ3を形成し、基板4に
は対応する位置に所定の電極5を形成する。このICチ
ップ1と基板4はそれぞれ電極2,5と半田バンプ3を
介して接合される。この時、図2に示す様に、ICチッ
プ1を基板4の所定位置に高精度で搭載することが困難
なため、電極2と5の位置にずれが生じることがある。
この様に電極2,5の中心線の位置がずれた状態でIC
チップ1と基板4が接合された場合接合不良となり、半
導体の作動不良の原因となる。
Here, flip chip bonding will be described as a typical example of a wireless bonding method via bumps. In this method, as shown in FIG. 1, solder bumps 3 are formed on the Al electrodes 2 of the IC chip 1 and predetermined electrodes 5 are formed on the substrate 4 at corresponding positions. The IC chip 1 and the substrate 4 are bonded to each other via the electrodes 2 and 5 and the solder bumps 3, respectively. At this time, as shown in FIG. 2, since it is difficult to mount the IC chip 1 at a predetermined position on the substrate 4 with high accuracy, the positions of the electrodes 2 and 5 may be displaced.
In this way, with the positions of the center lines of the electrodes 2 and 5 displaced, the IC
When the chip 1 and the substrate 4 are bonded, a bonding failure occurs, which causes a malfunction of the semiconductor.

【0004】この対応として特開平6−132353号
公報等には、半田バンプをリフローさせて接合精度を向
上させることが提案されており、これはICチップと基
板の電極位置に多少のずれがあっても両電極間に介在す
る半田バンプをリフローさせると、半田バンプが溶融し
た状態でその表面張力により表面積を極力小さくするよ
うに自己修正が行われ、ICチップのずれを解消出来る
とするものである。この方法はICチップ搭載上のずれ
を解消する方法として有効な方法であるが、ICチップ
Al電極上の半田バンプ材料をリフローするとICチッ
プと半田バンプの接合強度が低下するという問題が生じ
る。
In order to deal with this, Japanese Patent Laid-Open No. 6-132353 proposes to reflow solder bumps to improve the bonding accuracy. This is because the electrode positions of the IC chip and the substrate are slightly displaced. Even if the solder bumps interposed between the two electrodes are reflowed, the self-correction is performed so that the surface area of the solder bumps in the molten state is minimized by the surface tension, and the displacement of the IC chip can be eliminated. is there. This method is effective as a method for eliminating the deviation in mounting the IC chip, but when the solder bump material on the IC chip Al electrode is reflowed, there arises a problem that the bonding strength between the IC chip and the solder bump is lowered.

【0005】前記接合強度低下の対応として、ICチッ
プAl電極上にCr,Cu,Au又はTi,Ni,Au
等の多層スパッタ膜を形成することが試みられている。
しかし乍らこの方法は、工程が増えて時間を要しコスト
高になるという問題を有すると共に、リフロー処理温度
を低く抑えて、接合強度が低下することを防止する必要
がある。ここで、リフロー処理工程において他の接続材
料を融点の高い順に溶融し、半田バンプ材料は最後に低
温度でリフロー処理して接合強度が低下することを防止
する方法では、やはり工程が増えて時間を要するだけで
なくコスト高になるという問題を有する。このため、従
来多層スパッタ膜を形成した後227℃でリフロー処理
していたものを、多層スパッタ膜を形成することなく且
つ350℃でリフロー処理を行っても接合強度の低下を
防止することにより、他の接続材料の溶融を同時に行う
ことが検討されている。
In order to cope with the decrease in the bonding strength, Cr, Cu, Au or Ti, Ni, Au is formed on the IC chip Al electrode.
It has been attempted to form a multilayer sputtered film such as
However, this method has a problem that the number of steps increases, time is required, and the cost becomes high, and it is necessary to suppress the reflow treatment temperature to a low level and prevent the bonding strength from decreasing. Here, in the method of melting other connection materials in the order of higher melting point in the reflow treatment step, and finally reflowing the solder bump material at a low temperature to prevent the joint strength from decreasing, the number of steps also increases and There is a problem that not only the cost is increased but also the cost is increased. Therefore, by preventing the decrease in the bonding strength even after performing the reflow treatment at 350 ° C. without forming the multi-layer sputtered film, which was conventionally subjected to the reflow treatment at 227 ° C. after forming the multilayer sputtered film, Simultaneous melting of other connecting materials has been considered.

【0006】[0006]

【発明が解決しようとする課題】本発明は上記従来事情
に鑑み、ICチップAl電極上の半田バンプをリフロー
処理するに際して、Al電極上に別工程で皮膜形成を行
う工程を省略し、且つ350℃でリフロー処理を行って
も接合強度の劣化が小さい半田ワイヤ及びバンプ電極を
提供せんとするものである。
In view of the above-mentioned conventional circumstances, the present invention omits the step of forming a film on the Al electrode as a separate step when reflowing the solder bumps on the Al electrode of the IC chip. It is intended to provide a solder wire and a bump electrode whose bonding strength is less deteriorated even if reflow treatment is performed at a temperature of ℃.

【0007】[0007]

【課題を解決するための技術的手段】以上の目的を達成
するために本願第1発明は、半田材料の組成が下記〔組
成I〕であることを特徴とするICチップのバンプ電極
用半田ワイヤである。 〔組成I〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Tiを含有し、残部がSn又はPb−Snであ
る。
In order to achieve the above object, the first invention of the present application is the solder wire for bump electrode of IC chip, characterized in that the composition of the solder material is the following [composition I]. Is. [Composition I] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
It contains 0 wt% Ti and the balance is Sn or Pb-Sn.

【0008】また本願第2発明は、半田材料の組成が下
記〔組成II〕であることを特徴とするICチップのバン
プ電極用半田ワイヤである。 〔組成II〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Ti、1.0〜10.0重量%Sb、0.2〜
10.0重量%Agを含有し、残部がSn又はPb−S
nである。
A second invention of the present application is a solder wire for a bump electrode of an IC chip, wherein the composition of the solder material is the following [composition II]. [Composition II] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
0 wt% Ti, 1.0-10.0 wt% Sb, 0.2-
Contains 10.0 wt% Ag, balance Sn or Pb-S
n.

【0009】また本願第3発明は、半田材料の組成が下
記〔組成I〕であり、ICチップAl電極上で350℃
でリフローさせた後の剪断強度が19MPa以上である
ことを特徴とするICチップの半田バンプ電極用半田ワ
イヤである。 〔組成I〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Tiを含有し、残部がSn又はPb−Snであ
る。
In the third invention of the present application, the composition of the solder material is the following [composition I], and the composition is 350 ° C. on the Al electrode of the IC chip.
The solder wire for a solder bump electrode of an IC chip is characterized by having a shear strength of 19 MPa or more after being reflowed. [Composition I] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
It contains 0 wt% Ti and the balance is Sn or Pb-Sn.

【0010】さらに本願第4発明は、ICチップAl電
極上に形成された半田バンプ電極において、半田材料の
組成が下記〔組成I〕であり、且つICチップAl電極
と半田バンプの境界にCu,Ni,Znから選ばれる2
種以上、及びTiを含有する金属間化合物を形成してな
ることを特徴とするICチップの半田バンプ電極であ
る。 〔組成I〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Tiを含有し、残部がSn又はPb−Snであ
る。
Further, in the fourth invention of the present application, in the solder bump electrode formed on the IC chip Al electrode, the composition of the solder material is the following [composition I], and Cu, at the boundary between the IC chip Al electrode and the solder bump, 2 selected from Ni and Zn
A solder bump electrode for an IC chip, characterized in that an intermetallic compound containing at least one species and Ti is formed. [Composition I] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
It contains 0 wt% Ti and the balance is Sn or Pb-Sn.

【0011】[0011]

【作用】以下、本発明の構成と作用についてさらに説明
する。まず半田材料について説明すれば、半田材料はP
b−Sn合金を基合金とする。ここで半田材料中のSn
含有量は、下限が2重量%。上限が98重量%程度であ
ることが好ましい。Sn含有量が2重量%未満の時、半
田の表面酸化が激しく実用に耐えないという欠点があ
る。Sn含有量の上限98重量%程度は、有効な添加元
素を含みうる量である。
The structure and operation of the present invention will be further described below. First, the solder material is P
A b-Sn alloy is used as a base alloy. Here, Sn in the solder material
The lower limit of the content is 2% by weight. The upper limit is preferably about 98% by weight. If the Sn content is less than 2% by weight, there is a drawback that the surface oxidation of the solder is so severe that it cannot be put to practical use. The upper limit of the Sn content is about 98% by weight, which is an amount capable of containing an effective additive element.

【0012】また本発明の半田材料は、0.001〜
1.0重量%Tiを含有し、更に、Cu(0.01〜
5.0重量%),Ni(0.01〜5.0重量%),Z
n(0.01〜5.0重量%)の中から選ばれた2種以
上を含有することが必要である。Pb−Sn合金に対し
てTi、Cu、Ni、Znをこのように添加した合金半
田は、Al電極上でスパッタ膜被覆処理することなく3
50℃でリフローさせても、半田バンプ材の剪断強度の
劣化が小さく19MPa以上に出来る。また被覆処理す
ることなく227℃でリフローさせた後の剪断強度を基
準とした剪断強度維持率を90%以上とすることが出来
る。
The solder material of the present invention is 0.001 to
It contains 1.0 wt% Ti, and further contains Cu (0.01 to
5.0% by weight), Ni (0.01 to 5.0% by weight), Z
It is necessary to contain two or more kinds selected from n (0.01 to 5.0% by weight). The alloy solder obtained by adding Ti, Cu, Ni, and Zn to the Pb-Sn alloy in this way does not require sputter film coating treatment on the Al electrode.
Even when reflowed at 50 ° C., the shear strength of the solder bump material is less deteriorated and can be 19 MPa or more. Further, the shear strength retention rate based on the shear strength after reflow at 227 ° C. without coating treatment can be 90% or more.

【0013】Ti、Cu、Ni、Znの含有量は、Ti
(0.005〜0.5重量%)、Cu(0.05〜5.
0重量%)、Ni(0.05〜5.0重量%)、Zn
(0.05〜5.0重量%)であることが好ましい。こ
の時、Al電極上でスパッタ膜被覆処理することなく3
50℃でリフローさせても、半田バンプ材の剪断強度の
劣化は更に小さく、前記剪断強度維持率を100%とす
ることが出来る。
The contents of Ti, Cu, Ni and Zn are Ti
(0.005 to 0.5% by weight), Cu (0.05 to 5.
0% by weight), Ni (0.05 to 5.0% by weight), Zn
It is preferably (0.05 to 5.0% by weight). At this time, without coating the sputtered film on the Al electrode, 3
Even when the reflow is performed at 50 ° C., the deterioration of the shear strength of the solder bump material is further small, and the shear strength maintenance ratio can be 100%.

【0014】ここで、Ti含有量が0.001重量%未
満の時、スパッタ膜被覆処理することなく350℃でリ
フローさせると、剪断強度は19MPa以上に保持でき
るものの前記剪断強度維持率は約50%に低下する。T
i含有量が5.0重量%を越えると、アーク放電により
ボール形成する際、Tiが酸化してボールが偏心すると
いう欠点がある。Cu、Ni、Znの内少なくとも2種
を前記必要量含有しない時、スパッタ膜被覆処理するこ
となく350℃でリフローさせると、剪断強度は19M
Paに達しない。Cu、Ni、Znの内少なくとも2種
の含有量が各々5.0重量%を越えると、ワイヤが著し
く硬化し伸線加工に支障をきたすという欠点がある。こ
のためTi、Cu、Ni、Znの含有量は前述のごと
く、Ti(0.001〜1.0重量%)、Cu(0.0
1〜5.0重量%)、Ni(0.01〜5.0重量
%)、Zn(0.01〜5.0重量%)と定めた。
Here, when the Ti content is less than 0.001% by weight, when the reflow is performed at 350 ° C. without the sputter film coating treatment, the shear strength can be maintained at 19 MPa or more, but the shear strength maintenance ratio is about 50. %. T
If the i content exceeds 5.0% by weight, there is a drawback that Ti is oxidized and the ball is eccentric when the ball is formed by arc discharge. When at least two kinds of Cu, Ni and Zn are not contained in the required amount, the shear strength is 19 M when reflowed at 350 ° C. without the sputter film coating treatment.
Does not reach Pa. If the content of at least two kinds of Cu, Ni and Zn exceeds 5.0% by weight respectively, there is a drawback that the wire is significantly hardened and the wire drawing process is hindered. Therefore, the contents of Ti, Cu, Ni and Zn are Ti (0.001 to 1.0% by weight) and Cu (0.0
1 to 5.0% by weight), Ni (0.01 to 5.0% by weight), and Zn (0.01 to 5.0% by weight).

【0015】さらに本発明においては、半田材料を前記
構成にすることに加えて、半田材料として通常含有され
る成分を含み得るものである。冷間加工性を向上させる
ための0.2〜10重量%Ag、半田材料の強度を向上
させ取扱いを容易にするための1〜10重量%Sb等が
例示出来る。
Further, in the present invention, in addition to the above-mentioned constitution of the solder material, it is possible to include components usually contained as the solder material. Examples include 0.2 to 10 wt% Ag for improving cold workability, and 1 to 10 wt% Sb for improving the strength of the solder material and facilitating handling.

【0016】本発明において半田材料を上記した構成に
することにより、Al電極上でスパッタ膜被覆処理する
ことなく350℃でリフローさせても半田バンプ材の剪
断強度の劣化を小さく出来る理由は十分に解明されてい
ないものの、Al電極上で半田バンプ材を350℃でリ
フローさせた場合、従来はAl成分が半田バンプ材中に
拡散されてAl電極が消滅する傾向にあることに対し、
本発明においては図3に示すように、Al電極2と半田
バンプ材3aの境界に金属間化合物6が形成され、この化
合物6の中にCu,Ni,Znの内少なくとも2種、及
びTiを含むことが、Al電極上で350℃でリフロー
させてもAl成分が半田バンプ材中に拡散されることを
阻止する働きをしているものと考えられる。
The reason why the solder material of the present invention has the above-described structure can sufficiently reduce the deterioration of the shear strength of the solder bump material even if the solder material is reflowed at 350 ° C. without performing the sputter film coating treatment on the Al electrode. Although it has not been clarified, when the solder bump material is reflowed on the Al electrode at 350 ° C., conventionally, the Al component is diffused in the solder bump material and the Al electrode tends to disappear.
In the present invention, as shown in FIG. 3, an intermetallic compound 6 is formed at the boundary between the Al electrode 2 and the solder bump material 3a, and at least two kinds of Cu, Ni and Zn and Ti are contained in the compound 6. It is considered that the inclusion of Al functions to prevent the Al component from diffusing into the solder bump material even when reflowed on the Al electrode at 350 ° C.

【0017】次に、半田ワイヤの製造方法について説明
する。本発明になる半田ワイヤの製造方法としては次の
二つの方法が例示出来る。第1の方法は上記構成の半田
材料を溶解し、鋳造、押出、伸線加工を行うことにより
直径30〜100μmのワイヤに仕上げる。第2の方法
は前記構成の半田材料を溶解し、該溶湯を水中に噴射す
る急冷凝固法により素線を得、次いで伸線加工を行うこ
とにより直径30〜100μmのワイヤに仕上げる。本
発明においては第2の方法である急冷凝固法が好ましく
採用される。この理由は、均一な組成が得られると共に
良好な機械的性質が得られ、バンプ形成のハンドリング
が容易になるためである。
Next, a method of manufacturing the solder wire will be described. The following two methods can be exemplified as the method for manufacturing the solder wire according to the present invention. In the first method, the solder material having the above-mentioned structure is melted, and casting, extrusion, and wire drawing are performed to finish a wire having a diameter of 30 to 100 μm. The second method is to melt the solder material having the above-mentioned structure, obtain a wire by a rapid solidification method in which the molten metal is injected into water, and then perform wire drawing to finish a wire having a diameter of 30 to 100 μm. In the present invention, the second method, the rapid solidification method, is preferably adopted. The reason is that a uniform composition can be obtained, good mechanical properties can be obtained, and the handling of bump formation becomes easy.

【0018】以下に、図4を参照して、半田バンプの形
成方法と、ICチップと基板の接合について述べる。 半田ボールの形成 (a)図において、半田ワイヤ7はキャピラリ8からそ
の先端部を導出し、トーチ9を加熱源として半田ボール
10を形成する。 半田ボールの圧着 (b)図において、キャピラリ8を下降させることによ
り半田ボール10はICチップ1上のAl電極2上に圧
着される。ここでAl電極として、通常はAl−Siや
Al−Cu−Si等のAl合金が用いられる。 半田バンプの形成 (c)図において、キャピラリ8を引き上げることによ
り、半田ボール10のネック部が破断して半田ボール1
0がAl電極2上に残留する。この残留した半田ボール
10を半田バンプ3と呼ぶ。 ICチップ1と基板4の接合 (d)図において、ICチップ1と基板4はそれぞれの
電極2,5と半田バンプ3を介して接合される。この時
前述のように、半田バンプ材を溶融状態に至る迄加熱す
る所謂リフロー処理を行う。このリフロー処理を行うこ
とにより、ICチップ1と基板4の電極2,5の位置ず
れによる接合不良を、溶融した半田バンプ材の表面張力
を利用して自己修正させることが出来る。
The method of forming the solder bumps and the joining of the IC chip and the substrate will be described below with reference to FIG. Formation of Solder Ball In FIG. 1A, the solder wire 7 is led out of its tip from the capillary 8 and the solder ball 10 is formed using the torch 9 as a heating source. Solder ball crimping (b) In the figure, the solder ball 10 is crimped onto the Al electrode 2 on the IC chip 1 by lowering the capillary 8. Here, an Al alloy such as Al-Si or Al-Cu-Si is usually used as the Al electrode. Formation of Solder Bumps In FIG. 1C, the capillary 8 is pulled up, the neck portion of the solder ball 10 is broken, and the solder ball 1
0 remains on the Al electrode 2. The remaining solder balls 10 are called solder bumps 3. Bonding of IC Chip 1 and Substrate 4 In the diagram (d), the IC chip 1 and the substrate 4 are bonded to each other via electrodes 2 and 5 and solder bumps 3. At this time, as described above, so-called reflow treatment is performed to heat the solder bump material until it reaches a molten state. By performing this reflow process, it is possible to self-correct the bonding failure due to the positional displacement of the electrodes 2 and 5 of the IC chip 1 and the substrate 4 by utilizing the surface tension of the melted solder bump material.

【0019】[0019]

【実施例】以下、実施例について説明する。 〔実施例1〕50重量%Sn、0.001重量%Ti、
0.5重量%Cu、0.5重量%Ni、5.0重量%S
b、5.0重量%Ag、残部Pbとなるように、半田合
金100gをアルゴンガス雰囲気中で溶解し、アルゴン
ガス圧で穴径300μm石英ノズルから噴出させ、25
0rpmで回転している水層を形成した円筒ドラム内で
急冷凝固させ半田素線を得た。この素線を伸線加工して
直径50μmの半田ワイヤに仕上げた。ここで得られた
半田ワイヤを用いて、図4(a)〜(c)の手順に従っ
てICチップ1のAl−Si合金電極2上に半田バンプ
3を形成した。図4(a)〜(c)と同様の手順に従っ
て20個の半田バンプ試料を作成し、この内10個の半
田バンプ試料については日本アルファーメタルズ社製ロ
ジン系フラックス(商品名:α5003TR)を塗布
し、アルゴンガス雰囲気中で加熱台を用いて227℃と
350℃で加熱し、半田バンプをリフローさせた。2種
類のリフロー処理した各10個の半田バンプ材について
剪断強度を測定した。その結果を表2中に示す。次い
で、X線回析装置を用いて図3に示す金属間化合物6を
測定した。確認出来たTi、Cu、Ni、Zn成分の種
類を表2中に示す。
EXAMPLES Examples will be described below. [Example 1] 50 wt% Sn, 0.001 wt% Ti,
0.5 wt% Cu, 0.5 wt% Ni, 5.0 wt% S
b, 5.0 wt% Ag, and the balance Pb, 100 g of the solder alloy was melted in an argon gas atmosphere, and was jetted from a quartz nozzle with a hole diameter of 300 μm at an argon gas pressure of 25 g.
A solder wire was obtained by rapid solidification in a cylindrical drum formed with a water layer rotating at 0 rpm. This wire was drawn to form a solder wire with a diameter of 50 μm. Using the solder wire obtained here, the solder bump 3 was formed on the Al—Si alloy electrode 2 of the IC chip 1 according to the procedure of FIGS. 20 solder bump samples were prepared according to the same procedure as in FIGS. 4 (a) to 4 (c), and 10 solder bump samples were coated with rosin-based flux (trade name: α5003TR) manufactured by Japan Alpha Metals Co., Ltd. Then, the solder bumps were reflowed by heating at 227 ° C. and 350 ° C. using a heating table in an argon gas atmosphere. Shear strength was measured for each of 10 solder bump materials subjected to two types of reflow treatment. The results are shown in Table 2. Then, the intermetallic compound 6 shown in FIG. 3 was measured using an X-ray diffraction apparatus. Table 2 shows the types of confirmed Ti, Cu, Ni and Zn components.

【0020】〔剪断強度の測定方法〕半田バンプ材とI
CチップAl電極の間の剪断荷重をボンディング強度試
験装置を用いて測定し、光学顕微鏡により測定した接合
面積当りの剪断強度(MPa)で表示した。
[Method of Measuring Shear Strength] Solder bump material and I
The shear load between the C-chip Al electrodes was measured using a bonding strength tester, and the shear strength (MPa) per joint area measured by an optical microscope was displayed.

【0021】〔実施例2〜26、比較例1〜9〕半田ワ
イヤの組成を表1の様にしたこと以外は実施例1と同様
にして試験を行った。測定結果を表2に示す。
[Examples 2 to 26, Comparative Examples 1 to 9] Tests were conducted in the same manner as in Example 1 except that the composition of the solder wire was as shown in Table 1. The measurement results are shown in Table 2.

【0022】[0022]

【表1】 [Table 1]

【0023】[0023]

【表2】 [Table 2]

【0024】表1及び表2の実施例1〜26から明らか
な様に、半田材料中のSn含有量が10〜98重量%程
度であるPb−Sn合金、又はSnを基合金とし、且つ
0.001〜1.0重量%Tiに加えて、0.01〜
5.0重量%Cu,0.01〜5.0重量%Ni,0.
01〜5.0重量Znの内2種以上を含有した半田ワイ
ヤを用いて半田バンプを形成することにより、Al電極
上でスパッタ膜被覆処理することなく350℃でリフロ
ー処理しても、剪断強度はいずれも19MPa以上であ
り、従来のリフロー処理温度である227℃でリフロー
処理した後の剪断強度を基準とした剪断強度維持率は9
0%以上であることが判る。
As is clear from Examples 1 to 26 in Tables 1 and 2, the Sn content in the solder material is about 10 to 98% by weight, which is a Pb-Sn alloy or an Sn-based alloy, and 0 0.001-1.0 wt% Ti, 0.01-
5.0 wt% Cu, 0.01 to 5.0 wt% Ni, 0.
By forming a solder bump using a solder wire containing two or more of 01 to 5.0 weight Zn, the shear strength can be obtained even if the reflow treatment is performed at 350 ° C. without performing the sputter film coating treatment on the Al electrode. Is 19 MPa or more, and the shear strength maintenance ratio based on the shear strength after reflow treatment at 227 ° C. which is the conventional reflow treatment temperature is 9
It can be seen that it is 0% or more.

【0025】ここで、Tiを0.005〜0.5重量%
含有し、それに加えて2種類以上含有させるCu、N
i、Znを夫々0.05〜5.0重量%含有させると更
に優れた効果を示し、350℃で直接リフロー処理して
も剪断強度はいずれも30MPa以上であり、剪断強度
維持率は100%以上であることが判る。
Here, 0.005 to 0.5% by weight of Ti is used.
Cu, N to be included and to be added in addition to two or more kinds
When 0.05 to 5.0% by weight of each of i and Zn is contained, a more excellent effect is exhibited, and the shear strength is 30 MPa or more even if direct reflow treatment is performed at 350 ° C., and the shear strength retention rate is 100%. It turns out that this is the end.

【0026】これに対して、Pb−Sn合金を基合金と
しているものの、0.001〜1.0重量%Ti、若し
くは0.01〜5.0重量%Cu,0.01〜5.0重
量%Ni,0.01〜5.0重量%Znの内2種以上を
含有していない場合は、比較例1〜9から明らかな様
に、350℃でリフロー処理しても剪断強度はいずれも
25MPa以下であり、剪断強度維持率はいずれも45
%以下であることが判る。
On the other hand, although the Pb-Sn alloy is used as the base alloy, 0.001 to 1.0 wt% Ti, or 0.01 to 5.0 wt% Cu, 0.01 to 5.0 wt% % Ni and 0.01 to 5.0% by weight of Zn are not contained, as is clear from Comparative Examples 1 to 9, even if the reflow treatment is performed at 350 ° C., the shear strength is none. 25 MPa or less, and the shear strength maintenance rate is 45 in each case.
It turns out that it is less than or equal to%.

【0027】[0027]

【発明の効果】以上説明したように本発明は、半田バン
プ形成に用いる半田ワイヤの組成を上記構成とすること
により、ICチップAl電極上の半田バンプ材料をスパ
ッタ膜被覆処理するこなく、350℃でリフロー処理を
行っても剪断強度の劣化を低く抑えることが出来、実用
可能な剪断強度を得ることが出来た。従って、Al電極
上に別工程で皮膜形成を行なう必要があり、且つ他の接
続材料の溶融と別工程でリフロー処理を行う必要がある
従来のものに比べて、バンプ電極の形成、半導体装置の
製造にかかる工程が減って時間を要せず、コストも低減
出来る。
As described above, according to the present invention, the composition of the solder wire used for forming the solder bump is set to the above-mentioned structure, so that the solder bump material on the IC chip Al electrode is not subjected to the sputtered film coating process. Even if the reflow treatment was performed at ℃, the deterioration of the shear strength could be suppressed to a low level, and the practical shear strength could be obtained. Therefore, it is necessary to form the film on the Al electrode in a separate step, and to form the bump electrode and the semiconductor device in comparison with the conventional one in which another connection material needs to be melted and a reflow process needs to be performed in a separate step. The number of manufacturing steps is reduced, time is not required, and cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】フリップチップボンディング法の概要を示す簡
略図。
FIG. 1 is a simplified diagram showing an outline of a flip chip bonding method.

【図2】フリップチップボンディング法においてICチ
ップにずれが生じた場合を示す簡略図。
FIG. 2 is a simplified diagram showing a case where an IC chip is displaced in a flip chip bonding method.

【図3】本発明に係る半田バンプ電極の一実施例を示す
簡略図で、リフロー処理した状態を表す。
FIG. 3 is a simplified diagram showing an embodiment of a solder bump electrode according to the present invention, showing a state after reflow processing.

【図4】半田バンプの形成方法及びICチップと基板の
接合の概要を示す簡略図。
FIG. 4 is a simplified diagram showing an outline of a method of forming solder bumps and joining of an IC chip and a substrate.

【符号の説明】[Explanation of symbols]

1:ICチップ 2:Al電極 3:半田バンプ 4:基板 5:電極 6:金属間化合物 1: IC chip 2: Al electrode 3: Solder bump 4: Substrate 5: Electrode 6: Intermetallic compound

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半田材料の組成が下記〔組成I〕である
ことを特徴とするICチップバンプ電極用半田ワイヤ。 〔組成I〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Tiを含有し、残部がSn又はPb−Snであ
る。
1. A solder wire for an IC chip bump electrode, wherein the composition of the solder material is the following [composition I]. [Composition I] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
It contains 0 wt% Ti and the balance is Sn or Pb-Sn.
【請求項2】 半田材料の組成が下記〔組成II〕である
ことを特徴とするICチップバンプ電極用半田ワイヤ。 〔組成II〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Ti、1.0〜10.0重量%Sb、0.2〜
10.0重量%Agを含有し、残部がSn又はPb−S
nである。
2. A solder wire for an IC chip bump electrode, wherein the composition of the solder material is the following [composition II]. [Composition II] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
0 wt% Ti, 1.0-10.0 wt% Sb, 0.2-
Contains 10.0 wt% Ag, balance Sn or Pb-S
n.
【請求項3】 半田材料の組成が下記〔組成I〕であ
り、ICチップAl電極上で350℃でリフローさせた
後の剪断強度が19MPa以上であることを特徴とする
ICチップバンプ電極用半田ワイヤ。 〔組成I〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Tiを含有し、残部がSn又はPb−Snであ
る。
3. A solder for an IC chip bump electrode, wherein the composition of the solder material is the following [Composition I], and the shear strength after reflowing at 350 ° C. on the IC chip Al electrode is 19 MPa or more. Wire. [Composition I] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
It contains 0 wt% Ti and the balance is Sn or Pb-Sn.
【請求項4】 ICチップAl電極上に形成された半田
バンプ電極において、半田材料の組成が下記〔組成I〕
であり、且つICチップAl電極と半田バンプの境界に
Cu,Ni,Znから選ばれる2種以上、及びTiを含
有する金属間化合物を形成してなることを特徴とするI
Cチップ半田バンプ電極。 〔組成I〕Cu(0.01〜5.0重量%),Ni
(0.01〜5.0重量%),Zn(0.01〜5.0
重量%)から選ばれる2種以上、及び0.001〜1.
0重量%Tiを含有し、残部がSn又はPb−Snであ
る。
4. In a solder bump electrode formed on an IC chip Al electrode, the composition of the solder material is the following [composition I].
And an intermetallic compound containing Ti and two or more kinds selected from Cu, Ni and Zn is formed at the boundary between the IC chip Al electrode and the solder bump.
C chip solder bump electrode. [Composition I] Cu (0.01 to 5.0% by weight), Ni
(0.01 to 5.0% by weight), Zn (0.01 to 5.0)
2% or more, and 0.001-1.
It contains 0 wt% Ti and the balance is Sn or Pb-Sn.
JP6176916A 1994-07-28 1994-07-28 Solder wire and solder bump electrode Pending JPH0845940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6176916A JPH0845940A (en) 1994-07-28 1994-07-28 Solder wire and solder bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6176916A JPH0845940A (en) 1994-07-28 1994-07-28 Solder wire and solder bump electrode

Publications (1)

Publication Number Publication Date
JPH0845940A true JPH0845940A (en) 1996-02-16

Family

ID=16022009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6176916A Pending JPH0845940A (en) 1994-07-28 1994-07-28 Solder wire and solder bump electrode

Country Status (1)

Country Link
JP (1) JPH0845940A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6319461B1 (en) * 1999-06-11 2001-11-20 Nippon Sheet Glass Co., Ltd. Lead-free solder alloy
JP2002151538A (en) * 2000-11-10 2002-05-24 Nippon Steel Corp Semiconductor device and its producing method
US6440360B1 (en) * 1999-02-08 2002-08-27 Tokyo First Trading Company Pb-free soldering alloy
JP2005026715A (en) * 1996-08-27 2005-01-27 Nippon Steel Corp Semiconductor device having low melting point metal bump and flip chip bonding method
US10195698B2 (en) 2015-09-03 2019-02-05 AIM Metals & Alloys Inc. Lead-free high reliability solder alloys

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005026715A (en) * 1996-08-27 2005-01-27 Nippon Steel Corp Semiconductor device having low melting point metal bump and flip chip bonding method
US6440360B1 (en) * 1999-02-08 2002-08-27 Tokyo First Trading Company Pb-free soldering alloy
US6319461B1 (en) * 1999-06-11 2001-11-20 Nippon Sheet Glass Co., Ltd. Lead-free solder alloy
JP2002151538A (en) * 2000-11-10 2002-05-24 Nippon Steel Corp Semiconductor device and its producing method
US10195698B2 (en) 2015-09-03 2019-02-05 AIM Metals & Alloys Inc. Lead-free high reliability solder alloys

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