JPH0845982A - Semiconductor device mounting structure and method - Google Patents
Semiconductor device mounting structure and methodInfo
- Publication number
- JPH0845982A JPH0845982A JP6176380A JP17638094A JPH0845982A JP H0845982 A JPH0845982 A JP H0845982A JP 6176380 A JP6176380 A JP 6176380A JP 17638094 A JP17638094 A JP 17638094A JP H0845982 A JPH0845982 A JP H0845982A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pad
- solder
- board
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 MCMを、BGAでマザーボードにはんだ溶
融接合する場合に、MCM基板及びマザーボードの反り
と、BGAボール高さバラツキにより生じる接続不良を
無くし品質の向上を図ることを目的とする。
【構成】 MCM基板2には、表面にLSI1及び、そ
の他の電子部品が搭載されている。これらの部品が搭載
されている基板2の裏面には導体パッド3と、その上に
接続用はんだボールが形成されている。そしてパッド7
にはパッド3上に形成したはんだボールと同じ高さにな
るだけのはんだ量が供給されている。基板6側のパッド
9は、パッド7より広い面積を有している。基板2を基
板6の所定の位置に搭載し、リフロー加熱することによ
りMCM基板2及び基板6間のはんだ溶融接続の構造を
得る。
(57) [Abstract] [Purpose] To improve the quality by eliminating the warp of the MCM substrate and the mother board and the connection failure caused by the variation in the height of the BGA ball when the MCM is solder-melt bonded to the mother board by BGA. And [Structure] The LSI 1 and other electronic components are mounted on the surface of the MCM substrate 2. On the back surface of the substrate 2 on which these components are mounted, a conductor pad 3 and a solder ball for connection are formed thereon. And pad 7
Is supplied with an amount of solder that is as high as the solder ball formed on the pad 3. The pad 9 on the substrate 6 side has a larger area than the pad 7. The substrate 2 is mounted on the substrate 6 at a predetermined position and reflow heated to obtain a structure of solder fusion connection between the MCM substrate 2 and the substrate 6.
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の実装構造
及び方法に関し、特にマルチチップモジュール(MC
M)などのはんだボールを用いたボールグリッドアレイ
(BGA)で基板間を、はんだ溶融接続する実装構造及
び方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure and method, and more particularly to a multi-chip module (MC).
The present invention relates to a mounting structure and method for solder-melt connection between substrates with a ball grid array (BGA) using solder balls such as M).
【0002】[0002]
【従来の技術】図3(A)に従来のMCMの断面図を示
す。このMCMは、表面にLSI1やその他の電子部品
を搭載したMCM基板2の裏面に、BGA接続パッド3
上にはんだボール12が形成されている。図3(B)
は、図3(A)のMCMを配線基板6に搭載し、その後
この基板6上に搭載している他の電子部品と一括ではん
だボール12をリフロー加熱することではんだ接続部4
がBGA接続パッド3及び基板6上のパッド5に固着し
はんだ溶融接続が完了する。このようなBGAを用いた
半導体装置の実装構造としてUSP5241133及び
USP5216278がある。2. Description of the Related Art FIG. 3A shows a sectional view of a conventional MCM. This MCM has a BGA connection pad 3 on the back surface of an MCM substrate 2 on the front surface of which an LSI 1 and other electronic components are mounted.
Solder balls 12 are formed on the top. FIG. 3 (B)
3A is mounted on the wiring board 6 and then the solder balls 12 are reflow-heated together with the other electronic components mounted on the board 6 so that the solder connection portion 4 can be formed.
Adheres to the BGA connection pad 3 and the pad 5 on the substrate 6 to complete the solder fusion connection. As a mounting structure of a semiconductor device using such a BGA, there are USP 5241133 and USP 5216278.
【0003】このような構造のBGAで配線基板に接続
した場合、MCM基板2と配線基板6の反り及び、BG
Aパッド3上に形成したはんだボール12の高さバラツ
キによって配線基板6側のパッド5に接続されない箇所
が発生する。又、はんだ接続部4ははんだ形状が図3
(B)に示すように中央部がふくらんだ球欠体となって
いて、MCM基板2側のパッド3及び、配線基板6側の
パッド5と接合している部分がくびれて断面積では最も
小さい部分となる。このため熱ひずみが生じるとはんだ
接合部4のくびれた部分に応力が集中し疲労破壊を起す
欠点がある。When the BGA having such a structure is connected to the wiring board, warpage of the MCM board 2 and the wiring board 6 and BG
Due to variations in the height of the solder balls 12 formed on the A pads 3, there are places where the solder balls 12 are not connected to the pads 5 on the wiring board 6 side. Further, the solder connection portion 4 has a solder shape shown in FIG.
As shown in (B), the central portion is a bulged sphere, and the portion joined to the pad 3 on the MCM substrate 2 side and the pad 5 on the wiring substrate 6 side is constricted and the cross-sectional area is the smallest. It becomes a part. For this reason, when thermal strain occurs, stress concentrates on the constricted portion of the solder joint portion 4, causing a fatigue fracture.
【0004】この問題を解決するため図4に示すように
はんだ接続部14を鼓状や円柱状に引伸ばした構造にし
て対応している。図4に示すような接続部14を得る方
法として例えば特開昭57−118650号公報に記載
されているものがあり、これを図5に示す。これはシリ
コンチップ11にはんだバンプを形成し配線基板6に接
続する際の工法であるが、この方法は、チップ11の周
辺に予めはんだバンプを形成しておき、これを配線基板
6上のパッド5に仮付けした後、これらを加熱炉に入れ
て加熱することによりはんだを溶融させ、基板6上のパ
ッド5にはんだを融着させた後、はんだが溶融している
時に真空チャック方式のツール10を用いて、はんだ接
続部14の形状が円柱状になるようにチップ11を持ち
上げる。この状態ではんだを冷却させることにより所望
の形状をもった接続部14を得ている。このような工法
をMCMの場合に用いるとツール10で吸着すべきMC
M基板の表面に部品が搭載されているので、これらの部
品に当らないような形状にツールを加工しなければいけ
ないという欠点がある。In order to solve this problem, as shown in FIG. 4, the solder connecting portion 14 has a structure in which it is stretched into a drum shape or a column shape. As a method for obtaining the connecting portion 14 as shown in FIG. 4, there is one described in, for example, JP-A-57-118650, which is shown in FIG. This is a method for forming solder bumps on the silicon chip 11 and connecting them to the wiring board 6. In this method, solder bumps are formed in advance around the chip 11 and the solder bumps are formed on the wiring board 6. After being temporarily attached to No. 5, the solder is melted by putting them in a heating furnace and heating them to fuse the solder to the pads 5 on the substrate 6, and then when the solder is melted, a vacuum chuck type tool Using 10, the chip 11 is lifted so that the shape of the solder connection portion 14 is cylindrical. By cooling the solder in this state, the connection portion 14 having a desired shape is obtained. When such a construction method is used in the case of MCM, the MC to be adsorbed by the tool 10
Since the components are mounted on the surface of the M substrate, there is a drawback that the tool has to be processed into a shape that does not hit these components.
【0005】図4に示すような接続部14を得る他の方
法として特開昭55−163852号公報に記載されて
いるものがあり、これを図6に示す。これは、チップ1
1に配線基板6のパッド5と接続されるはんだ接続部1
7となるはんだバンプが形成されるパッド3が設けてあ
り、さらにパッド3と大きさの異なったパッド16と、
はんだ接続部17のものとは別個のはんだバンプ18が
形成してある。この二つの基板11と6とを接続する場
合は、はんだ接続部17となるバンプ及び18を溶融さ
せてパッド3とパッド5とをはんだ接続部17により接
続する。このときはんだバンプ18のはんだ量ははんだ
接続部17のものより大きくしてあるのではんだバンプ
18の表面張力により、両基板11、6の間隔が広が
る。このようにして図6のはんだ接続部17の形状を得
ており、接続部のふくらみに起因する接続不良を防止し
ている。しかしこの方法では、基板11、6の反りやは
んだバンプ(又ははんだボール)の高さのバラツキによ
り、はんだバンプの先端と基板側のパッドが接触してな
い場合、未接続の不良が発生するという欠点がある。Another method for obtaining the connecting portion 14 as shown in FIG. 4 is disclosed in Japanese Patent Laid-Open No. 163852/55, which is shown in FIG. This is chip 1
1 is a solder connection portion 1 connected to the pad 5 of the wiring board 6
7 is provided with a pad 3 on which a solder bump to be formed is formed, and a pad 16 having a size different from that of the pad 3,
Solder bumps 18 different from those of the solder connection portion 17 are formed. When connecting the two substrates 11 and 6, the bumps and 18 to be the solder connecting portions 17 are melted and the pads 3 and 5 are connected by the solder connecting portions 17. At this time, since the solder amount of the solder bump 18 is larger than that of the solder connection portion 17, the surface tension of the solder bump 18 widens the space between the substrates 11 and 6. In this way, the shape of the solder connection part 17 of FIG. 6 is obtained, and the connection failure due to the bulge of the connection part is prevented. However, according to this method, when the tips of the solder bumps and the pads on the board are not in contact with each other due to the warp of the boards 11 and 6 and the variation in the height of the solder bumps (or solder balls), unconnected defects are said to occur. There are drawbacks.
【0006】[0006]
【発明が解決しようとする課題】上述した従来の半導体
装置の実装構造及び方法では、いずれも基板の反りや、
はんだボールの高さのバラツキでのはんだ接続部とパッ
ドとの未接触によって生じる接続不良の低減や、高信頼
度のはんだ接続を得ることが困難であるという問題点が
あった。In any of the above-described conventional semiconductor device mounting structures and methods, warpage of the substrate,
There are problems that it is difficult to reduce connection failure caused by non-contact between the solder connection portion and the pad due to variations in the height of the solder balls, and it is difficult to obtain highly reliable solder connection.
【0007】[0007]
【課題を解決するための手段】本発明の半導体装置の接
続構造は、第1の基板と、第2の基板と、前記第1の基
板に設けられた第1のパッド及び前記第2の基板に設け
られた第2のパッドに溶融接続されたはんだボールから
なるはんだ接続部と、前記第1の基板に設けられた第1
の基板間隔制御用パッド及び前記第2の基板に設けられ
前記第1の基板間隔制御用パッドより面積が広い第2の
基板間隔制御用パッドに溶融接続された基板間隔制御用
はんだ接続部とを備え、前記第1の基板が当接する突起
を前記第2の基板に設けてもよい。A semiconductor device connection structure according to the present invention comprises a first substrate, a second substrate, a first pad provided on the first substrate, and the second substrate. A solder connection portion formed of a solder ball fused and connected to a second pad provided on the first substrate, and a first solder provided on the first substrate.
And a board-interval-controlling solder connection portion, which is provided on the second board and has a larger area than the first board-interval control pad, and is fused and connected to the second board-interval control pad. The second substrate may be provided with a projection with which the first substrate abuts.
【0008】本発明の半導体装置の接続方法は、第1の
基板に設けられた第1のパッド上にはんだボールを形成
し、前記第1の基板に設けられた第1の基板間隔制御用
パッドに前記はんだボールと同一高さの基板間隔制御用
はんだを供給し、前記第1のパッドを第2の基板に設け
られた第2のパッドに前記第1の基板間隔制御用パッド
を前記第2の基板に設けられ前記第1の基板間隔制御用
パッドより広い面積の第2の基板間隔制御用パッドに位
置を合わせて前記第1の基板を前記第2の基板に搭載
し、前記はんだボール及び前記基板間隔制御用はんだそ
れぞれをリフロー加熱して対応する前記第2のパッド及
び前記第2の基板間隔制御用パッドに溶融接続すること
を特徴とする。According to the method of connecting a semiconductor device of the present invention, a solder ball is formed on a first pad provided on a first substrate, and a first substrate gap control pad provided on the first substrate. Substrate soldering control solder having the same height as the solder balls is supplied to the second pad provided on the second substrate and the first substrate spacing control pad to the second pad. The first board is mounted on the second board by aligning with the second board spacing control pad which is provided on the board and has a larger area than the first board spacing control pad. Each of the substrate spacing control solders is reflow-heated to be melted and connected to the corresponding second pad and second substrate spacing control pad.
【0009】[0009]
【作用】はんだボールを用いて第1及び第2の基板を接
続する場合に、第1及び第2の基板の回路間の導通目的
用の本来のはんだボールとは別個に第1の基板に設けた
第1の基板間隔制御用パッドにはんだを供給しておき、
第2の基板には、対応した位置により大きな面積の第2
の基板間隔制御用パッドを配置する。この両基板を合わ
せてリフロー加熱すると第1の基板間隔制御用パッドに
供給されたはんだが溶融し広い面積を有するパッドに濡
れ広がる。この時、双方の基板が引き寄せられるため、
基板の反りや、はんだボール高さのバラツキを吸収しは
んだボールとパッドとの未接触による接続不良の発生を
解消するとともに、第2の基板間隔制御用パッドに濡れ
て広がったはんだがフィレット状の接続部を形成するた
め接続強度が増す。これにより、接続部の信頼性を高め
ることになる。When the first and second substrates are connected using the solder balls, the solder balls are provided on the first substrate separately from the original solder balls for the purpose of conduction between the circuits of the first and second substrates. Solder is supplied to the first board gap control pad,
The second substrate has a second
The pad for controlling the substrate spacing is arranged. When these two substrates are combined and reflow heated, the solder supplied to the first substrate gap control pad melts and wets and spreads on the pad having a large area. At this time, since both boards are attracted,
The warp of the board and the variation of the height of the solder balls are absorbed to eliminate the occurrence of the connection failure due to the non-contact between the solder balls and the pads, and the solder spread on the second board gap control pad spreads in a fillet shape. Since the connection portion is formed, the connection strength is increased. This will increase the reliability of the connection.
【0010】[0010]
【実施例】本発明の実施例を図を用いて説明する。Embodiments of the present invention will be described with reference to the drawings.
【0011】図1(A)は、本発明の第1の実施例によ
る半導体装置のはんだ溶融接続構造を示す断面図であ
る。本実施例について製造工程に従って説明していく。
基板2には、LSI1がフェースダウン又は、フェース
アップでボンディングされている。さらにその他の電子
部品(たとえば、チップ抵抗,チップコンデンサなど)
も搭載されている。これらの部品が搭載されている基板
2の裏面には導体パッド3が設けられていてその上に接
続用はんだボールが形成されている。さらに基板2の裏
面にはパッド7が設けられていてパッド7にはパッド3
上に形成したはんだボールと同じ高さになるだけのはん
だ量が供給されている。FIG. 1A is a sectional view showing a solder melting connection structure of a semiconductor device according to a first embodiment of the present invention. This embodiment will be described according to the manufacturing process.
The LSI 1 is bonded to the substrate 2 face down or face up. Still other electronic components (eg chip resistors, chip capacitors, etc.)
Is also installed. Conductor pads 3 are provided on the back surface of the substrate 2 on which these components are mounted, and solder balls for connection are formed thereon. Further, a pad 7 is provided on the back surface of the substrate 2, and the pad 7 is provided on the pad 7.
The amount of solder supplied is the same as the height of the solder balls formed above.
【0012】この基板2を基板6の所定の位置に搭載
し、リフロー加熱することによりパッド3上のはんだボ
ールが基板6上のパッド5に固着してはんだ接続部4と
なり、パッド7上のはんだが基板6上のパッド9に固着
して基板間隔制御用はんだ接続部8となり、図1(A)
に示す接続構造が形成される。ここで、パッド7及びパ
ッド9は、円形、四角形又は他の形状でも可能であるが
パッド9の面積をパッド7のものより大きくしてある。
パッド7上のはんだが加熱されてパッド9上に濡れて広
がると基板2、6を互いに引き寄せるためすべてのはん
だ接続部4が確実にパッド5に接続され作業工数を増や
すことなく高い信頼性のはんだ接続が得られ、半導体装
置の接続における歩留りの向上が図れた。The board 2 is mounted on the board 6 at a predetermined position, and by reflow heating, the solder ball on the pad 3 is fixed to the pad 5 on the board 6 to form the solder connection portion 4, and the solder on the pad 7 is soldered. Is fixed to the pad 9 on the substrate 6 to become the solder connection portion 8 for controlling the substrate gap, and FIG.
The connection structure shown in is formed. Here, the pad 7 and the pad 9 may have a circular shape, a square shape, or another shape, but the area of the pad 9 is larger than that of the pad 7.
When the solder on the pad 7 is heated and spreads wet and spreads on the pad 9, the substrates 2 and 6 are attracted to each other, so that all the solder connecting portions 4 are reliably connected to the pad 5 and a highly reliable solder can be obtained without increasing the number of working steps. The connection was obtained, and the yield in connecting the semiconductor devices was improved.
【0013】図1(B)は、本発明の第2の実施例の断
面図である。主な構成要素は第1の実施例と同じである
のでここでは説明を省略し相違点のみを延べる。基板6
上に所定の高さを有する絶縁性(例えばソルダーレジス
トなど)の突起15を予め形成しておく、基板2は実施
例1と同じ構成であり、この基板2を基板6の所定位置
に搭載しリフロー加熱する。このときパッド7上のはん
だにより基板2と基板6は互いに引き寄せられ基板2が
突起15に当接するまで両者の間隔が狭まり、最終的に
は両者間に突起15の高さの間隔が確保される。FIG. 1B is a sectional view of the second embodiment of the present invention. Since the main constituent elements are the same as those in the first embodiment, their explanations are omitted here and only the differences are extended. Board 6
An insulating (for example, solder resist) protrusion 15 having a predetermined height is previously formed on the substrate 2. The substrate 2 has the same configuration as that of the first embodiment. The substrate 2 is mounted on the substrate 6 at a predetermined position. Reflow heat. At this time, the board 2 and the board 6 are attracted to each other by the solder on the pad 7, and the distance between the boards 2 and 6 is narrowed until the board 2 comes into contact with the projections 15. Finally, the height interval of the projections 15 is secured between them. .
【0014】図2(A)は、本発明の第3の実施例の断
面図である。主な構成要素は第1の実施例と同じであり
異なる点は、第1の実施例ではパッド7,9及び基板間
隔制御用はんだ接続部8が1箇所のみに設けてあったの
が、この第3の実施例では複数箇所に配置され基板2,
6を接続している。これにより2枚の基板2,6は第1
の実施例より引き合う力が強くなり、反りの大きい基板
や、高さバラツキの大きいはんだボールに対応すること
が可能で、このような基板やはんだボールは安価に購入
できるので、なお一層の価格低減が図れる。FIG. 2A is a sectional view of the third embodiment of the present invention. The main constituent elements are the same as in the first embodiment, and the difference is that in the first embodiment, the pads 7 and 9 and the solder connection portion 8 for controlling the substrate spacing are provided only at one location. In the third embodiment, the substrates 2, which are arranged at a plurality of locations,
6 are connected. As a result, the two substrates 2 and 6 are
It is possible to deal with boards with large warpage and solder balls with large height variations compared to the above example, and such boards and solder balls can be purchased at low cost, further reducing the price. Can be achieved.
【0015】図2(B)は、本発明の第4の実施例であ
る。主な構成要素は第1の実施例から第3の実施例と共
通である。これらと異る点は、基板2の裏面にも表面同
様にLSI1などの電子部品を高密度に実装した点であ
る。FIG. 2B shows a fourth embodiment of the present invention. Main constituent elements are common to the first to third embodiments. The difference from these is that electronic components such as the LSI 1 are mounted on the back surface of the substrate 2 as well as the front surface at a high density.
【0016】[0016]
【発明の効果】以上説明したように本発明は、第1の基
板に設けられた第1の基板間隔制御用パッドと、第2の
基板に設けられ第1の基板間隔制御用パッドより広い面
積の第2の基板間隔制御用パッドとに基板間隔制御用は
んだ接続部を溶融接続することにより、はんだ溶融接合
時の濡れを利用し第1及び第2の基板が互いに引き合う
ようにして基板間隔を狭くすることにより、基板の反り
や、はんだボールの高さバラツキでのはんだボールとパ
ットとの未接触によって生じる接続不漁を低減し、作業
工数を増やすことなく高い信頼性のはんだ接続と歩留り
の向上を図れるという効果がある。さらに基板間隔制御
用はんだ接続部が第2のパッド上にフィレット状の接続
部を形成するため第1及び第2の基板間の接続強度が増
し、これによっても信頼性を高めることができる。As described above, the present invention has a larger area than the first substrate spacing control pad provided on the first substrate and the first substrate spacing control pad provided on the second substrate. By melt-connecting the solder connection portion for controlling the board space to the second board space control pad, the first board and the second board are attracted to each other by utilizing the wetting at the time of the solder fusion joining, and By making it narrower, we can reduce the connection failure caused by the warp of the board and the non-contact between the solder ball and the pad due to the variation of the height of the solder ball, and the highly reliable solder connection and the improvement of the yield without increasing the man-hours. There is an effect that can be achieved. Furthermore, since the board-spacing-controlling solder connection section forms a fillet-shaped connection section on the second pad, the connection strength between the first and second boards is increased, which also improves reliability.
【図1】分図(A)は本発明の第1の実施例の断面図で
あり、分図(B)は本発明の第2の実施例の断面図であ
る。FIG. 1A is a sectional view of a first embodiment of the present invention, and FIG. 1B is a sectional view of a second embodiment of the present invention.
【図2】分図(A)は本発明の第3の実施例の断面図で
あり、分図(B)は本発明の第4の実施例の断面図であ
る。FIG. 2A is a sectional view of a third embodiment of the present invention, and FIG. 2B is a sectional view of a fourth embodiment of the present invention.
【図3】分図(A)は従来の半導体装置の接続構造に用
いられるMCMの断面図であり、分図(B)は従来の半
導体装置の接続構造の断面図である。FIG. 3A is a sectional view of an MCM used in a conventional semiconductor device connection structure, and FIG. 3B is a sectional view of a conventional semiconductor device connection structure.
【図4】従来の他の半導体装置の実装構造の断面図であ
る。FIG. 4 is a cross-sectional view of another conventional semiconductor device mounting structure.
【図5】図4に示す従来の半導体装置の実装構造の製造
工程を示す断面図である。FIG. 5 is a cross-sectional view showing the manufacturing process of the conventional semiconductor device mounting structure shown in FIG. 4;
【図6】従来のさらに他の半導体装置の実装構造の断面
図である。FIG. 6 is a sectional view of a mounting structure of still another conventional semiconductor device.
1 LSI 2,6 基板 3,5,7,9,16 パッド 4,14 はんだ接続部 8 基板間隔制御用はんだ接続部 10 ツール 11 チップ 12 はんだボール 15 突起 17,18 はんだバンプ 1 LSI 2,6 Board 3,5,7,9,16 Pad 4,14 Solder Connection Section 8 Board Spacing Control Solder Connection Section 10 Tool 11 Chip 12 Solder Ball 15 Protrusion 17,18 Solder Bump
Claims (5)
の基板に設けられた第1のパッド及び前記第2の基板に
設けられた第2のパッドに溶融接続されたはんだボール
からなるはんだ接続部と、前記第1の基板に設けられた
第1の基板間隔制御用パッド及び前記第2の基板に設け
られ前記第1の基板間隔制御用パッドより面積が広い第
2の基板間隔制御用パッドに溶融接続された基板間隔制
御用はんだ接続部とを含むことを特徴とする半導体装置
の実装構造。1. A first substrate, a second substrate, and the first substrate.
A first pad provided on the first substrate and a first pad provided on the first substrate, and a solder connection portion including a solder ball melt-connected to a first pad provided on the second substrate and a second pad provided on the second substrate. A board space control pad, and a board space control solder connection portion fused to a second board space control pad provided on the second board and having a larger area than the first board space control pad. A semiconductor device mounting structure characterized by the above.
に設けた請求項1記載の半導体装置の実装構造。2. The mounting structure for a semiconductor device according to claim 1, wherein a protrusion with which the first substrate contacts is provided on the second substrate.
板間隔制御用パッド及び基板間隔制御用はんだ接続部を
複数組設けた請求項1又は2記載の半導体装置の実装構
造。3. The mounting structure for a semiconductor device according to claim 1, wherein a plurality of sets of a first board space control pad, a second board space control pad and a board space control solder connection portion are provided.
基板及び前記第2の基板の間の面に電気部品が搭載され
ている請求項1、2又は3記載の半導体装置の実装構
造。4. The semiconductor device according to claim 1, 2 or 3, wherein an electrical component is mounted on a surface of the first substrate or the second substrate between the first substrate and the second substrate. Mounting structure.
にはんだボールを形成し、前記第1の基板に設けられた
第1の基板間隔制御用パッドに前記はんだボールと同一
高さの基板間隔制御用はんだを供給し、前記第1のパッ
ドを第2の基板に設けられた第2のパッドに前記第1の
基板間隔制御用パッドを前記第2の基板に設けられ前記
第1の基板間隔制御用パッドより広い面積の第2の基板
間隔制御用パッドに位置を合わせて前記第1の基板を前
記第2の基板に搭載し、前記はんだボール及び前記基板
間隔制御用はんだそれぞれをリフロー加熱して対応する
前記第2のパッド及び前記第2の基板間隔制御用パッド
に溶融接続することを特徴とする半導体装置の実装方
法。5. A solder ball is formed on a first pad provided on a first substrate, and the same height as the solder ball is formed on a first substrate gap control pad provided on the first substrate. The substrate spacing control solder is supplied, the first pad is provided on the second substrate on the second pad, and the first substrate spacing control pad is provided on the second substrate. The first board is mounted on the second board in alignment with a second board spacing control pad having a larger area than that of the board spacing control pad, and the solder balls and the board spacing controlling solder are respectively attached. A method of mounting a semiconductor device, characterized by performing reflow heating and melting and connecting to the corresponding second pad and the second substrate gap control pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6176380A JP2540788B2 (en) | 1994-07-28 | 1994-07-28 | Semiconductor device mounting structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6176380A JP2540788B2 (en) | 1994-07-28 | 1994-07-28 | Semiconductor device mounting structure and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0845982A true JPH0845982A (en) | 1996-02-16 |
| JP2540788B2 JP2540788B2 (en) | 1996-10-09 |
Family
ID=16012632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6176380A Expired - Fee Related JP2540788B2 (en) | 1994-07-28 | 1994-07-28 | Semiconductor device mounting structure and method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2540788B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1056039A (en) * | 1996-08-08 | 1998-02-24 | Matsushita Electric Ind Co Ltd | Bonding method of work with bump |
| CN109411373A (en) * | 2018-09-18 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
| CN115334747A (en) * | 2021-05-11 | 2022-11-11 | 鸿富锦精密工业(武汉)有限公司 | Circuit board structure and manufacturing method thereof |
-
1994
- 1994-07-28 JP JP6176380A patent/JP2540788B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1056039A (en) * | 1996-08-08 | 1998-02-24 | Matsushita Electric Ind Co Ltd | Bonding method of work with bump |
| CN109411373A (en) * | 2018-09-18 | 2019-03-01 | 中国工程物理研究院电子工程研究所 | A method of realizing that multilager base plate is three-dimensional stacked using carrier supported |
| CN115334747A (en) * | 2021-05-11 | 2022-11-11 | 鸿富锦精密工业(武汉)有限公司 | Circuit board structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2540788B2 (en) | 1996-10-09 |
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