JPH0846142A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device in which the characteristics can be arranged for each MOSFET constituting each protective circuit. CONSTITUTION:An SOI layer is formed on a P-type single crystal silicon substrate 13 through a silicon oxide and an inner circuit is formed therein. A protective circuit is provided between the inner circuit and each input pad 7 where the protective circuit comprises a protective resistor and an N-channel MOSFET formed on the P-type single crystal silicon substrate 13. A P<+> impurity diffusion region 26 is extended around the N-channel MOSFET forming region of each protective circuit in the P-type single crystal silicon substrate 13. The P<+> impurity diffusion region 26 is connected with a metal wiring formed thereon and the metal wiring 28 is connected with a bonding pad 7a for ground terminal thus setting the impurity diffusion region 26 at the ground potential.

Description

Detailed Description of the Invention

[0001]

This invention has an SOI structure,
The present invention also relates to a semiconductor integrated circuit device including a protection circuit for protecting the semiconductor integrated circuit from static electricity and the like.

[0002]

2. Description of the Related Art Conventionally, the SOI technology is one in which a semiconductor layer is formed on an insulator layer formed on a semiconductor substrate, and a semiconductor integrated circuit element is formed on the semiconductor layer. Further, a protection circuit is provided to protect the semiconductor integrated circuit element having the SOI structure from a large current generated by static electricity or the like. This protection circuit has a protection circuit element such as a transistor for releasing a large current, and the element has been formed in a semiconductor layer on an insulator layer. However, the semiconductor integrated circuit element is easily broken because the path for releasing a large current can be formed only in the lateral direction. for that reason,
The protection circuit element has come to be formed on a semiconductor substrate in order to release a large current generated by static electricity or the like. One example thereof is shown in Japanese Patent Laid-Open No. 345064/1992. As shown in FIG. 6, a protection circuit 33 is provided between an input bonding pad 31 and an internal circuit 32. The protection circuit 33 includes a protection resistor 34 and a protection MO.
It consists of SFET35. Also, this protection MOSFET
As shown in FIG. 7, reference numeral 35 denotes a semiconductor substrate 36 having source / drain regions 37 and a semiconductor layer 38 forming a gate electrode.

This protection circuit 33, as shown in FIG.
It is provided for each of the plurality of bonding pads 31. Further, as shown in FIG. 8, the substrate potential pad 3 for the protection MOSFET 35 formed on the semiconductor substrate 36.
9 is formed at a specific place on the semiconductor substrate 36 (chip), the pad 39 and the semiconductor substrate 36 are electrically connected immediately below the substrate potential pad 39, and the semiconductor substrate 36 is set to the ground potential. It

[0004]

However, the protective MO
As for the potential of the semiconductor substrate region immediately below the source / drain of the SFET 35, since the distance between the protection MOSFET 35 and the substrate potential pad 39 is different for each protection MOSFET 35, as shown in FIG.
A voltage drop occurs every 5 times by the substrate resistance (R1, R2, R3, ...). As a result, since the substrate potential differs for each protection MOSFET 35, the amount of current flowing through the protection MOSFET 35 also differs, resulting in a problem that the breakdown withstand value also differs.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device in which the characteristics of each MOSFET forming each protection circuit can be made uniform.

[0006]

According to a first aspect of the present invention, a semiconductor integrated circuit formed in a semiconductor layer on a semiconductor substrate with an insulator layer interposed therebetween, and the semiconductor integrated circuit and the outside are electrically connected to each other. A semiconductor integrated circuit device comprising: a plurality of external connection terminals for connection; and a protection circuit that is provided between the semiconductor integrated circuit and each external connection terminal and that includes a MOSFET formed on the semiconductor substrate. The gist is a semiconductor integrated circuit device in which an impurity diffusion region is extended to a position close to the MOSFET of each protection circuit on the semiconductor substrate and the impurity diffusion region is set to a predetermined potential.

According to a second aspect of the present invention, the impurity diffusion region in the semiconductor integrated circuit device according to the first aspect is
The gist of the invention is a semiconductor integrated circuit device extending around a MOSFET formation region of each protection circuit on a semiconductor substrate.

According to a third aspect of the present invention, the impurity diffusion region in the semiconductor integrated circuit device according to the first aspect is
The gist of the invention is a semiconductor integrated circuit device extended to the outer peripheral portion of the semiconductor substrate.

[0009]

According to the first aspect of the invention, the impurity diffusion region is extended to a position close to the MOSFET of each protection circuit on the semiconductor substrate, and the impurity diffusion region is set to a predetermined potential. As a result, the distance between each MOSFET and the impurity diffusion region (that is, the substrate potential wiring) can be equalized, and the potential of the semiconductor substrate region directly under the source / drain of each MOSFET can also be equalized. Therefore, each MOS
The characteristics such as the breakdown withstand value of the FET are also equalized.

According to the second aspect of the present invention, the impurity diffusion region is extended around the MOSFET formation region of each protection circuit on the semiconductor substrate, and the impurity diffusion region is set to a predetermined potential. As a result, the distance between each MOSFET and the impurity diffusion region (that is, the substrate potential wiring) can be equalized, and the potential of the semiconductor substrate region directly under the source / drain of each MOSFET can also be equalized. Therefore, each M
The characteristics such as the breakdown withstand value of the OSFET are also equalized.

According to the invention of claim 3, claim 1
In addition to the effect of the invention described in (1), the impurity diffusion region is originally
The impurity diffusion region is easily arranged by being extended to the outer peripheral portion of the semiconductor substrate which is an unused portion.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows an electrical configuration of the semiconductor integrated circuit device.

An inverter 2 is used at each input stage of an internal circuit 1 as a semiconductor integrated circuit in a semiconductor integrated circuit device. Each inverter 2 is
P-channel MOSFET 3 and N-channel MOSFET 4
Consists of In addition, the P channel MOSFE of the inverter 2
A power supply terminal (V _DD ) 5 is connected to the source electrode of T3,
A ground terminal (V _SS ) 6 is connected to the source electrode of the N-channel MOSFET 4. As the power supply voltage V _DD , for example, 3 V is applied to the power supply terminal 5. A protection circuit 8 is arranged between the input terminal of the inverter 2 and the input pad (bonding pad) 7 which is an external connection terminal. The protection circuit 8 has a protection resistor 9
And an N-channel MOSFET 10. That is, the protection resistor 9 is arranged in the middle of the connection line 11 connecting the input pad 7 and the input terminal of the inverter 2. In addition, N is provided between the connecting wire 11 and the ground terminal (V _SS ) 12.
The channel MOSFET 10 is arranged and the N channel MO
The gate terminal of the SFET 10 is connected to the connection line 11.

Various circuits other than the inverter can be used as the input stage of the internal circuit (semiconductor integrated circuit) 1, and the internal circuit (semiconductor integrated circuit) 1 does not include various circuits (elements). Needless to say.

FIG. 1 shows a plan view of a semiconductor integrated circuit device (chip). 2 shows the AA cross section of FIG. 1, FIG. 3 shows the BB cross section of FIG. 1, and FIG. 4 shows the CC cross section of FIG. In FIG. 5, the protective resistor 9 and the like shown in FIG. 5 are omitted.

As shown in FIG. 1, the central portion of the semiconductor integrated circuit device (chip) is the internal circuit 1 and each protection circuit 8.
Forming region Z1 of the N-channel MOSFET 10 of
The above-mentioned input pads (bonding pads) 7 are arranged on the periphery thereof. The pads 7 include grounding terminal bonding pads (substrate potential pads) 7a.

FIG. 4 shows only one of the plurality of input pads (bonding pads) 7, and the other input pads (bonding pads) 7 have the same structure.

As shown in FIG. 4, P as a semiconductor substrate
A silicon oxide film 14 as an insulator layer is formed on the type single crystal silicon substrate 13, and a single crystal silicon layer (hereinafter referred to as SOI) as a semiconductor layer is formed on the silicon oxide film 14.
15, 16 and 17 are arranged. SOI
A polysilicon gate electrode 19 is formed on the layer 15 through a gate oxide film 18 to form an N-channel MOSFET 4. The SOI layer 16 has a gate oxide film 20.
A polysilicon gate electrode 21 is formed via the above to form a P-channel MOSFET 3. Both MOS
The above-mentioned inverter 2 is composed of the FETs 3 and 4.

The P-type single crystal silicon substrate 13 on both sides of the SOI layer 17 has N-type source regions 22 and N-type.
A mold drain region 23 is formed. And SO
The I layer 17 is used as a gate electrode, the silicon oxide film 14 is used as a gate oxide film, and the P-type single crystal silicon substrate 13 is used as a source.
As the drain region, the N-channel MOSFET 10 forming the protection circuit 8 described above is formed. Thus, the N-channel MOSFET 10 is formed on the P-type single crystal silicon substrate 13.

The silicon oxide film 14 including the SOI layers 15, 16 and 17 is covered with an interlayer insulating film 24 and a wiring 25 made of aluminum or the like is provided. Further, as shown in FIGS. 1 and 2, on the interlayer insulating film 24,
A plurality of input pads 7 made of aluminum or the like are arranged.

Further, as shown in FIG. 1, the outer peripheral portion of the P-type single crystal silicon substrate 13 (chip), that is, each protection circuit 8 is formed.
In the surface portion of the P-type single crystal silicon substrate 13 around the formation region Z1 of the N-channel MOSFET 10, the P ⁺ impurity diffusion region 26 for the substrate potential is formed in a ring shape. The P ⁺ impurity diffusion region 26 is formed by implanting boron (B) which is a P-type impurity. The P ⁺ impurity diffusion region 26 is a P single crystal silicon substrate 13
Has a predetermined depth from the surface. Further, a contact hole 27 is provided in the silicon oxide film 14, the SOI layer, and the interlayer insulating film 24 over the P ⁺ impurity diffusion region 26 in all areas, and a metal wiring 28 made of aluminum is provided through the contact hole 27. ing. The metal wiring 28 has substantially the same size as the P ⁺ impurity diffusion region 26. The metal wiring 28 does not necessarily have to have the same size as the P ⁺ impurity diffusion region 26.

In this way, the P ⁺ impurity diffusion region 26 becomes P
The single crystal silicon substrate 13 is extended to a position close to the N-channel MOSFET 10 of each protection circuit 8. More specifically, the P ⁺ impurity diffusion region 26 is arranged so as to be substantially equidistant from the N-channel MOSFET 10 of each protection circuit 8.

The metal wiring 28 is connected to the grounding terminal bonding pad 7a via the connection wiring 28a on the interlayer insulating film 24.
Connected with. In this way, the P ⁺ impurity diffusion region 26 is connected to the ground terminal bonding pad 7a through the metal wiring 28, and the ground potential V _ss is applied as the substrate potential.

Further, the pad 7 is formed on the interlayer insulating film 24.
It is covered with the passivation film 30 except for (including 7a). Next, the operation of the semiconductor integrated circuit device thus configured will be described.

When a high voltage such as static electricity or surge voltage is applied to the input pad 7, the N-channel MOSF of the protection circuit 8 is
A current flows between the source / drain of the ET 10, a large current escapes to the ground terminal 12, and the internal circuit 1 is protected.

[0026] Further, P ⁺ impurity diffusion region 26 around the forming region Z1 of the N-channel MOSFET10 of the protection circuit 8 is extended in the P-type single crystal silicon substrate 13, a ground potential V the P ⁺ impurity diffusion region 26 _{Since SS} is used, each N-channel MOSFET 10 and P ⁺ impurity diffusion region 26
(Ie, the wiring for the substrate potential) becomes even,
Substrate region potentials directly under the source and drain of each N-channel MOSFET 10 become equal. That is, in the conventional device shown in FIG. 8, the substrate potential pad 39 is formed at a specific place on the semiconductor substrate 36 (chip), and the protection MOSFE is formed.
Regarding the potential of the substrate region immediately below the source / drain of T35, the distance between the protective MOSFET 35 and the substrate potential pad 39 is different for each protective MOSFET 35.
As shown in FIG. 9, a voltage drop occurs for each protection MOSFET 35 by the amount of the substrate resistance (R1, R2, R3 ...). However, in this device, as shown in FIG.
Since the substantial distance between the channel MOSFET 10 and the grounding terminal bonding pad (substrate potential pad) 7a is the same in each N-channel MOSFET 10, a voltage drop corresponding to the substrate resistance of each N-channel MOSFET 10 does not occur. Therefore, each N-channel MOSFET
Substrate region potentials directly under the source / drain of 10 are equalized, and the breakdown withstand values of the N-channel MOSFETs 10 are also equalized.

As described above, in this embodiment, the P-type single crystal silicon is used.
N-channel MOS of each protection circuit 8 on the control board 13
P to the position close to FET10⁺Impurity diffusion region 26
And extend this P⁺The impurity diffusion region 26 is set to the ground potential V_SS
(Predetermined potential). More specifically, N of each protection circuit 8
P around the formation region Z1 of the channel MOSFET 10 ⁺
The impurity diffusion region 26 is extended. As a result, each N channel
Le MOSFET 10 and P⁺Impurity diffusion region 26 (that is,
(The wiring for the substrate potential) is made uniform, and each N
P just under the source / drain of the channel MOSFET 10
The electric potential of the region of the single crystal silicon substrate 13 is equalized.
It Therefore, the breakdown resistance of each N-channel MOSFET 10
The values are also equalized. In this way, each protection circuit 8 is constructed.
The characteristics of each N-channel MOSFET 10 to be formed should be the same.
And are possible.

In addition, the P ⁺ impurity diffusion region 26 is formed as a P type single crystal silicon substrate 13 (chip) which is originally an unused portion.
Since it is extended to the outer peripheral portion, the P ⁺ impurity diffusion region 26 can be easily arranged. In addition, P ⁺ impurity diffusion region 2
The metal wiring 28 that contacts with the P-type single crystal silicon substrate 1
Since it is extended to the outer peripheral portion of the chip 3 (chip), the area of the contact hole 27 can be secured without hindering the internal circuit 1 (semiconductor integrated circuit).

The present invention is not limited to the above embodiment. For example, in the above embodiment, a P type semiconductor substrate was used as the semiconductor substrate and a P type impurity diffusion region was used. Use the N type as the substrate,
The impurity diffusion region may be formed by implanting phosphorus (P) which is an N-type impurity.

Further, the P ⁺ impurity diffusion region 26 does not necessarily have to surround the formation region Z1 of the N-channel MOSFET 10 (P
It does not need to be provided in a ring shape on the outer peripheral portion of the type single crystal silicon substrate 13 and may be extended to a position close to each N-channel MOSFET 10.

[0031]

As described in detail above, according to the inventions of claims 1 and 2, each MOSFET constituting each protection circuit
It has the excellent effect that the characteristics of can be made uniform.

According to the invention of claim 3, in addition to the effect of the invention of claim 1, the impurity diffusion region can be easily arranged.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a sectional view taken along line CC of FIG.

FIG. 5 is an electrical configuration diagram of a semiconductor integrated circuit device of an example.

FIG. 6 is an electrical configuration diagram of a conventional semiconductor integrated circuit device.

FIG. 7 is a cross-sectional view of a conventional semiconductor integrated circuit device.

FIG. 8 is a plan view of a conventional semiconductor integrated circuit device.

FIG. 9 is an electrical configuration diagram of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Internal circuit as semiconductor integrated circuit, 7 ... Input pad as external connection terminal, 8 ... Protection circuit, 10 ... N-channel MOSFET, 13 ... P-type single crystal silicon substrate as semiconductor substrate, 14 ... As insulator layer , 16 ... SOI layer as semiconductor layer, 26 ... P
⁺ Impurity diffusion region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/092 29/786 9056-4M H01L 29/78 623 A

Claims (3)

[Claims] 1. A semiconductor integrated circuit formed in a semiconductor layer on a semiconductor substrate via an insulating layer, a plurality of external connection terminals for electrically connecting the semiconductor integrated circuit and the outside, and the semiconductor. A semiconductor integrated circuit device provided with an integrated circuit and a protection circuit including a MOSFET formed on the semiconductor substrate, the protection circuit being provided between the external connection terminals, and the MOSFET of each protection circuit on the semiconductor substrate.
A semiconductor integrated circuit device characterized in that an impurity diffusion region is extended to a position close to, and the impurity diffusion region is set to a predetermined potential. 2. The semiconductor integrated circuit device according to claim 1, wherein the impurity diffusion region is extended around a MOSFET formation region of each protection circuit in the semiconductor substrate. . 3. The semiconductor integrated circuit device according to claim 1, wherein the impurity diffusion region is extended to an outer peripheral portion of the semiconductor substrate.