JPH08503813A - 集積回路装置を製造するための方法及び装置 - Google Patents
集積回路装置を製造するための方法及び装置Info
- Publication number
- JPH08503813A JPH08503813A JP6507721A JP50772194A JPH08503813A JP H08503813 A JPH08503813 A JP H08503813A JP 6507721 A JP6507721 A JP 6507721A JP 50772194 A JP50772194 A JP 50772194A JP H08503813 A JPH08503813 A JP H08503813A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- manufacturing
- wafer
- slicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/834—Interconnections on sidewalls of chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dicing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.複数のパッドを各々有する複数の集積回路を第1及び第2の平らな表面を持 つウェーハ上に製造する工程と、 前記ウェーハの前記表面の両方に保護材料層を設けるウエーハワイズ取り付け 工程と、 その後、前記ウェーハ及びこれに取り付けられた前記保護材料をスライスして 複数のパッケージ前の集積回路装置を形成するスライス工程とを有する集積回路 装置の製造方法。 2.前記スライス工程は、前記複数のパッドの断面を露呈する、請求項1に記載 の集積回路装置の製造方法。 3.前記スライス工程は、一対の隣接した集積回路と関連したパッドを切断し、 これによって、前記対をなした隣接した集積回路の両方について電気接点領域を 同時に形成する、請求項2に記載の集積回路装置の製造方法。 4.多数のパッドを各々有する複数の集積回路を、ウェーハ上に製造する工程と 、 その後、前記ウエーハをスライスして複数の集積回路要素を形成するスライス 工程とを有し、前記スライス工程により前記多数のパッドの断面を露呈する、集 積回路装置の製造方法。 5.前記スライス工程は、一対の隣接した集積回路の一方と導通したパッド及び 一対の隣接した集積回路の他方と導通したパッドを含む複数のパッドを切断し、 これによって前記対をなした隣接した集積回路の両方についての電気接点領域を 形成する、請求項4に記載の集積回路装置の製造方法。 6.前記集積回路のスライス縁部上に導電層を設け、前記多数のパッドのうちの 別の一つのパッドと導通した前記導電層の部分を電気的に分離する工程を更に有 する、請求項1乃至5のいずれかに記載の集積回路装置の製造方法。 7.導電層を設ける前記工程の前に、前記集積回路の前記スライス縁部に沿って 電気絶縁層を設ける、請求項6に記載の集積回路装置の製造方法。 8.導電層を設ける前記工程は、導電コーティングを前記集積回路の縁部以外の 部分にも形成する工程を含む、請求項6に記載の集積回路装置の製造方法。 9.前記スライス工程は、前記ウェーハに刻み目線を付ける工程、及びこの工程 の後にウェーハにエッチングを施す工程を含む、請求項1乃至8のいずれかに記 載の集積回路装置の製造方法。 10.多数の露呈されたパッド縁部を各々有する複数の集積回路を、製造する工程 と、 前記複数の集積回路と回路基板とを前記多数の露呈されたパッド縁部を介して 電気的に接続する工程とを有する集積回路装置の製造方法。 11.前記スライス工程は、結果的に得られた集積回路のスライス縁部のところで シリコン基材が露呈されない位置で行われる、請求項1乃至9のいずれかに記載 の集積回路装置の製造方法。 12.前記スライス工程の前に、前記集積回路の平らな表面を保護絶縁層で取り囲 み、縁部をエポキシで取り囲む、請求項1乃至9及び11のいずれかに記載の集 積回路装置の製造方法。 13.前記集積回路装置の少なくとも一つの平らな外面にヒートシンクへの熱連結 部を形成する請求項1乃至12のいずれかに記載の集積回路装置の製造方法。 14.前記集積回路装置に接地平面を一体に形成する工程を更に有する、請求項1 乃至13のいずれかに記載の集積回路装置の製造方法。 15.前記集積回路を支持する複数のウェーハを積み重ねた構成で互いに接合し、 多層集積回路装置を構成する、請求項1乃至14のうちのいずれかに記載の集積 回路装置の製造方法。 16.前記集積回路装置をその縁部に沿って取り付け要素に取り付ける工程を更に 有する、請求項1乃至15のいずれかに記載の集積回路装置の製造方法。 17.前記保護層は、消去可能なプログラム可能読み取り専用記憶装置の消去に使 用される放射線に対して透明である、請求項1乃至16のいずれかに記載の集積 回路装置の製造方法。 18.露呈されたパッド縁部を有する前記集積回路装置の電気接点を耐蝕処理する 工程を更に有する、請求項1乃至17のいずれかに記載の集積回路装置の製造方 法。 19.機械的に保護され且つ電気的に絶縁され、電気パッドの複数の露呈断面をパ ッ ケージの縁部で露呈させてなるパッケージの内部に、半導体要素を形成する工程 と、 前記露呈断面と外部回路との間を電気的に接続する工程とを有する半導体装置 の製造方法。 20.前記半導体要素形成工程は、保護層をウェーハ上に設けるウェーハワイズ取 り付け工程と、この工程に続いて、前記ウェーハを個々のダイにダイシングする 工程とを含む、請求項19に記載の半導体装置の製造方法。 21.多数のパッドを各々有する複数の集積回路を平らな両面を持つウェーハ上に 製造する装置と、 前記ウェーハの前記平らな両面に保護パッケージング材料層を設けるウェーハ ワイズ取り付ける装置と、 その後、前記ウェーハ及びこれに取り付けられた前記保護材料をスライスして 複数のパッケージ前の集積回路装置を形成するスライス装置とを有する集積回路 製造装置。 22.前記スライス装置は、前記多数のパッドの断面を露呈する、請求項21に記 載の集積回路製造装置。 23.前記スライス装置は、隣接した集積回路を導通するパッドを切断すると同時 に前記隣接した集積回路への電気接点領域を構成する、請求項22に記載の集積 回路製造装置。 24.多数のパッドを各々有する複数の集積回路を、ウェーハ上に製造する装置と 、 その後、前記ウェーハをスライスして複数の集積回路装置を形成するスライス 装置とを有し、前記スライス装置は、前記多数のパッドの断面を露呈するように 作動する集積回路装置製造装置。 25.前記スライス装置は、一対の隣接した集積回路の一方と導通したパッド及び 対をなした隣接した集積回路の他方と導通したパッドを含む複数のパッドを切断 して前記対をなした隣接した集積回路の両方の電気接点領域を構成する、請求項 24に記載の集積回路装置製造装置。 26.前記切断したウェーハのスライス縁部上に導電層を付け、前記多数のパッド のうちの別のパッドと導通した前記導電層の部分を電気的に分離するための装置 を更に有する請求項21乃至25のいずれかに記載の集積回路装置製造装置。 27.前記切断したウェーハの前記スライス縁部に沿って、前記導電層を設ける前 に、電気絶縁層を形成する、請求項26に記載の集積回路装置製造装置。 28.前記導電層は、前記集積回路の前記縁部以外に付けた導電コーティングから なる、請求項26に記載の集積回路装置製造装置。 29.前記スライス装置は、前記ウェーハに刻み目線を付けるための装置及びこれ に続いて前記ウェーハをエッチングするための装置を含む、請求項21乃至28 のいずれかに記載の集積回路装置製造装置。 30.多数の露呈したパッド縁部を各々有する複数の集積回路を製造するための手 段と、 前記複数の集積回路と回路基板との間を前記多数の露呈したパッド縁部を介し て電気的に接続するための手段とを有する集積回路製造装置。 31.前記スライス装置は、結果的に得られた集積回路のスライス縁部のところで シリコン基板が露呈されない位置で作動される、請求項21乃至29のいずれか に記載の集積回路製造装置。 32.前記スライス工程の前に、前記集積回路の平らな表面を保護絶縁層で取り囲 み、縁部をエポキシで取り囲む、請求項21乃至29及び31のいずれかに記載 の集積回路製造装置。 33.前記集積回路装置の少なくとも一つの平らな外面にヒートシンクへの熱連結 部を形成する、請求項21乃至32のいずれかに記載の集積回路製造装置。 34.前記集積回路装置と一体に形成された接地平面を更に有する、請求項21乃 至33のいずれかに記載の集積回路製造装置。 35.前記集積回路を支持する複数のウェーハを積み重ねた構成で互いに接合し、 多層集積回路装置を構成する、請求項21乃至34のいずれかに記載の集積回路 製造装置。 36.前記集積回路装置をそれらの集積回路装置の縁部に沿って取り付け要素に取 り付けるための装置を更に有する、請求項21乃至35のいずれかに記載の集積 回路製造装置。 37.前記保護層は、消去可能なプログラム可能読み取り専用記憶装置の消去に使 用される放射線に対して透明である、請求項21乃至36のいずれかに記載の集 積回路製造装置。 38.前記集積回路装置の電気接点及びパッド縁部に耐蝕処理保護のための処理を 施す、請求項21乃至37のいずれかに記載の集積回路製造装置。 39.機械的に保護され且つ電気的に絶縁され、電気パッドの複数の露呈された断 面をパッケージの縁部で露呈させてなるパッケージ内部に、半導体要素を形成す る手段と、 前記露呈された断面と外部回路との間を電気的に接続するための装置とを有す る半導体装置製造装置。 40.半導体要素を形成するための前記装置は、保護層をウェーハ上に設けるウェ ーハワイズ取り付け装置と、これに続いて、前記ウェーハを個々のダイにダイシ ングするための装置とを含む、請求項39に記載の半導体装置製造装置。 41.請求項1乃至20のうちのいずれか一項に記載の方法に従って製造された集 積回路装置。 42.請求項21乃至40のうちのいずれか一項に記載の装置を使用して製造され た集積回路装置。 43.電気絶縁性であり且つ機械的な保護を与える材料で形成された上面及び下面 と、導電パッドの露呈断面を持つ電気絶縁性の縁部表面とを有する集積回路アッ センブリからなる集積回路装置。 44.前記集積回路アッセンブリは、積み重ねた関係で互いに結合された複数のシ リコンチップからなる、請求項43に記載の集積回路装置。 45.前記複数のシリコンチップは、前記集積回路アッセンブリ内で互いに絶縁さ れている、請求項44に記載の集積回路装置。 46.前記集積回路装置の外面に形成され且つ導電パッドの前記露呈断面と電気的 に導通した導電ストリップを更に有する、請求項41乃至45のうちのいずれか 一項に記載の集積回路装置。 47.前記導電ストリップは、前記集積回路装置の前記縁部に沿って延びている、 請求項46に記載の集積回路装置。 48.前記導電ストリップは、前記集積回路装置の平らな表面にまで延びている、 請求項47に記載の集積回路装置。 49.前記導電ストリップは、複数のダイの導電パッドの前記露呈断面を相互接続 するため、前記集積回路装置の前記外面上に形成されており、これによって、そ の間に電気的相互接続を構成する、請求項41乃至48のうちのいずれか一項に 記載の集積回路装置。 50.前記集積回路装置は、互いに絶縁された複数のシリコン部分を有する、請求 項41乃至49のうちのいずれか一項に記載の集積回路装置。 51.前記装置の前記外面から機械的に及び電気的に絶縁された少なくとも一つの シリコン要素を有する、請求項41乃至50のうちのいずれか一項に記載の集積 回路装置。 52.前記装置の平らな外面に設けられたヒートシンクへの、一体に形成された熱 連結部を更に有する、請求項41乃至51のうちのいずれか一項に記載の集積回 路装置。 53.一体に形成された接地平面を更に有する、請求項41乃至52のうちのいず れか一項に記載の集積回路装置。 54.複数の縁部の導電パッドの前記露呈断面を相互接続するため、導電ストリッ プが前記集積回路装置の前記外面に形成されている、請求項41乃至53のうち のいずれか一項に記載の集積回路装置。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP1992/002134 WO1994007267A1 (en) | 1992-09-14 | 1992-09-14 | Methods and apparatus for producing integrated circuit devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08503813A true JPH08503813A (ja) | 1996-04-23 |
| JP3621093B2 JP3621093B2 (ja) | 2005-02-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50772194A Expired - Lifetime JP3621093B2 (ja) | 1992-09-14 | 1992-09-14 | 集積回路装置を製造するための方法及び装置 |
Country Status (23)
| Country | Link |
|---|---|
| US (2) | US5455455A (ja) |
| EP (1) | EP0660967B1 (ja) |
| JP (1) | JP3621093B2 (ja) |
| KR (1) | KR100310220B1 (ja) |
| AT (1) | ATE200593T1 (ja) |
| AU (1) | AU2554192A (ja) |
| BG (1) | BG99554A (ja) |
| CA (1) | CA2144323C (ja) |
| DE (1) | DE69231785T2 (ja) |
| DK (1) | DK0660967T3 (ja) |
| EC (1) | ECSP930975A (ja) |
| FI (1) | FI951142A7 (ja) |
| GT (1) | GT199300053A (ja) |
| HU (1) | HUT73312A (ja) |
| IL (1) | IL106710A (ja) |
| MA (1) | MA25277A1 (ja) |
| MX (1) | MX9305603A (ja) |
| MY (1) | MY129454A (ja) |
| NO (1) | NO950960L (ja) |
| PL (1) | PL169823B1 (ja) |
| PT (1) | PT101354A (ja) |
| WO (1) | WO1994007267A1 (ja) |
| ZA (1) | ZA936039B (ja) |
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| IL108359A (en) * | 1994-01-17 | 2001-04-30 | Shellcase Ltd | Method and apparatus for producing integrated circuit devices |
| US6117707A (en) * | 1994-07-13 | 2000-09-12 | Shellcase Ltd. | Methods of producing integrated circuit devices |
| US5851845A (en) * | 1995-12-18 | 1998-12-22 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
| US5637916A (en) * | 1996-02-02 | 1997-06-10 | National Semiconductor Corporation | Carrier based IC packaging arrangement |
| US5904546A (en) * | 1996-02-12 | 1999-05-18 | Micron Technology, Inc. | Method and apparatus for dicing semiconductor wafers |
| US5952725A (en) | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
| US5682065A (en) | 1996-03-12 | 1997-10-28 | Micron Technology, Inc. | Hermetic chip and method of manufacture |
| FR2748350B1 (fr) * | 1996-05-06 | 2000-07-13 | Solaic Sa | Composant electronique sous forme de circuit integre pour insertion a chaud dans un substrat et procedes pour sa fabrication |
| US6784023B2 (en) * | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
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| US5292686A (en) * | 1991-08-21 | 1994-03-08 | Triquint Semiconductor, Inc. | Method of forming substrate vias in a GaAs wafer |
| US5266833A (en) * | 1992-03-30 | 1993-11-30 | Capps David F | Integrated circuit bus structure |
| DK0660967T3 (da) * | 1992-09-14 | 2001-08-13 | Shellcase Ltd | Fremgangsmåde til fremstilling af integrerede kredsløbsanordninger |
| US5376235A (en) * | 1993-07-15 | 1994-12-27 | Micron Semiconductor, Inc. | Method to eliminate corrosion in conductive elements |
-
1992
- 1992-09-14 DK DK92919323T patent/DK0660967T3/da active
- 1992-09-14 AU AU25541/92A patent/AU2554192A/en not_active Abandoned
- 1992-09-14 FI FI951142A patent/FI951142A7/fi not_active Application Discontinuation
- 1992-09-14 CA CA002144323A patent/CA2144323C/en not_active Expired - Fee Related
- 1992-09-14 KR KR1019950700986A patent/KR100310220B1/ko not_active Expired - Lifetime
- 1992-09-14 US US07/962,222 patent/US5455455A/en not_active Expired - Lifetime
- 1992-09-14 MX MX9305603A patent/MX9305603A/es not_active IP Right Cessation
- 1992-09-14 WO PCT/EP1992/002134 patent/WO1994007267A1/en not_active Ceased
- 1992-09-14 EP EP92919323A patent/EP0660967B1/en not_active Expired - Lifetime
- 1992-09-14 HU HU9500783A patent/HUT73312A/hu unknown
- 1992-09-14 JP JP50772194A patent/JP3621093B2/ja not_active Expired - Lifetime
- 1992-09-14 DE DE69231785T patent/DE69231785T2/de not_active Expired - Fee Related
- 1992-09-14 PL PL92308140A patent/PL169823B1/pl unknown
- 1992-09-14 AT AT92919323T patent/ATE200593T1/de active
-
1993
- 1993-08-16 IL IL10671093A patent/IL106710A/xx not_active IP Right Cessation
- 1993-08-18 ZA ZA936039A patent/ZA936039B/xx unknown
- 1993-08-20 EC EC1993000975A patent/ECSP930975A/es unknown
- 1993-09-02 PT PT101354A patent/PT101354A/pt not_active Application Discontinuation
- 1993-09-09 GT GT199300053A patent/GT199300053A/es unknown
- 1993-09-13 MA MA23286A patent/MA25277A1/fr unknown
- 1993-09-14 MY MYPI93001866A patent/MY129454A/en unknown
-
1994
- 1994-07-13 US US08/274,251 patent/US5547906A/en not_active Expired - Lifetime
-
1995
- 1995-03-13 NO NO950960A patent/NO950960L/no unknown
- 1995-04-10 BG BG99554A patent/BG99554A/xx unknown
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010502006A (ja) * | 2006-08-22 | 2010-01-21 | トロワデー、プリュ | 3次元電子モジュールの集合的製作方法 |
| US9082438B2 (en) | 2008-12-02 | 2015-07-14 | Panasonic Corporation | Three-dimensional structure for wiring formation |
| JPWO2010087336A1 (ja) * | 2009-01-27 | 2012-08-02 | パナソニック株式会社 | 半導体チップの実装方法、該方法を用いて得られた半導体装置及び半導体チップの接続方法、並びに、表面に配線が設けられた立体構造物及びその製法 |
| US8759148B2 (en) | 2009-01-27 | 2014-06-24 | Panasonic Corporation | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same |
| US8901728B2 (en) | 2009-01-27 | 2014-12-02 | Panasonic Corporation | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same |
| US9070393B2 (en) | 2009-01-27 | 2015-06-30 | Panasonic Corporation | Three-dimensional structure in which wiring is provided on its surface |
| US9795033B2 (en) | 2009-01-27 | 2017-10-17 | Panasonic Corporation | Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same |
| US9478503B2 (en) | 2012-03-30 | 2016-10-25 | Tohoku University | Integrated device |
| CN105489510A (zh) * | 2014-10-02 | 2016-04-13 | 住友电木株式会社 | 半导体装置的制造方法和半导体装置 |
| JP2016076694A (ja) * | 2014-10-02 | 2016-05-12 | 住友ベークライト株式会社 | 半導体装置の製造方法および半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| NO950960L (no) | 1995-05-10 |
| DE69231785D1 (de) | 2001-05-17 |
| IL106710A (en) | 1997-01-10 |
| DK0660967T3 (da) | 2001-08-13 |
| PL308140A1 (en) | 1995-07-24 |
| GT199300053A (es) | 1995-03-03 |
| BG99554A (bg) | 1996-03-29 |
| HU9500783D0 (en) | 1995-05-29 |
| PT101354A (pt) | 1994-07-29 |
| EP0660967A1 (en) | 1995-07-05 |
| NO950960D0 (no) | 1995-03-13 |
| CA2144323C (en) | 2005-06-28 |
| CA2144323A1 (en) | 1994-03-31 |
| FI951142A0 (fi) | 1995-03-10 |
| ECSP930975A (es) | 1994-04-20 |
| ATE200593T1 (de) | 2001-04-15 |
| MA25277A1 (fr) | 2001-12-31 |
| WO1994007267A1 (en) | 1994-03-31 |
| JP3621093B2 (ja) | 2005-02-16 |
| FI951142L (fi) | 1995-05-10 |
| ZA936039B (en) | 1994-03-10 |
| EP0660967B1 (en) | 2001-04-11 |
| US5455455A (en) | 1995-10-03 |
| FI951142A7 (fi) | 1995-05-10 |
| DE69231785T2 (de) | 2001-11-15 |
| IL106710A0 (en) | 1993-12-08 |
| KR100310220B1 (ko) | 2001-12-17 |
| HUT73312A (en) | 1996-07-29 |
| AU2554192A (en) | 1994-04-12 |
| MX9305603A (es) | 1994-05-31 |
| PL169823B1 (pl) | 1996-09-30 |
| MY129454A (en) | 2007-04-30 |
| US5547906A (en) | 1996-08-20 |
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