JPH0851181A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH0851181A
JPH0851181A JP6184432A JP18443294A JPH0851181A JP H0851181 A JPH0851181 A JP H0851181A JP 6184432 A JP6184432 A JP 6184432A JP 18443294 A JP18443294 A JP 18443294A JP H0851181 A JPH0851181 A JP H0851181A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
sealed
semiconductor
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6184432A
Other languages
Japanese (ja)
Inventor
Tetsuo Muramatsu
哲雄 村松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP6184432A priority Critical patent/JPH0851181A/en
Publication of JPH0851181A publication Critical patent/JPH0851181A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】 【目的】 樹脂モールド部面積を少なくして複数の半導
体チップを高密度に実装した樹脂封止型半導体装置を提
供する。 【構成】 半導体チップ3をダイパッド部4に接着し、
半導体チップ3から金属細線6でインナーリード部5に
接続して半導体回路部を形成した。そして、複数個の半
導体回路部を、1モールド部で実装回路基板7に対し
て、垂直に配列して封止した。これにより、1モールド
当りの樹脂面積を少なくでき、高密度で複数の半導体チ
ップを1モールド実装できた。よって、樹脂封止型半導
体装置を実装する実装回路基板7の面積を少なくするこ
ともでき、高密度化にも対応できる。
(57) [Summary] [Object] To provide a resin-encapsulated semiconductor device in which a plurality of semiconductor chips are mounted at high density by reducing the area of the resin mold portion. [Structure] The semiconductor chip 3 is bonded to the die pad portion 4,
A semiconductor circuit portion was formed by connecting the semiconductor chip 3 to the inner lead portion 5 with a thin metal wire 6. Then, a plurality of semiconductor circuit parts were arranged vertically with respect to the mounting circuit board 7 by one molding part and sealed. As a result, the resin area per mold can be reduced, and a plurality of semiconductor chips can be mounted in one mold with high density. Therefore, it is possible to reduce the area of the mounting circuit board 7 on which the resin-sealed semiconductor device is mounted, and it is possible to cope with high density.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は主に回路実装基板面積を
減少させ、あるいは樹脂モールド面積を減少させ、回路
集積度を向上させることができる樹脂封止型半導体装置
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a resin-encapsulated semiconductor device capable of reducing a circuit mounting substrate area or a resin molding area and improving circuit integration.

【0002】[0002]

【従来の技術】近年、半導体装置としては半導体チップ
を樹脂で封止したタイプのいわゆる樹脂封止型半導体装
置の開発が盛んであり、それに伴ってパッケージの外形
の小型化や、パッケージ内または外部の微細加工による
高集積化も向上している。
2. Description of the Related Art In recent years, as a semiconductor device, a so-called resin-encapsulated semiconductor device of a type in which a semiconductor chip is encapsulated with resin has been actively developed. The high degree of integration is also improved by the fine processing of.

【0003】従来は、樹脂封止型半導体装置の樹脂封止
したモールド部の一側面に外部電極端子がマトリックス
状に多数出ているものがあるが、半導体チップの内蔵個
数がただ1個であり、またその半導体チップの内蔵方向
が樹脂封止型半導体装置を実装する回路基板に対して平
行に配列されていた。図5に従来の樹脂封止型半導体装
置の断面構造を示す。
Conventionally, a large number of external electrode terminals are arranged in a matrix on one side surface of a resin-sealed mold part of a resin-sealed semiconductor device, but the number of built-in semiconductor chips is only one. Also, the direction in which the semiconductor chips are embedded is arranged parallel to the circuit board on which the resin-sealed semiconductor device is mounted. FIG. 5 shows a cross-sectional structure of a conventional resin-sealed semiconductor device.

【0004】図5に示す従来の樹脂封止型半導体装置
は、外観は樹脂によるモールド部1と、モールド部1の
側面から突出している外部電極端子2よりなっている。
そしてモールド部1内には、半導体チップ3がリードフ
レームのダイパッド部4上に導電性接着剤により接合さ
れ、リードフレームのインナーリード部5と前記半導体
チップ3とは金属細線6により電気的接続がなされてい
る。
The conventional resin-encapsulated semiconductor device shown in FIG. 5 has a molded portion 1 made of resin and an external electrode terminal 2 protruding from the side surface of the molded portion 1.
The semiconductor chip 3 is bonded on the die pad portion 4 of the lead frame by a conductive adhesive in the mold portion 1, and the inner lead portion 5 of the lead frame and the semiconductor chip 3 are electrically connected by the thin metal wire 6. Has been done.

【0005】[0005]

【発明が解決しようとする課題】前記従来の樹脂封止型
半導体装置のモールド部内に内蔵されている半導体チッ
プの配列方向が前記樹脂封止型半導体装置を実装する回
路基板に対して、平行である分、モールド部の面積を広
くしなければならないため、回路基板の面積をその分広
げる必要があり、内蔵する半導体チップが複数個もあれ
ばその分大幅に広げなければならなかった。また、外部
電極端子も数が多ければ多いほどその分電気特性が取れ
るため機能は向上するが、その分モールド面積を広げな
くてはならなかった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention The arrangement direction of the semiconductor chips embedded in the mold portion of the conventional resin-sealed semiconductor device is parallel to the circuit board on which the resin-sealed semiconductor device is mounted. To some extent, the area of the mold part must be increased, and therefore the area of the circuit board must be increased accordingly. If there are a plurality of built-in semiconductor chips, the area must be increased correspondingly. Further, the larger the number of external electrode terminals, the more the electrical characteristics can be obtained, and thus the function is improved. However, the mold area must be expanded accordingly.

【0006】そこで本発明は、樹脂封止型半導体装置の
モールド部の面積を大幅に増加させることなく、複数個
の半導体チップを1モールドで高密度に実装した樹脂封
止型半導体装置を実現することを目的とし、またその樹
脂封止型半導体装置を実装する回路基板の面積の増加も
抑えることができる樹脂封止型半導体装置を提供する。
Therefore, the present invention realizes a resin-encapsulated semiconductor device in which a plurality of semiconductor chips are densely mounted in one mold without significantly increasing the area of the molded portion of the resin-encapsulated semiconductor device. It is an object of the present invention to provide a resin-encapsulated semiconductor device capable of suppressing an increase in the area of a circuit board on which the resin-encapsulated semiconductor device is mounted.

【0007】[0007]

【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、半導体チップをリードフレームのダイパッド
上に接着し、接着した半導体回路チップからインナーリ
ードまでをワイヤーボンドで接続して形成した半導体回
路部を複数枚、樹脂封止型半導体装置を実装する回路基
板に対して半導体チップが垂直になるように非接触で重
なり合うように同一方向に配列して封止樹脂でモールド
するようにしている。
The resin-sealed semiconductor device of the present invention is formed by bonding a semiconductor chip onto a die pad of a lead frame and connecting the bonded semiconductor circuit chip to the inner lead by wire bonding. A plurality of semiconductor circuit parts are arranged in the same direction so that the semiconductor chips are overlapped in a non-contact manner so that the semiconductor chips are perpendicular to the circuit board on which the resin-sealed semiconductor device is mounted. There is.

【0008】[0008]

【作用】本発明の構成によると、樹脂封止型半導体装置
のモールド部内の半導体チップの内蔵方向が、回路基板
に対して垂直かつ非接触で重なり合うように同一方向に
配列しているので、回路基板に対する半導体チップの面
積は少なくなり、モールド部の面積を少なく取れる。ま
た内蔵する半導体チップの数を多くすればするほど、前
記のようなモールド部の面積の差が大きくなるので、本
発明にかかる技術を複数個の半導体チップを内蔵する樹
脂封止型半導体装置に適用した場合は、集積度が増し、
小型化が図れる。
According to the structure of the present invention, since the embedded direction of the semiconductor chips in the mold portion of the resin-sealed semiconductor device is arranged in the same direction so as to overlap the circuit board vertically and in a non-contact manner, The area of the semiconductor chip with respect to the substrate is reduced, and the area of the mold portion can be reduced. Further, the greater the number of built-in semiconductor chips, the larger the difference in the area of the mold portion as described above. Therefore, the technique according to the present invention is applied to a resin-sealed semiconductor device having a plurality of built-in semiconductor chips. When applied, the degree of integration increases,
The size can be reduced.

【0009】[0009]

【実施例】本発明の一実施例について、以下、図面を参
照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0010】図1は本発明の一実施例にかかる樹脂封止
型半導体装置の外観斜視図である。図1において、1は
封止用樹脂によるモールド部、2はモールド部1内に内
蔵されている半導体チップの電気特性を取り出すための
外部電極端子である。
FIG. 1 is an external perspective view of a resin-sealed semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a mold portion made of a sealing resin, and 2 is an external electrode terminal for taking out electrical characteristics of a semiconductor chip built in the mold portion 1.

【0011】次に図1に示した樹脂封止型半導体装置の
詳細な構成について説明する。図2は図1で示した樹脂
封止型半導体装置の正面断面図であり、樹脂封止型半導
体装置を回路実装基板に接合した状態での断面を示して
いる。図3は同様に図1で示した樹脂封止型半導体装置
の側面断面図であり、樹脂封止型半導体装置を回路実装
基板に接合した状態での断面を示している。図4は同様
に図1で示した樹脂封止型半導体装置の平面断面図であ
り、樹脂封止型半導体装置を実装回路基板に接合した状
態での断面を示している。
Next, the detailed structure of the resin-sealed semiconductor device shown in FIG. 1 will be described. FIG. 2 is a front cross-sectional view of the resin-sealed semiconductor device shown in FIG. 1, showing a cross-section in a state where the resin-sealed semiconductor device is bonded to a circuit mounting board. Similarly, FIG. 3 is a side sectional view of the resin-sealed semiconductor device shown in FIG. 1, and shows a cross-section in a state where the resin-sealed semiconductor device is bonded to a circuit mounting board. Similarly, FIG. 4 is a plan sectional view of the resin-encapsulated semiconductor device shown in FIG. 1, and shows a section in a state where the resin-encapsulated semiconductor device is bonded to a mounting circuit board.

【0012】図2、図3および図4において、3は半導
体チップである。4は半導体チップ3を搭載接合してい
るリードフレームのダイパッド部である。5はリードフ
レームのインナーリード部である。6は半導体チップ3
とインナーリード部5とを電気的に接続するための金属
細線であり、アルミニウム線もしくは金線である。7は
樹脂封止型半導体装置を接合した実装回路基板であり、
樹脂封止型半導体装置の外部電極端子2がハンダ8で接
合される。なお、外部電極端子2はリードフレームの前
記インナーリード部5が延在し、封止用樹脂のモールド
部1より外部に突出している部分である。
In FIGS. 2, 3, and 4, reference numeral 3 is a semiconductor chip. Reference numeral 4 is a die pad portion of the lead frame on which the semiconductor chip 3 is mounted and bonded. Reference numeral 5 is an inner lead portion of the lead frame. 6 is a semiconductor chip 3
Is a thin metal wire for electrically connecting the inner lead portion 5 with the inner lead portion 5, and is an aluminum wire or a gold wire. 7 is a mounting circuit board to which a resin-sealed semiconductor device is joined,
The external electrode terminals 2 of the resin-sealed semiconductor device are joined with solder 8. The external electrode terminal 2 is a portion in which the inner lead portion 5 of the lead frame extends and projects to the outside from the mold portion 1 of the sealing resin.

【0013】なお、リードフレームのダイパッド部4上
に接合された半導体チップ3と、半導体チップ3とリー
ドフレームのインナーリード部5の一端とを電気的接続
した金属細線6とにより、半導体回路部を構成してい
る。
The semiconductor circuit portion is formed by the semiconductor chip 3 bonded on the die pad portion 4 of the lead frame and the thin metal wire 6 electrically connecting the semiconductor chip 3 and one end of the inner lead portion 5 of the lead frame. I am configuring.

【0014】以上のような構成の本実施例の樹脂封止型
半導体装置においては、半導体チップ3が複数個、図3
および図4に示すように縦型でモールド部1内に封止さ
れている。つまりは、図3、図4に示すように、複数枚
のリードフレームを用い、各々のリードフレームのダイ
パッド部4に半導体チップ3を接合して縦型(垂直)に
同一方向に配置し、封止用樹脂でモールドし、またリー
ドフレームのインナーリード部5を下方に延在させ、モ
ールド部1より突出させている。
In the resin-encapsulated semiconductor device of this embodiment having the above-mentioned structure, a plurality of semiconductor chips 3 are provided.
And, as shown in FIG. 4, it is vertically sealed in the mold part 1. That is, as shown in FIGS. 3 and 4, a plurality of lead frames are used, the semiconductor chip 3 is bonded to the die pad portion 4 of each lead frame, arranged vertically (vertically) in the same direction, and sealed. It is molded with a stop resin, and the inner lead portion 5 of the lead frame is extended downward so as to protrude from the molding portion 1.

【0015】なお、図においては、半導体チップ3の個
数は4個としているが、その数については、目的に応じ
て増減可能である。
Although the number of semiconductor chips 3 is four in the figure, the number can be increased or decreased according to the purpose.

【0016】本実施例の構成により、半導体チップを搭
載したダイパッドをそれぞれ有したリードフレーム群を
同一方向で、かつ実装する実装回路基板に垂直に配列
し、リードフレームのリード部分を同一方向の一側面か
ら突出させることにより、集積度を向上させ、複数個の
半導体チップを樹脂封止し、一つのパッケージ内に高密
度に内蔵させることができる。
With the structure of this embodiment, lead frame groups each having a die pad on which a semiconductor chip is mounted are arranged in the same direction and perpendicularly to the mounting circuit board to be mounted, and the lead portions of the lead frame are arranged in the same direction. By projecting from the side surface, the degree of integration can be improved, a plurality of semiconductor chips can be resin-sealed, and they can be incorporated in one package at a high density.

【0017】[0017]

【発明の効果】本発明によれば、樹脂封止型半導体装置
のモールド部内の半導体チップの内蔵方向を実装する回
路実装基板方向に対して垂直にすることにより、モール
ド部の幅、または奥行き方向の厚みを抑えて高密度の樹
脂封止型半導体装置を得ることができる。そして本発明
にかかる樹脂封止型半導体装置を用いることにより、実
装する実装回路基板上の実装面積を抑えることができ
る。これにより実装回路基板の小型化や、高密度化も可
能となる。
According to the present invention, the direction of embedding a semiconductor chip in a mold portion of a resin-sealed semiconductor device is made perpendicular to the direction of a circuit mounting board on which the semiconductor chip is mounted. It is possible to obtain a high-density resin-sealed semiconductor device by suppressing the thickness of the. By using the resin-sealed semiconductor device according to the present invention, the mounting area on the mounted circuit board to be mounted can be suppressed. As a result, the mounted circuit board can be downsized and the density can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例にかかる樹脂封止型半導体装
置の外観斜視図
FIG. 1 is an external perspective view of a resin-sealed semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施例にかかる樹脂封止型半導体装
置の正面断面図
FIG. 2 is a front sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention.

【図3】本発明の一実施例にかかる樹脂封止型半導体装
置の側面断面図
FIG. 3 is a side sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention.

【図4】本発明の一実施例にかかる樹脂封止型半導体装
置の平面断面図
FIG. 4 is a plan sectional view of a resin-encapsulated semiconductor device according to an embodiment of the present invention.

【図5】従来の樹脂封止型半導体装置の断面図FIG. 5 is a sectional view of a conventional resin-encapsulated semiconductor device.

【符号の説明】[Explanation of symbols]

1 モールド部 2 外部電極端子 3 半導体チップ 4 ダイパッド部 5 インナーリード部 6 金属細線 7 実装回路基板 8 ハンダ 1 Mold Part 2 External Electrode Terminal 3 Semiconductor Chip 4 Die Pad Part 5 Inner Lead Part 6 Thin Metal Wire 7 Mounted Circuit Board 8 Solder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 リードフレームのダイパッド上に接合さ
れた半導体素子と、前記半導体素子と前記リードフレー
ムのリード部の一端とを電気的接続した金属細線とより
なる半導体回路部と、前記半導体回路部を樹脂封止した
樹脂封止型半導体装置であって、前記樹脂封止型半導体
装置の樹脂封止面の一側面から前記リードフレームのリ
ード部の樹脂封止されていない部分が外部電極端子とし
て延在してなり、また前記半導体回路部は前記樹脂封止
型半導体装置が実装される回路基板に対して垂直方向に
複数個同一方向に配列して設けられて樹脂封止されてい
ることを特徴とする樹脂封止型半導体装置。
1. A semiconductor circuit portion comprising a semiconductor element bonded on a die pad of a lead frame, and a thin metal wire electrically connecting the semiconductor element and one end of a lead portion of the lead frame, and the semiconductor circuit portion. A resin-sealed semiconductor device in which the resin-sealed semiconductor device is a resin-sealed semiconductor device, and a portion of the lead frame not resin-sealed from one side surface of the resin-sealed semiconductor device serves as an external electrode terminal. And a plurality of the semiconductor circuit portions are arranged in the same direction in the vertical direction with respect to the circuit board on which the resin-sealed semiconductor device is mounted and are resin-sealed. A characteristic resin-encapsulated semiconductor device.
【請求項2】 樹脂封止型半導体装置が実装される回路
基板に対して垂直方向に複数個配列して設けられて樹脂
封止されている半導体回路部同士が、樹脂封止した樹脂
部の幅または奥行き方向に非接触で重なり合って同一方
向に配列されていることを特徴とする請求項1記載の樹
脂封止型半導体装置。
2. A plurality of semiconductor circuit parts, which are arranged in a direction perpendicular to a circuit board on which a resin-sealed semiconductor device is mounted and are resin-sealed, are resin-sealed resin parts. 2. The resin-encapsulated semiconductor device according to claim 1, wherein the resin-encapsulated semiconductor devices are arranged in the same direction so as to overlap in the width or depth direction without contact.
JP6184432A 1994-08-05 1994-08-05 Resin-sealed semiconductor device Pending JPH0851181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6184432A JPH0851181A (en) 1994-08-05 1994-08-05 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6184432A JPH0851181A (en) 1994-08-05 1994-08-05 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH0851181A true JPH0851181A (en) 1996-02-20

Family

ID=16153055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6184432A Pending JPH0851181A (en) 1994-08-05 1994-08-05 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH0851181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6380616B1 (en) 1998-01-15 2002-04-30 Infineon Technologies Ag Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6380616B1 (en) 1998-01-15 2002-04-30 Infineon Technologies Ag Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component

Similar Documents

Publication Publication Date Title
US5800958A (en) Electrically enhanced power quad flat pack arrangement
KR100294719B1 (en) Molded semiconductor device and method for manufacturing the same, lead frame
US6459148B1 (en) QFN semiconductor package
US5770888A (en) Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
JP3243116B2 (en) Semiconductor device
JP2000133767A (en) Laminated semiconductor package and method of manufacturing the same
KR100369907B1 (en) Semiconductor Package And Mounting Structure On Substrate Thereof And Stack Structure Thereof
US6396129B1 (en) Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package
JPH09312375A (en) Lead frame, semiconductor device, and method of manufacturing semiconductor device
JP2001035961A (en) Semiconductor device and manufacturing method thereof
JP3259377B2 (en) Semiconductor device
JP3153197B2 (en) Semiconductor device
JP2524482B2 (en) QFP structure semiconductor device
JP2533012B2 (en) Surface mount semiconductor device
JPH0851181A (en) Resin-sealed semiconductor device
JP2533011B2 (en) Surface mount semiconductor device
KR0148078B1 (en) Lead on chip having forward lead
KR100537893B1 (en) Leadframe and multichip package using the same
KR19990086280A (en) Semiconductor package
KR100639700B1 (en) Chip Scale Stacked Chip Packages
JPH11354673A (en) Semiconductor device
KR100481927B1 (en) Semiconductor Package and Manufacturing Method
KR100525091B1 (en) semiconductor package
KR950003904B1 (en) Semiconductor package
JP2629461B2 (en) Resin-sealed semiconductor device