JPH0855853A - Formation method of conductive layer - Google Patents

Abstract

PURPOSE:To obtain a formation method in which a low-resistance conductive layer in a minute pattern is formed with good dimensional accuracy and simply. CONSTITUTION:A poly-Si layer and a Ti layer are deposited sequentially on a gate insulating film 34A, a heat-treatment is then executed in an N2 or NH3 atmosphere, and a TiN/TiSi2 laminate is formed. By a dry-etching treatment which uses a resist layer 40A as a mask, the TiN/TiSi2 laminate is patterned, and a TiN layer 38A1 and a TiSi2 layer 38B2 as a part of the laminate are left. The resist layer 40A is removed, poly-Si layer 36 is patterned by a dry- etching treatment which uses the layers 38A1, 38B1 as a mask, and a part of the layer 36 is left. A laminate by the remaining part of the layer 36 and by the layers 38A1, 38B1 is used as a gate electrode. A laminate by the layers 38A1, 38B1 and by the resist layer 40A may be used as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a low resistance conductive layer having a fine pattern used as an electrode or wiring of a semiconductor device or the like. Titanium nitride (TiN) / titanium silicide (TiSi)
₂ ) A low resistance conductive layer can be easily formed with high dimensional accuracy by forming a laminated layer, patterning the TiN / TiSi ₂ laminated layer, and then patterning the poly-Si layer using the remaining portion of the laminated layer as a mask.

[0002]

2. Description of the Related Art Conventionally, the following methods (a) to (d) are known as methods for patterning a conductive material layer for electrodes or wiring.

(A) As shown in FIG. 19, after forming a conductive material layer 3 on an insulating film 2 which covers the surface of a semiconductor substrate 1, resist layers 4A to 4C having a desired pattern are formed by a well-known photolithography process. And the conductive material layer 3 is selectively dry-etched using these resist layers as a mask.

(B) A silicon oxide film or a silicon nitride film having a low etching rate is used as a mask for patterning (for example, Japanese Unexamined Patent Publication No. 2-125425).
(See the official gazette). Further, a laminated film in which a resist layer is laminated on an inorganic film such as silicon oxide or silicon nitride is used as a mask for patterning (for example,
J. -S. Maa et al. : J. Vac. Sc
i. Technol. B9 (3), May / Jun 1
991 p. 1596-1597 or P.I. E. Rile
y et al. : Solid State Tech
noology Feb. 1993 p. 47-55 etc.).

(C) A resist layer containing a light-absorbing dye is used as a patterning mask when patterning on a high reflectance substrate.

(D) An antireflection film is provided on the surface of the conductive material layer to be patterned when patterning on a high reflectance substrate. As the antireflection film, a method using a silicon nitride film is known (see, for example, JP-A-1-241125 and JP-A-5-55130), and a method using a TiN film is also known. (For example, JP-A-60-240127, JP-A-6-240127)
1-185928, JP-A-63-232324, etc.).

[0007]

When the patterning of the fine wiring is performed by the above method (a), the etching rate changes according to the wiring interval (space width) (the microloading effect of the etching rate). There is an inconvenience that the formation yield decreases.

That is, in a pattern in which the space width is reduced in the order of the resist layers 4A, 4B, and 4C as shown in FIG. 19, the etching rate decreases as the space width becomes narrower as shown in FIG. I have something to do. For this reason, if a predetermined amount of etching is performed at a location where the space width is narrow, overetching may occur at a location where the space width is wide, and the film loss of the underlying film such as the insulating film 2 may increase.

Contrary to the above, if the space width becomes smaller, the etching rate may increase. That is, as shown in FIG. 21, the resist layers 4a, 4b, 4
In a pattern in which the space width decreases in the order of c and 4d, the etching rate may increase as the space width decreases as shown in FIG. Therefore, if a desired amount of etching is performed at a location with a wide space width, overetching occurs at a location with a narrow space width, and X ₁ ,
As shown in the section of X ₂ , there is a case where the undercoating occurs.

Further, in the fine wiring patterning as described above, there is also a disadvantage that the wiring formation yield is reduced due to the etching shape or dimension changing according to the space width (micro loading effect of etching shape).

That is, as shown in FIG. 23, when the dense wiring layers 3P and 3Q are obtained by dry etching using the dense resist layers 4P and 4Q as a mask, for example, the width W _D of the wiring layer 3P is It is almost equal to the width W ₀ of 4P (W _D ≈W ₀ ). On the other hand, as shown in FIG. 24, when the isolated wiring layer 3R is obtained by performing dry etching with the resist layer 4R having the isolated width W ₀ as a mask, the width W _I of the wiring layer 3R is
It becomes larger than the width W _D shown in FIG. 23 (W _I > W _D ).
The it is generally, in the etching of exceptionally WSi ₂ / poly-Si multilayer (a laminate of the WSi ₂ layer on the poly-Si layer) to be an W _I <W _D.

As an example where W _I > W _D , when etching an Al alloy using BCl ₃ / Cl ₂ as an etching gas, Cl ₂ / O ₂ , C as an etching gas is used.
There is a case where a poly Si layer or a polycide layer (a silicide layer is laminated on a poly Si layer) is etched using l ₂ / N ₂ or SF ₆ / C ₂ Cl ₃ F ₃ or the like. Further, as an example in which W _I <W _D , HBr / SF _{6 is used} as an etching gas in a magnetron RIE (reactive ion etching) device as described later with reference to FIG.
There is a case where the polycide layer is etched by using.

Meanwhile, in the fine wiring patterning as described above, there is also a disadvantage that the wiring formation yield is reduced due to an increase in the film reduction amount of the mask material such as a resist (a reduction in the mask selection ratio).

That is, in dry etching,
In addition to the chemical reaction between the gas and the mask material, ions or particles having kinetic energy collide with the mask material, causing a film loss of the mask material. When particles having kinetic energy collide with the mask material, the mask material is
At 5, the shoulder layer is shaped like a shoulder as shown in the resist layer 4S. The angle of the shoulder portion of the mask material is a value that maximizes the sputtering efficiency. However, the actual angle is not 45 °, which is efficient for purely physical sputter etching. The phenomenon that the shoulder part of the mask material is sputtered is called "faceting", and the surface formed on the shoulder part is called "facet".

FIG. 25 shows a step of forming a wiring layer by dry-etching the conductive material layer 3 using the resist layer 4S as a mask. The line width (wiring width) K is the conductive material layer 3
Is set to a small value close to the thickness T. Even if faceting occurs as shown in FIG. 25, the upper surface of the resist layer 4S is present until the left and right facets come into contact with each other, and the resist film reduction amount ΔT ₁ is equal to the conductive material layer (etched material layer) 3 Is equal to the film thickness reduction amount of the resist having a sufficiently large pattern as compared with the film thickness T.

However, as shown in FIG. 26, when the etching progresses and the left and right facets come into contact with each other, the resist film reduction amount ΔT ₂ of the resist having a pattern sufficiently larger than the film thickness of the conductive material layer 3 is obtained. It is larger than the amount of film loss. The inventor believes that this is because the sum of the component of the faceting in the film thickness direction and the resist etching rate in the film thickness direction is the resist film reduction rate.

Such a phenomenon becomes more remarkable as the wiring width becomes smaller. That is, the thinner the wiring, the lower the effective selection ratio for resist.

FIG. 27 shows the line width K with respect to the resist film reduction amount, the resist selection ratio, and the resist taper angle θ.
It shows dependence. The resist taper angle θ is shown in FIG.
As shown in FIG. 6, it is the angle at which the extension line of any facet intersects the bottom surface of the conductive material layer 3. The data of FIG. 27 is obtained by using BCl ₃ / C as an etching gas in a microwave plasma etcher as described later with reference to FIG.
It was obtained when the Al alloy was etched by using l ₂ , and according to this, the reduction amount of the resist film increases with the decrease of the line width K (the selection ratio with respect to the resist decreases).
At the same time, it can be seen that the resist taper angle θ increases.

When the thickness of the resist layer used as an etching mask is made thin, the depth of focus of photolithography becomes deep and fine patterns can be formed. Further, by reducing the thickness of the resist layer, the microloading effect of dry etching is also reduced.

However, as described above with reference to FIGS. 25 to 27, the substantial selection ratio of the wiring to the etching mask decreases as the wiring becomes finer. Therefore, if the resist layer is thinned, the resist layer disappears during etching. Then, the wiring may be broken. Therefore, the resist layer cannot be made too thin.

In order to solve the problems such as the reduction of the mask selectivity with the miniaturization of the pattern, an etching technique having a high selectivity with respect to the mask material is developed or a mask material having a high selectivity is used. Need to be adopted. The above-mentioned method (b) is effective as a method for increasing the etching selection ratio with respect to the mask material.

However, the method using a silicon oxide film as a patterning mask has a problem that the silicon oxide film does not function as an antireflection film. The antireflection film will be described later. Further, the method of using the silicon nitride film as the patterning mask has a problem that the antireflection function of the silicon nitride film is insufficient. In addition, in either method, the inorganic mask material remains on the surface of the wiring or electrode after etching, and if the substrate experiences a high temperature in the subsequent process, the difference in the thermal expansion coefficient between the mask material and the conductive material may result. There is a problem that the mask material peels off from the surface of the wiring or the electrode to become particles, which lowers the yield.

By the way, when the wiring is formed on the high reflectance substrate, there is a disadvantage that the dimensional accuracy of the pattern is deteriorated due to irregular reflection on the substrate surface.

That is, when there is a step on the surface of the semiconductor substrate 1 due to the insulating films 5A and 5B as shown in FIG. 28, a resist layer 7A is formed on the surface of the substrate via a wiring material layer 6A and the resist layer 7A is formed. When the exposure process is performed by irradiating the light 9 through the mask 8 having a desired pattern, the light is reflected by the slopes AB and CD of the wiring material layer 6A having a high reflectance, and the resist layer 7A should not be exposed. Light reaches the area and exposes the area. After that, when resist development is performed, a resist layer 7 having a pattern as shown in FIG. 29 is obtained.

As shown in FIGS. 29 and 30, the resist layer 7 has a rectangular sectional shape in the flat portion and a desired width W ₁ can be obtained, but as shown in FIGS. 29 and 31, the insulating films 5A and 5A are formed.
In the portion sandwiched by B, the cross-sectional shape is semicircular and only the width W ₂ narrower than the desired width W ₁ can be obtained. Therefore, when the resist layer 7 to form the wiring layer wiring material layer 6A by dry etching as a mask, so that the resulting thinning and breaking in a portion of the width W ₂ in the wiring layer.

When forming a wiring on a high-reflectance substrate, there is also a problem that the pattern dimensions are different at different reflectances.

As an example, as shown in FIG. 32, after forming the insulating film 11 on the substrate 1 so as to cover the insulating film 5 and the gate electrode layer 10, the substrate surface is reached by a dry etching process using the resist layer 12 as a mask. When forming the insulating hole 11a and the connection hole 11b reaching the gate electrode layer 10,
The dimension W _{B of the} connection hole 11b is larger than the dimension W _A of the connection hole 11a.
Is bigger. When the size of the connection hole 11b is increased as described above, the alignment margin in the photolithography process is reduced, and the connection hole 11b may be formed at a position displaced from the gate electrode layer 10 as shown in FIG.
As a result, the wiring layer 13 is formed so as to electrically short the gate electrode layer 10 and the substrate surface. In order to prevent such a situation, it is necessary to increase the alignment margin by design, which leads to a decrease in the degree of integration.

The reason why the size of the connection hole becomes large in a place where the reflectance is high is that the diameter R of the hole in the resist layer 12 becomes large. The reason why the diameter R of the hole becomes large is explained as follows. To be done.

That is, in the photolithography technique, a pattern is formed by decomposing only a light-irradiated portion of a photosensitizer which makes a resist difficult to dissolve in a developer and dissolving it in the developer. The amount of decomposition of the photosensitizer increases with increasing exposure energy. Therefore, as shown in FIG. 34, the diameter R of the hole increases as the exposure energy increases.

When an object such as the gate electrode layer 10 having a high reflectance exists below the resist layer 12, the reflected light from the object is added to the resist layer 12. For this reason,
The effective exposure energy absorbed by the resist layer 12 is larger than that in a place where the reflectance is low. Therefore, the decomposition of the photosensitizer is promoted, and the diameter R of the hole is increased.

In the method (c) described above, since a dye that absorbs light for exposure is added to the resist layer, it is possible to suppress deterioration of dimensional accuracy due to reflection of light to some extent.

However, when the dye-containing resist layer 15 having a desired pattern is formed on the wiring material layer 14 covering the insulating film 5 as shown in FIG. 35, the cross-sectional shape of the resist layer 15 has a tapered bottom. Become a state. This is because the exposure energy of the resist attenuates as it gets deeper from the resist surface, and the dimension of the resist pattern becomes thicker as the exposure energy becomes smaller. When the wiring material layer 14 is dry-etched by using the resist layer 15 as a mask to form the wiring layer, the skirts a and b of the resist layer 15 are etched by the dry etching, and the wiring layer is thinned. is there. Further, since the resist layer 15 contains a dye, the resolution in the photolithography process is lowered. Therefore, the method (c) is not suitable for pattern miniaturization.

On the other hand, in the above-mentioned method (d), since the antireflection film is provided on the surface of the conductive material layer under the resist layer to suppress the light reflection, it is possible to prevent the deterioration of the dimensional accuracy due to the light reflection. It is effective, and there is no problem like the method (c).

However, in the above method (d), although the antireflection film is used, a resist layer having a sufficient thickness is used as an etching mask, so that the microloading effect at the time of dry etching cannot be reduced.

An object of the present invention is to provide a novel conductive layer forming method capable of forming a low resistance conductive layer having a fine pattern with dimensional accuracy.

[0036]

A method of forming a conductive layer according to the present invention comprises a step of forming a polysilicon layer on an insulating film covering a surface of a substrate and then forming a titanium layer on the polysilicon layer. And heat treating the polysilicon layer and the titanium layer in a nitriding atmosphere to form a titanium silicide layer overlapping the polysilicon layer and a titanium nitride layer overlapping the titanium silicide layer, and photolithography. Forming a resist layer having a desired pattern on the titanium nitride layer by a treatment, and patterning a stack of the titanium nitride layer and the titanium silicide layer by a dry etching treatment using the resist layer as a mask. A step of leaving a part of the laminated layer, and after removing the resist layer,
And a step of leaving a part of the polysilicon layer by patterning the polysilicon layer by a dry etching process using the remaining portion of the stack as a mask,
A laminate of the remaining portion of the polysilicon layer, the remaining portion of the titanium silicide layer, and the remaining portion of the titanium nitride layer is used as a conductive layer for electrodes or wiring.

In the conductive layer forming method of the present invention, the titanium nitride layer is patterned by dry etching using the resist layer as a mask, the resist layer is removed, and then the remaining portion of the titanium nitride layer is used as a mask. The stack of the titanium silicide layer and the polysilicon layer may be patterned by dry etching.

In the conductive layer forming method of the present invention, the thickness of the resist layer is sufficient for patterning the stacked layer of titanium nitride layer and titanium silicide layer (or titanium nitride layer), but the polysilicon layer. It may be set to a level insufficient for patterning (or a stack of a titanium silicide layer and a polysilicon layer). Then, after patterning the stack of the titanium nitride layer and the titanium silicide layer (or the titanium nitride layer), the resist layer and the remaining portion of the stack of the titanium nitride layer and the titanium silicide layer are removed without removing the resist layer. By patterning the polysilicon layer (or the stack of the titanium silicide layer and the polysilicon layer) by dry etching using a mask, a part of the polysilicon layer (or the stack of the titanium silicide layer and the polysilicon layer) is left and the resist The layer may be removed.

[0039]

According to the method of the present invention, the titanium silicide layer and the titanium nitride layer are formed in one step by heat-treating the titanium layer formed on the polysilicon layer in a nitriding atmosphere. In this case, when the titanium nitride layer having a thickness of about 30 to 50 nm is formed, the maximum antireflection effect can be obtained. By doing so, the resistance of the polysilicon layer can be reduced by the titanium silicide layer and the antireflection by the titanium nitride layer can be achieved at the same time.

A resist layer is not used as an etching mask when patterning a polysilicon layer (or a stack of titanium silicide layers and polysilicon layers), and a stack of titanium nitride layers and titanium silicide layers (or titanium nitride) is used. Layers) are used. Therefore, the resist layer may be thin enough to allow patterning of the stacked layer of the titanium nitride layer and the titanium silicide layer (or the titanium nitride layer), so that the depth of focus becomes deep in the photolithography process. Further, since the stack of the titanium nitride layer and the titanium silicide layer (or the titanium nitride layer) as the etching mask is thin, the microloading effect is reduced.

When the thin resist layer and the stack of the titanium nitride layer and the titanium silicide layer (or the titanium nitride layer) are used as the etching mask as described above, the polysilicon layer (or the titanium silicide layer and the polysilicon layer) is used. Since the resist layer is removed in the step of patterning (lamination), a separate step for removing the resist layer is unnecessary.

[0042]

1 to 15 show a method of manufacturing a MOS type IC according to an embodiment of the present invention, and steps (1) to (15) corresponding to the respective drawings will be sequentially described.

(1) A field insulating film 32 made of silicon oxide is formed on the surface of a semiconductor substrate 30 made of, for example, silicon by a well-known selective oxidation process. The insulating film 32 has holes 32A, 3 for arranging the active region.
Have 2B. Gate insulating films 34A, 3 made of silicon oxide by oxidizing the substrate surface in the holes 32A, 32B
4B is formed. As the insulating films 34A and 34B, Si is used.
_{A 3} N ₄ film may be used.

(2) Insulating films 32, 34A, 3 on the upper surface of the substrate
CVD of poly-Si layer 36 for gate electrode covering 4B
It is deposited by the (chemical vapor deposition) method. Impurities such as phosphorus and arsenic are doped into the poly-Si layer 36 during or after the CVD process to reduce the resistance. Then, a Ti layer 38 is deposited on the poly-Si layer 36 by the CVD method or the sputtering method. When an oxide film is formed on the surface of the poly-Si layer 36 during impurity doping, after removing the oxide film by hydrofluoric acid cleaning or the like, Ti
Deposit layer 38. The Ti layer 38 has a thickness of
The thickness is set such that a TiN layer having an antireflection effect can be obtained by the N / TiSi ₂ layer forming process. For example, when exposed to i-line or g-line, the TiN layer has an antireflection effect regardless of the thickness, but a maximum antireflection effect is obtained with a thickness of 30 to 50 nm. The thickness of the Ti layer 38 is set so that such a TiN layer can be formed.

(3) Nitrogen (N ₂ ) or ammonia (NH
₃ ) etc. in a nitriding atmosphere such as poly-Si layer 36 and Ti layer 3
8 is subjected to a heat treatment so that T which overlaps the poly-Si layer 36
iSi ₂ layer 38B and TiN layer 38 that overlaps this layer 38B
Form A and. The heat treatment is performed by a lamp annealing device or a diffusion furnace. In this case, on the surface of the Ti layer 38, the TiN layer 38A is formed by the nitriding reaction with N ₂ or NH _3.
Is formed, and a TiSi ₂ layer 38B is formed at the interface between the Ti layer 38 and the poly-Si layer 36 by the reaction of Ti and Si. Regarding the formation of the TiN layer and the TiSi ₂ layer, (i) “Next Generation VLSI Process Technology Application Edition” published by Realize Co., pp. 190-191,
(Ii) Sympo. on VLSI Techno
l. , V-2 (1986) 51 pp. 51-52.

The TiN layer 38A is used as an antireflection film in the step of FIG. 4, and is formed to have a thickness of 30 to 50 nm in order to obtain an antireflection effect.

The TiSi ₂ layer 38B serves to reduce the resistance of the poly Si layer 36. Table 1 below shows Ti
Si ₂ is another refractory metal silicide or doped poly Si
It shows that the resistivity is lower than that of.

[0048]

[Table 1] The data in Table 1 is from T.W. P. Cho et al. : Dr
y Etchingfor Microelectro
nics, edited by R. A. Powel
1, page 44.

(4) In the steps of FIGS. 4 and 5, a desired resist pattern is formed by photolithography.
First, a resist layer 40 is formed on the upper surface of the substrate by a spin coating method or the like so as to cover the TiN layer 38A. Then, exposure processing is performed. That is, the resist layer 40 is irradiated with the exposure light UV through the light-shielding masks M _A and M _B having a desired gate electrode formation pattern. At this time, the TiN layer 38A
Acts as an antireflection film, so that highly accurate resist patterning is possible.

(5) Next, the resist layer 40 is developed to form resist layers 40A and 40 having a desired pattern.
B is left. The thickness of the resist layers 40A and 40B is
It may be thin enough to pattern the TiN / TiSi ₂ stacks 38A and 38B but not enough to pattern the poly-Si layer 36, and may be, for example, 0.5 μm.

(6) TiN / TiSi ₂ is formed by dry etching using the resist layers 40A and 40B as a mask.
TiN layer 38A is formed by patterning the laminated layers 38A and 38B.
₁ , 38A ₂ and TiSi ₂ layers 38B ₁ and 38B ₂ (both are a part of the laminated layers 38A and 38B) are left. At this time, Cl ₂ may be used as the etching gas.
The TiSi ₂ layer 38B can be etched by the same gas plasma that etches the TiN layer 38A. It is considered that TiSi ₂ becomes volatile Ti chloride TiCl ₄ or Si chloride SiCl ₄ by reacting with chlorine and is etched away from the upper surface of the substrate.

(7) Resist layer 4 by ashing treatment
Remove 0A and 40B. As another method, the resist layers 40A and 40B may be removed by cleaning treatment using an organic solvent.

(8) TiN / TiSi ₂ laminated layer 38A ₁ ,
The poly-Si layer 36 is patterned by a dry etching process using 38B ₁ and 38A ₂ , 38B ₂ as a mask to form poly-Si layers 36A and 36B (both of which are poly-Si layer 36).
Part of) remains. Poly Si layer 36A, TiSi ₂
The stack of the layer 38B ₁ and the TiN layer 38A ₁ constitutes the gate electrode layer 42A, and the poly Si layer 36B and the TiSi ₂ layer 3 are formed.
8B ₂ and the TiN layer 38A ₂ are stacked to form the gate electrode layer 4
Make up 2B.

In patterning the poly-Si layer 36,
The etching gas is Cl ₂ / O ₂ , Cl ₂ / SF
A gas containing O ₂ or F such as ₆ , HBr / SF ₆ and HBr / O ₂ may be used. When a gas containing O ₂ or F is used, titanium oxide (Ti
O, TiO ₂ , Ti ₂ O ₃ ) or titanium fluoride (TiF
₃ ) is formed to suppress the progress of TiN etching.
Therefore, the TiN layer sufficiently functions as an etching mask.

(9) Electrode layers 42A and 42B and insulating film 3
Ion ION which is a conductivity type determining impurity is selectively implanted into the surface of the substrate using 2 as a mask to form a source region and a drain region having a low impurity concentration. Then, the side spacers 44A, 44 are formed on the electrode layers 42A, 42B, respectively.
After providing B, the selective ion implantation process is performed again in the same manner as described above to form the source region and the drain region having a high impurity concentration. As a result, source regions 46S ₁ and 46S ₂ and drain regions 46D ₁ and 46D ₂ each having a low concentration portion are obtained. The MOS type transistor T _A includes an electrode layer 42A, a source region 46S ₁ and a drain region 46D ₁ , and the MOS type transistor T _B includes an electrode layer 42B, a source region 46S ₂ and a drain region 46D ₂ .

(10) An interlayer insulating film 48 is formed on the upper surface of the substrate by CVD or the like so as to cover the transistors T _A and T _B and the insulating film 32. As the insulating film 48, a silicon oxide film, a silicon nitride film, a PSG (phosphosilicate glass) film, a BPSG (boron phosphosilicate glass) film, or the like can be used.

(11) A resist layer 50 having a desired connection hole forming pattern is formed on the insulating film 48 by photolithography. When the insulating film 48 is transparent, the TiN layers 38A ₁ , 3 forming the gate electrode layers are formed.
Since 8A ₂ acts as an antireflection film when the resist layer 50 is subjected to the exposure process, the dimensional accuracy of the resist pattern is good above the gate electrode layer.

(12) A source connection hole 48a and gate connection holes 48b and 48c are formed in the insulating film 48 by dry etching using the resist layer 50 as a mask. When an insulating film of titanium oxide, titanium fluoride or the like is formed on the surfaces of the TiN layers 38A ₁ and 38A ₂ as described above, the connection holes 48b and 48 are formed in order to obtain good electrical contact.
c through TiN layers 38A ₁ and 38A ₂ respectively to form Ti
It is formed so as to reach the S ₂ layers 38B ₁ and 38B ₂ . T
When the insulating film is not formed on the surfaces of the iN layers 38A ₁ and 38A ₂ , the connection holes 48b and 48c are formed in the TiN layers 38A ₁ and 38A ₁ .
It may be formed so as to reach the surface of 38A ₂ . After that, the resist layer 50 is removed.

(13) A wiring material layer 52 of Al or Al alloy is deposited on the upper surface of the substrate so as to cover the insulating film 48 and the connection holes 48a to 48c. Then, on the wiring material layer 52, a conductive material layer 54 such as TiN or TiON for the antireflection and etching mask is formed by, for example, the reactive sputtering method.

(14) A resist layer 56 having a desired wiring formation pattern is formed on the conductive material layer 54 by photolithography.

(15) The conductive material layer 54 is patterned by dry etching using the resist layer 56 as a mask to leave the conductive material layers 54A, 54B and 54C (all of which are part of the conductive material layer 54). After removing the resist layer 56, the wiring material layer 52 is patterned by a dry etching process using the conductive material layers 54A, 54B, and 54C as a mask to form the wiring material layers 52A, 52B, and 52C (all of the wiring material layers 52 are part of the wiring material layer 52). ) Remains. The lamination of the wiring material layer 52A and the conductive material layer 54A constitutes a wiring layer 58S ₁ connected to the source region 46S ₁ of the transistor T _A. The wiring material layer 52B and the conductive material layer 54B are stacked to form the transistor T.
_A wiring layer 58G ₁ connected to the _A gate electrode layer 42A is formed. The lamination of the wiring material layer 52C and the conductive material layer 54C is
A wiring layer 58G ₂ connected to the gate electrode layer 42B of the transistor T _B is formed.

In the above embodiment, the TiN / TiSi ₂ layer was patterned in the step of FIG. 6, but in the step of FIG. 6, the TiN layer 38A is formed by the dry etching process using the resist layers 40A and 40B as a mask. The TiN layers 38A ₁ and 38A ₂ may be patterned so that the TiN layers 38A ₁ and 38A ₂ remain. Then, in the process of FIG. 7, the resist layer 40A,
After removing 40B, in the process of FIG.
_The TiSi ₂ / poly Si stacks 38B, 36 are patterned by dry etching using ₁ , 38A ₂ as a mask to form parts 38B ₁ , 38B ₂ , 36A, 36 of the stacks.
You may make B remain.

Further, in the above-described embodiment, poly-Si is used in the state where the resist layer is removed in the step of FIG. 8 or FIG.
Layer 36 (or TiSi ₂ / poly Si stack 38B, 36)
Alternatively, although the wiring material layer 52 is patterned, the resist layer may be used as a mask without removing the resist layer.
That is, in the process of FIG. 8, the resist layers 40A and 40B are
And TiN / TiSi ₂ stacks 38A ₁ , 38B ₁ and 38
A ₂ and 38B ₂ (or TiN layers 38A ₁ and 38A ₂ ) are used as a mask, and in the process of FIG.
6 and the conductive material layers 54A to 54C as a mask, the resist layer 4 is formed by dry etching during patterning.
Alternatively, 0A, 40B or 56 may be removed. This eliminates the need for an independent process for removing the resist layer.

In order to confirm that the TiN layer is effective as an etching mask, TiN and poly-Si are removed by a gas containing O ₂ and F by using three kinds of dry etching apparatus as shown in FIGS. An etching experiment was conducted.

FIG. 16 shows an example of the microwave plasma etcher. A solenoid coil 62 is provided around the plasma chamber 60, and a microwave MW of 2.45 GHz is supplied to the chamber 60 from a magnetron 64 via a waveguide 66. An electrode 68 holding a wafer (substrate) WF to be processed is provided in the chamber 60, and a high frequency source RF of 2 MHz is connected to the electrode 68. The etching gas G is supplied into the chamber 60, and the lower portion of the chamber 60 is connected to the exhaust means VAC.

In the chamber 60, a uniform and high-density plasma can be generated under a wide range of pressure by the synergistic action of the microwave and the magnetic field. The ion energy incident on the wafer WF can be controlled by adjusting the high frequency power supplied to the electrode 68.

FIG. 17 shows an example of the ECR plasma etcher. Around the plasma chamber 70,
The magnet coil 72 is provided and the coil 72
A pipe for passing the cooling water CL is provided inside the chamber and around the chamber 70. 2.45 GH in the chamber 70
The microwave MW of z is supplied and the etching gas G is supplied. An etching chamber 74 is connected to a lower portion of the chamber 70, and the chamber 74 includes
A plasma flow PL is supplied from the chamber 70. An electrode 76 for holding the processing target wafer WF is provided in the chamber 74, and a high frequency source RF of 13.56 MHz is connected to the electrode 76. The lower part of the chamber 74 is connected to the exhaust means VAC.

FIG. 18 shows an example of a magnetron RIE apparatus. In the reaction chamber 80, the processed wafer W
An electrode 82 for holding F is provided, and a high frequency source RF of 13.56 MHz is connected to the electrode 82. A magnetic field B parallel to the surface of the wafer WF is formed in the reaction chamber by a coil or a permanent magnet (not shown), and the etching gas G is supplied from above. Reaction chamber 8
The lower part of 0 is connected to the exhaust means VAC.

(A) Using a microwave plasma etcher TiN and poly-Si were etched using a microwave plasma etcher as shown in FIG.
The data as shown in was obtained.

[0070]

[Table 2] In this case, the fixed conditions are gas pressure = 5 mTorr, RF
(2 MHz) power = 30 W, microwave power (anode current of magnetron) = 160 mA, electrode cooling water temperature = 20 ° C., upper coil current = 20.5 A, lower coil current 7.5 A.

Table 2 shows that the addition of O ₂ to Cl ₂ reduces the etching rate of TiN and improves the selection ratio with respect to poly Si ₂ .

(B) When using ECR plasma etcher When TiN having a thickness of 40 nm was etched for 5 minutes using an ECR plasma etcher as shown in FIG. 17, TiN was hardly etched. The etching conditions at this time are Cl ₂ / O ₂ = 25 / 11scc
m, gas pressure = 2 mTorr, RF (13.56 MHz)
Power = 34 W, microwave (2.45 GHz) power = 1400 W, and electrode cooling water temperature = 15 ° C.

Even if TiN having a thickness of 40 nm is etched in 5 minutes, the etching rate of TiN is 8 nm / minute. Therefore, it can be said that the etching rate of TiN is 8 nm / min or less.

When poly-Si was etched under the same conditions as TiN, the data shown in Table 3 below was obtained.

[0075]

[Table 3] As an example, a 300 nm thick poly-Si layer is TiN /
When dry etching is performed using the TiSi ₂ stack as a mask, the selection ratio of poly Si to TiN is> 30.3. , TiN
The layer acts as an etching mask.

On the other hand, when used as an antireflection film for i-ray or g-ray ultraviolet light, the thickness of the TiN layer may be 30 to 50 nm. Therefore, the TiN layer formed as the antireflection film on the TiSi ₂ / polySi stack sufficiently functions as an etching mask.

(C) When using magnetron RIE device When TiN and poly-Si were dry-etched using a magnetron RIE device as shown in FIG. 18, the data shown in the following Table 4 were obtained. The etching conditions at this time were HBr / SF ₆ = 15/45 sccm, pressure = 20 mTorr, RF power = 250 W, magnetic flux density = 30 Gauss, and cooling water temperature = 40 ° C.

[0078]

[Table 4] Calculating from the selection ratio in Table 4, when dry etching a 300 nm poly-Si layer using a TiN / TiSi ₂ stack as a mask, the thickness of the TiN layer should be 32.2 nm assuming that 30% overetching is performed. Become. In the case of a poly-Si layer having a thickness of 200 nm,
The thickness of the TiN layer is 21.5 nm (overetch 30
%) I understand that it is all right.

In summary, in dry etching using a gas containing O ₂ and F, it is understood that the TiN layer can be used as an etching mask because the selection ratio of polySi to TiN is high.

[0080]

As described above, according to the present invention, the titanium layer formed on the polysilicon layer is heat-treated in a nitriding atmosphere to form the titanium silicide layer and the titanium nitride layer, and then the resist layer. The titanium nitride / titanium silicide layer (or titanium nitride layer) as a mask, and the remaining portion of the layer (or titanium nitride layer) as a mask is used to pattern the polysilicon layer (or titanium silicide / polysilicon layer). As a result, (1) it is possible to simultaneously achieve the low resistance of the polysilicon layer by the titanium silicide layer and the antireflection by the titanium nitride layer.
(2) By reducing the thickness of the resist layer when patterning the titanium nitride / titanium silicide layer (or titanium nitride layer), the depth of focus in the photolithography process is improved, and fine patterns can be formed. (3) When patterning the polysilicon layer (or titanium silicide / polysilicon layer), the thickness of the titanium nitride / titanium silicide layer (or titanium nitride layer) as an etching mask is thin, The micro-loading effect during dry etching is reduced, and the dimensional accuracy is improved.

Moreover, the polysilicon layer (or titanium silicide / polysilicon layer) is patterned by using the thin resist layer and the remaining portion of the titanium nitride / titanium silicide layer (or titanium nitride layer) as a mask. If the resist layer is also removed, there is also an advantage that an independent process for removing the resist layer is unnecessary.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a gate insulating film forming step in a method of manufacturing a MOS type IC according to an embodiment of the present invention.

FIG. 2 is a substrate cross-sectional view showing a poly-Si and Ti deposition step following the step of FIG.

FIG. 3 is a substrate cross-sectional view showing a heat treatment step for forming a TiN / TiSi ₂ stack following the step of FIG.

FIG. 4 is a substrate cross-sectional view showing a resist exposure step that follows the step of FIG.

FIG. 5 is a substrate cross-sectional view showing a resist developing step following the step of FIG.

FIG. 6 is a substrate cross-sectional view showing a TiN / TiSi ₂ laminated etching step following the step of FIG. 5;

FIG. 7 is a substrate cross-sectional view showing a resist removing step following the step of FIG.

FIG. 8 is a substrate cross-sectional view showing a poly-Si layer etching step that follows the step of FIG.

FIG. 9 is a substrate cross-sectional view showing a source / drain formation process following the process of FIG. 8;

FIG. 10 is a substrate cross-sectional view showing an interlayer insulating film forming step following the step of FIG.

11 is a substrate cross-sectional view showing a resist pattern forming step following the step of FIG.

12 is a substrate cross-sectional view showing a connection hole forming step that follows the step of FIG.

13 is a cross-sectional view of a substrate showing a wiring material and conductive material deposition step following the step of FIG.

FIG. 14 is a substrate cross-sectional view showing a resist pattern forming step following the step of FIG.

FIG. 15 is a substrate cross-sectional view showing a wiring patterning step that follows the step of FIG.

FIG. 16 is a cross-sectional view showing an example of a microwave plasma etcher.

FIG. 17 is a sectional view showing an example of an ECR plasma etcher.

FIG. 18 is a sectional view showing an example of a magnetron RIE apparatus.

FIG. 19 is a cross-sectional view of a substrate showing a situation where the etching rate decreases in a narrow space.

FIG. 20 is a substrate cross-sectional view showing the relationship between the space width and the etching rate.

FIG. 21 is a cross-sectional view of a substrate showing a situation where the etching rate increases in a narrow space.

FIG. 22 is a substrate cross-sectional view showing the relationship between the space width and the etching rate.

FIG. 23 is a substrate cross-sectional view showing an etching state of a dense wiring layer.

FIG. 24 is a substrate cross-sectional view showing a state of etching an isolated wiring layer.

FIG. 25 is a cross-sectional view showing an etching state of a mask material in fine wiring patterning.

FIG. 26 is a cross-sectional view showing a state where etching has progressed more than in the case of FIG.

FIG. 27 is a graph showing a relationship between a line width, a resist film reduction amount, a resist selectivity ratio, and a resist taper angle.

FIG. 28 is a substrate cross-sectional view showing a resist exposure state on a substrate having a step.

FIG. 29 is a substrate top view showing the resist development state of FIG. 28.

30 is a cross-sectional view taken along the line X-X ′ of FIG. 29.

31 is a cross-sectional view taken along the line Y-Y ′ of FIG. 29.

FIG. 32 is a cross-sectional view of a substrate showing a situation of forming a connection hole when the reflectance of the substrate differs depending on the location.

FIG. 33 is a substrate cross-sectional view showing a wiring formation state when the connection hole formation position is displaced.

FIG. 34 is a graph showing the relationship between exposure energy and hole diameter.

FIG. 35 is a substrate cross-sectional view showing a step of forming a dye-containing resist layer.

[Explanation of symbols]

30: semiconductor substrate, 32, 34A, 34B, 48: insulating film, 36: poly-Si layer, 38: Ti layer, 38A: TiN
Layer, 38B: TiSi ₂ layer, 40, 50, 56: resist layer, 42A, 42B: electrode layer, 52: wiring material layer, 5
4: Conductive material layer, 58S ₁ , 58G ₁ , 58G ₂ : Wiring layer, T _A , T _B : Transistor.

Claims (4)

[Claims] 1. A step of forming a polysilicon layer on an insulating film covering a surface of a substrate and then forming a titanium layer on the polysilicon layer, and a nitriding atmosphere in the polysilicon layer and the titanium layer. A step of forming a titanium silicide layer that overlaps the polysilicon layer and a titanium nitride layer that overlaps the titanium silicide layer by performing a heat treatment in a photolithography process to form a desired pattern on the titanium nitride layer. A step of forming a resist layer having, a step of patterning a stack of the titanium nitride layer and the titanium silicide layer by a dry etching process using the resist layer as a mask, and leaving a part of the stack, the resist layer After removing the film, a dry etching process using the remaining portion of the laminated film as a mask is performed. And a step of leaving a part of the polysilicon layer left by patterning the polysilicon layer, and stacking a remaining part of the polysilicon layer, a remaining part of the titanium silicide layer, and a remaining part of the titanium nitride layer. A method for forming a conductive layer used as a conductive layer for electrodes or wiring. 2. A step of forming a titanium layer on the polysilicon layer after forming a polysilicon layer on the insulating film covering the surface of the substrate, and a nitriding atmosphere in the polysilicon layer and the titanium layer. A step of forming a titanium silicide layer that overlaps the polysilicon layer and a titanium nitride layer that overlaps the titanium silicide layer by performing a heat treatment in a photolithography process to form a desired pattern on the titanium nitride layer. In the step of forming a resist layer having the thickness of the resist layer to such an extent that it is sufficient to pattern the stack of the titanium nitride layer and the titanium silicide layer, but not enough to pattern the polysilicon layer. What is set, and the laminated layer is patterned by a dry etching process using the resist layer as a mask. And a part of the polysilicon layer is left by patterning the polysilicon layer by dry etching using the resist layer and the remaining part of the stack as a mask. And a step of removing the resist layer, and a laminate of the remaining portion of the polysilicon layer, the remaining portion of the titanium silicide layer and the remaining portion of the titanium nitride layer is used as a conductive layer for electrodes or wiring. Conductive layer forming method used. 3. A step of forming a polysilicon layer on an insulating film covering a surface of a substrate and then forming a titanium layer on the polysilicon layer, and a nitride atmosphere in the polysilicon layer and the titanium layer. A step of forming a titanium silicide layer that overlaps the polysilicon layer and a titanium nitride layer that overlaps the titanium silicide layer by performing a heat treatment in a photolithography process to form a desired pattern on the titanium nitride layer. Forming a resist layer having, a step of patterning the titanium nitride layer by dry etching treatment using the resist layer as a mask to leave a part of the titanium nitride layer, and after removing the resist layer The dry etching process using the remaining portion of the titanium nitride layer as a mask. Patterning the stack of the tantalum silicide layer and the polysilicon layer to leave a part of the stack, the remaining portion of the polysilicon layer, the remaining portion of the titanium silicide layer, and the titanium nitride layer. A method of forming a conductive layer, wherein a laminate with the remaining portion of is used as a conductive layer for an electrode or a wiring. 4. A step of forming a titanium layer on the polysilicon layer after forming a polysilicon layer on the insulating film covering the surface of the substrate, and a nitride atmosphere in the polysilicon layer and the titanium layer. A step of forming a titanium silicide layer that overlaps the polysilicon layer and a titanium nitride layer that overlaps the titanium silicide layer by performing a heat treatment in a photolithography process to form a desired pattern on the titanium nitride layer. In the step of forming a resist layer having the thickness of the resist layer is sufficient for patterning the titanium nitride layer, but not enough for patterning a stack of the titanium silicide layer and the polysilicon layer. And the titanium layer formed by dry etching using the resist layer as a mask. Patterning the nitride layer to leave a part of the titanium nitride layer remaining; and patterning the stack by dry etching using the resist layer and the remaining part of the titanium nitride layer as a mask. Of the remaining portion of the polysilicon layer, the remaining portion of the titanium silicide layer, and the remaining portion of the titanium nitride layer for electrode or wiring. Of forming a conductive layer to be used as a conductive layer for an automobile.