JPH0855931A - Surface mounting semiconductor mounting device and substrate for surface mounting semiconductor mounting device - Google Patents
Surface mounting semiconductor mounting device and substrate for surface mounting semiconductor mounting deviceInfo
- Publication number
- JPH0855931A JPH0855931A JP20821894A JP20821894A JPH0855931A JP H0855931 A JPH0855931 A JP H0855931A JP 20821894 A JP20821894 A JP 20821894A JP 20821894 A JP20821894 A JP 20821894A JP H0855931 A JPH0855931 A JP H0855931A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor element
- substrate
- wiring
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 熱放散性に優れ、多端子対応ができ、且つ、
低コストで比較的簡単に製造可能で、構造的にも複雑で
ない、表面実装型半導体装置を提供する。
【構成】 貫通孔を有する金属板の全表面を絶縁層によ
り覆った基板を用いて半導体素子を搭載し、樹脂で封止
したプラスチックパッケージであって、前記基板の半導
体素子を搭載した一方の面には、半導体素子を搭載する
ためのダイパッド部と、半導体素子と金属ワイヤーによ
り結線されるボンディングパッド部と、該ボンディング
パッドから前記貫通孔部まで達する配線とを設けてお
り、前記基板の他方の面には、前記配線と接続し、貫通
孔の内部を埋め、且つ外部へ突出した金属製の外部接続
端子を設けている。
(57) [Abstract] [Purpose] It has excellent heat dissipation and can be used with multiple terminals.
(EN) Provided is a surface mount semiconductor device which can be manufactured relatively easily at low cost and which is not structurally complicated. A plastic package in which a semiconductor element is mounted using a substrate in which the entire surface of a metal plate having a through hole is covered with an insulating layer and which is sealed with a resin, wherein one surface of the substrate on which the semiconductor element is mounted is mounted. Is provided with a die pad portion for mounting a semiconductor element, a bonding pad portion that is connected to the semiconductor element by a metal wire, and a wiring that extends from the bonding pad to the through hole portion. The surface is provided with a metal external connection terminal that is connected to the wiring, fills the inside of the through hole, and protrudes to the outside.
Description
【0001】[0001]
【産業上の利用分野】本発明は,樹脂封止型半導体装置
(プラスチックパッケージ)に関し、詳しくは、熱放散
性が優れ、且つ多端子(ピン)化に対応できる面実装型
半導体装置とその基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device (plastic package), and more particularly to a surface-mounted semiconductor device excellent in heat dissipation and capable of coping with multiple terminals (pins) and its substrate. Regarding
【0002】[0002]
【従来の技術】近年、半導体装置は、電子機器の高性能
化と軽薄短小化の傾向(時流)からLSIのASICに
代表されるように、ますます高集積化、高機能化になっ
ている。高集積化、高機能化された半導体装置において
は、信号の高速処理のためには、パッケージ内のインダ
クタンスが無視できない状況になってきて、パッケージ
内のインダクタンスを低減するために、電源、グランド
の接続端子数を多くし、実質的なインダクタンスを下げ
るようにして、対応してきた。この為、半導体装置の高
集積化、高機能化は外部端子(ピン)の総数の増加とな
り、ますます多端子(ピン)化が求められるようになっ
てきた。多端子(ピン)IC、特にゲートアレイやスタ
ンダードセルに代表されるASICあるいは、マイコ
ン、DSP(Digital Signal Proc
essor)等の半導体装置化には、PGA(Pin
Grid Aray)やQFP(Quard Flat
Package)等のピン挿入型、あるいは表面実装
型パッケージが用いられており、PGAでは400ピン
クラスが、QFPでは300ピンクラスのものまでが実
用化に至ってきている。2. Description of the Related Art In recent years, semiconductor devices have become more highly integrated and more functional, as typified by LSI ASICs, due to the trend toward higher performance, lighter, thinner, shorter, and smaller electronic devices (current trends). . In a highly integrated and highly functional semiconductor device, in order to process signals at a high speed, the inductance in the package has become a condition that cannot be ignored, and in order to reduce the inductance in the package, power supply and ground This has been dealt with by increasing the number of connection terminals and reducing the substantial inductance. For this reason, the higher integration and higher functionality of semiconductor devices has led to an increase in the total number of external terminals (pins), and there is an increasing demand for more terminals (pins). Multi-terminal (pin) IC, especially ASIC represented by gate array or standard cell, microcomputer, DSP (Digital Signal Proc)
In order to make semiconductor devices such as essors), PGA (Pin)
Grid Array) and QFP (Quad Flat)
A pin insertion type package such as a package) or a surface mount type package is used, and a PGA of 400 pin class and a QFP of 300 pin class have been put into practical use.
【0003】しかしながら、近年の半導体素子の信号処
理の高速化及び高性能(機能)化は、更に多くの端子を
必要としている。これに対応するには、PGAではパッ
ケージサイズを大きくせざるをえない為、実装効率面で
の低下を招くことになり好ましくない。また、QFPで
は、外部端子ピッチを狭めることにより、更なる多端子
化に対応できるが、外部端子を狭ピッチ化した場合、外
部端子自体の幅も狭める必要があり、外部端子強度が低
下させることとなる。その結果、端子成形(ガルウイン
グ化)の位置精度あるいは平坦精度等において問題を生
じてしまう。また、QFPでは、アウターリードのピッ
チが、0.4mm、0.3mmと更にピッチが狭くなる
につれ、これら狭ピッチの実装工程が難しくなってき
て、高度なボード実装技術を実現せねばならない等の障
害(問題)をかかえている。However, in recent years, the higher speed and higher performance (function) of signal processing of semiconductor devices requires more terminals. In order to deal with this, the PGA has no choice but to increase the package size, which leads to a reduction in mounting efficiency, which is not preferable. Further, in the QFP, the external terminal pitch can be narrowed to cope with a further increase in the number of terminals. However, when the external terminal pitch is narrowed, the width of the external terminal itself must be narrowed, and the external terminal strength is reduced. Becomes As a result, a problem occurs in the positional accuracy or flatness accuracy of terminal molding (gull wing formation). Further, in the QFP, as the pitch of the outer leads is further narrowed to 0.4 mm and 0.3 mm, the mounting process of these narrow pitches becomes difficult, and it is necessary to realize an advanced board mounting technology. Have an obstacle (problem).
【0004】これら従来のPGAやQFP等のパッケー
ジがかかえる実装効率、実装性の問題を回避するため
に、半田ボールをパッケージの外部端子に置き換えた面
実装型パッケージであるBGA(Ball Grid
Array)と呼ばれるプラスチックパッケージが開発
されてきた。このBGAは、入出力端子を増やすため
に、両面配線基板の片面に半導体素子を搭載し、もう一
方の面に球状の半田を取付けた外部端子用電極を設け、
スルー・ホールを通じて半導体素子と外部端子用電極と
の導通をとっていた。球状の半田をアレイ状に並べるこ
とにより、端子ピッチの間隔を従来のリードフレームを
用いた半導体装置より広くすることができ、この結果、
半導体装置の実装工程を難しくせず、入出力端子の増加
に対応できた。BGAは、一般に図7に示すような構造
である。図7(b)は図7(a)の裏面(基板)側から
みた図で図7(c)はスルホール750部を示したもの
である。このBGAはBTレジン(ビスマレイミド系樹
脂)を代表とする耐熱性有する平板(樹脂板)の基材7
02の片面に半導体素子701を搭載するダイパッド7
05と半導体素子701からボンディングワイヤ708
により電気的に接続されるボンディングパッド710を
もち、もう一方の面に、外部回路半導体搭載装置との電
気的、物理的接続を行う格子状あるいは千鳥状に配置さ
れた半田ボールにより形成した外部端子706をもち、
外部接続端子706とボンディングパッド710の間を
配線704とスルーホール750、配線704Aにより
電気的に接続している構造である。この様な耐熱樹脂基
材を用いて構成される、従来型のBGAは、比較的コス
トも安く、多端子実装に対応した半導体装置を実現でき
るものである。 このBGAの場合、半導体素子701
で生じた熱は、半導体素子701、配線704、スルー
ホール750、配線704A、外部端子706を経由し
て外部の配線回路へと伝達される。図7(c)に示すよ
うに基板の中央部ダイバッド705領域のBTレジンに
貫通孔を設け、貫通孔内部に無電解メッキ電解メッキ7
18を施した熱伝導ビア751を設け搭載するプリント
基板にダイレクトに熱を逃がすことで、熱放散性を向上
させている。In order to avoid the problems of the mounting efficiency and mountability of these conventional packages such as PGA and QFP, BGA (Ball Grid) is a surface mounting type package in which solder balls are replaced with external terminals of the package.
Plastic packages called Arrays have been developed. In this BGA, in order to increase the number of input / output terminals, a semiconductor element is mounted on one surface of a double-sided wiring board, and external terminal electrodes provided with spherical solder are provided on the other surface.
Conduction was established between the semiconductor element and the external terminal electrode through the through hole. By arranging the spherical solder in an array, the terminal pitch can be made wider than that of the semiconductor device using the conventional lead frame.
It was possible to cope with an increase in the number of input / output terminals without making the semiconductor device mounting process difficult. BGA generally has a structure as shown in FIG. FIG. 7B is a view seen from the back surface (substrate) side of FIG. 7A, and FIG. 7C shows the through hole 750 portion. This BGA is a base material 7 of a heat-resistant flat plate (resin plate) represented by BT resin (bismaleimide resin).
Die pad 7 on which semiconductor element 701 is mounted on one side of 02
05 and the semiconductor element 701 to the bonding wire 708
External terminals having bonding pads 710 electrically connected to each other by solder balls arranged on the other surface in a grid or zigzag pattern for electrical and physical connection with an external circuit semiconductor mounting device. Has 706,
This is a structure in which the external connection terminal 706 and the bonding pad 710 are electrically connected by the wiring 704, the through hole 750, and the wiring 704A. The conventional BGA configured using such a heat-resistant resin base material is relatively low in cost and can realize a semiconductor device compatible with multi-terminal mounting. In the case of this BGA, the semiconductor element 701
The heat generated in 1 is transmitted to an external wiring circuit via the semiconductor element 701, the wiring 704, the through hole 750, the wiring 704A, and the external terminal 706. As shown in FIG. 7 (c), a through hole is provided in the BT resin in the central portion of the die pad 705 of the substrate, and electroless plating electrolytic plating 7 is performed inside the through hole.
The heat dissipation via is improved by providing the heat conducting via 751 provided with 18 and radiating the heat directly to the mounted printed circuit board.
【0005】[0005]
【発明が解決しようとする課題】上記耐熱性基材(樹脂
板)を用いて構成される従来型のプラスチックBGA
は、搭載した半導体素子とワイヤ結線を行う為の回路形
成と、半導体装置化した後にプリント基板実装する為の
端子形成とが耐熱性基材を挟んで両面に存在することと
なる為、スルーホールを介した両面回路を形成する必要
があり、回路形成が複雑となる。耐熱性基材を用いて構
成されるプラスチックBGA用の基板を製造するための
プロセスは、樹脂基板の孔あけや表裏金属の導通メッキ
処理あるいは、スルーホールのティンディング処理を施
したフオトエッチングといった、工程が必要で、全体と
して長い工程となる。これに加えて、高密度化を実現す
る為の回路形成プロセスには制約が多く、低コストに製
造することが難しい。また、半導体素子の搭載及びワイ
ヤ結線した後に半導体素子搭載面側に樹脂モールドを施
す為、スルホールを樹脂モールドラインよりも外側に配
置形成しなければならない。その為半導体素子から外部
端子に至るまでのリード長さが長くなることに加えて、
スルーホールの加工径サイズが半導体装置自体の大きさ
を律速させることになる等構造上の制約が多い。更に、
耐熱性基材(樹脂板)に孔あけ後、銅メッキ処理を施し
て、形成される熱伝導ビアは半導体素子の直下に対する
熱放散性はある程度良いものの、パッケージ全域に熱拡
散する効果がない為、熱放散性にはまだ問題がある。本
発明は、これらの問題を解決しようとするもので、熱放
散性に優れた、多端子対応のでき、且つ、低コストで比
較的簡単に製造可能な、構造的にも複雑でない、樹脂封
止型の面実装半導体装置を提供するものである。A conventional plastic BGA constructed by using the above heat-resistant base material (resin plate).
Since the circuit formation for wire connection with the mounted semiconductor element and the terminal formation for mounting on the printed circuit board after forming the semiconductor device are present on both sides with the heat resistant base material interposed therebetween, Since it is necessary to form a double-sided circuit via the circuit, the circuit formation becomes complicated. The process for manufacturing a substrate for plastic BGA configured by using a heat-resistant base material is, for example, hole etching of a resin substrate, conductive plating of front and back metals, or photo-etching with tinning of through holes. It requires a process, which is a long process as a whole. In addition to this, there are many restrictions on the circuit forming process for realizing high density, and it is difficult to manufacture at low cost. Further, since the semiconductor element mounting surface side is subjected to resin molding after mounting the semiconductor element and wire connection, the through hole must be arranged and formed outside the resin molding line. Therefore, in addition to increasing the lead length from the semiconductor element to the external terminal,
There are many structural restrictions such that the size of the processed diameter of the through hole limits the size of the semiconductor device itself. Furthermore,
The heat conducting vias formed by drilling holes in a heat resistant base material (resin plate) and then copper plating have good heat dissipation to the area directly under the semiconductor element, but do not have the effect of heat diffusion throughout the package. , Heat dissipation is still a problem. The present invention is intended to solve these problems, is excellent in heat dissipation, can be used for multiple terminals, can be manufactured relatively easily at low cost, and is structurally uncomplicated and resin-sealed. A static-type surface-mount semiconductor device is provided.
【0006】[0006]
【課題を解決するための手段】又、本発明の面実装半導
体搭載装置は、貫通孔を有する金属板の全表面を絶縁層
により覆った基材を用いて回路を形成した基板に半導体
素子を搭載し、樹脂で封止した樹脂封止型半導体装置
(プラスチックパッケージ)であって、前記基板の半導
体素子を搭載した一方の面には、半導体素子を搭載する
ためのダイパッド部と、半導体素子と金属ワイヤーによ
り結線されるボンディングパッド部と、該ボンディング
パッドから前記貫通孔部まで達する配線とを設けてお
り、前記基板の他方の面には、前記配線と接続し、貫通
孔の内部を埋め、且つ外部へ突出した金属製の外部接続
端子を設けていることを特徴とするものである。そし
て、上記において、基材の貫通孔は、半導体素子側が、
面実装半導体搭載装置外側よりも小径であることを特徴
とするものである。。又、上記において、基板は半導体
素子搭載領域内に配線を設け、且つ、前記配線と接続
し、貫通孔の内部を埋め、且つ外部へ突出した金属製の
外部接続端子を設けていることを特徴とするものであ
り、半導体素子は基板の配線上に設けられた絶縁テープ
を介して固定されていることを特徴とするものである。
更に、上記において、外部接続端子側の面に、貫通孔の
内部を埋め、且つ外部へ突出した金属製の放熱用端子を
設けたことを特徴とするものである。本発明の半導体装
置用基板は、貫通孔を有する金属板の全表面を絶縁層に
より覆った基材の片面に、半導体素子を搭載するダイパ
ッド部と、半導体素子と金属ワイヤーにより結線される
ボンディングパッド部と、該ボンディングパッドから前
記貫通孔部まで達する配線とを形成したことを特徴とす
るものである。Further, in a surface mounting semiconductor mounting device of the present invention, a semiconductor element is mounted on a substrate on which a circuit is formed by using a base material in which the entire surface of a metal plate having a through hole is covered with an insulating layer. A resin-sealed semiconductor device (plastic package) mounted and sealed with a resin, wherein one surface of the substrate on which the semiconductor element is mounted has a die pad portion for mounting the semiconductor element, and a semiconductor element. A bonding pad portion connected by a metal wire and a wiring reaching the through hole portion from the bonding pad are provided, the other surface of the substrate is connected to the wiring, and the inside of the through hole is filled, In addition, it is characterized in that a metal external connection terminal protruding to the outside is provided. Then, in the above, the through-hole of the base material, the semiconductor element side,
The feature is that the diameter is smaller than the outside of the surface mounting semiconductor mounting device. . Further, in the above, the substrate is provided with a wiring in the semiconductor element mounting region, and is provided with a metal external connection terminal that is connected to the wiring, fills the inside of the through hole, and projects to the outside. The semiconductor device is characterized by being fixed via an insulating tape provided on the wiring of the substrate.
Further, in the above, the surface of the external connection terminal side is provided with a metal heat radiating terminal that fills the inside of the through hole and projects to the outside. The substrate for a semiconductor device of the present invention includes a die pad portion on which a semiconductor element is mounted, and a bonding pad connected to the semiconductor element and a metal wire on one surface of a base material in which the entire surface of a metal plate having a through hole is covered with an insulating layer. And a wiring that extends from the bonding pad to the through hole portion are formed.
【0007】[0007]
【作用】本発明の面実装半導体搭載装置は、上記のよう
な構成にすることにより、熱放散性の優れた、多端子
(ピン)対応のできるもので、且つ、低コストで作製の
できる簡単な構造としている。また、基材の貫通孔の径
を半導体素子搭載側で小とすることにより、配線の引回
しエリアを大きくとれ、配線の自由度を上げている。更
に、半導体素子の領域に、配線を設け、且つ、そこから
貫通孔の内部を埋め、且つ外部へ突出した金属製の外部
接続端子へと接続させることにより、ボンディングパッ
トより外側に位置する貫通孔(外部端子)の数により、
半導体搭載装置の端子(ピン)数が制限されることはな
く、半導体搭載装置の端子(ピン)数の制限は大幅に緩
和される。又、外部へ突出した金属製の外部接続端子と
同様な構造の放熱用の接続端子を設けていることに熱放
散性を一層良いものとしている。又、本発明の半導体装
置用基板は、上記のような構成にすることにより、従来
のスルホール付き耐熱性基板(樹脂基板)からなる両面
配線回路基板に比べ、製造プロセスを簡略化でき、且つ
安価なものとしている。そして、従来の両面配線回路基
板のようにスルーホールを設ける必要がなく、スルホー
ル位置により制約をうけない為、半導体装置自体の小型
化に大きく寄与できる。金属板をコアとしている為、半
導体素子を搭載した場合には、熱放散性の高いものとし
ているThe surface-mounting semiconductor mounting device of the present invention, having the above-mentioned structure, is excellent in heat dissipation and capable of supporting multiple terminals (pins), and can be easily manufactured at low cost. It has a different structure. Further, by making the diameter of the through hole of the base material small on the semiconductor element mounting side, a large wiring area can be secured and the degree of freedom of wiring is increased. Further, by providing wiring in the region of the semiconductor element, filling the inside of the through hole from there, and connecting to the external connection terminal made of metal protruding to the outside, the through hole positioned outside the bonding pad is formed. Depending on the number of (external terminals)
The number of terminals (pins) of the semiconductor mounting device is not limited, and the limitation of the number of terminals (pins) of the semiconductor mounting device is greatly relaxed. Further, the heat dissipation property is further improved by providing the connection terminal for heat dissipation, which has the same structure as the external connection terminal made of metal and protruding to the outside. In addition, the semiconductor device substrate of the present invention can be simplified in manufacturing process and is less expensive than the conventional double-sided wiring circuit substrate made of a heat-resistant substrate with through holes (resin substrate) by the above-mentioned configuration. It is supposed to be. Further, unlike the conventional double-sided wiring circuit board, there is no need to provide through holes, and there are no restrictions on the positions of through holes, which can greatly contribute to the miniaturization of the semiconductor device itself. Since a metal plate is used as a core, it has high heat dissipation when a semiconductor element is mounted.
【0008】[0008]
【実施例】本発明の面実装半導体搭載装置の第一の実施
例を以下、図にそって説明する。図1(a)は実施例の
面実装半導体搭載装置の内部構造を示す要部斜視図で、
図1(b)は外部接続端子部における断面図であり、図
2(a)は配線部を含む断面図で、図2(b)はボンデ
ィングパッド部を示す斜視図、図2(c)は貫通孔部の
斜視断面図である。図1中、100は面実装半導体搭載
装置、101は半導体、102は基板、103はモール
ドレジン(樹脂)、104は配線、105はダイパッ
ド、106は外部接続端子との配線接続部、106Aは
外部接続端子、107は放熱用端子との配線接続部、1
07Aは放熱用接続端子、108はボンディングワイ
ヤ、110はボンディングパッド、111はパイロット
ホールである。本実施例の面実装半導体搭載装置は、基
板102の半導体素子101側の面に、半導体素子10
1を搭載するダイパッド部105と半導体素子101と
ボンディングワイヤー108により結線されるボンデイ
ングパッド部110と、ボンディングパッド110から
外部接続端子との配線接続部106まで達する配線10
4を設けている。そして、基板102の他方の面には、
基板102の貫通孔の内部から半導体搭載装置100の
外側に突出するように一体となった金属製の外部接続端
子106Aとを設け、外部接続端子との配線接続部10
6と接続させている。また、必要に応じて、基板102
の半導体素子101側に、放熱用端子への配線接続部1
07(図示していない)を設けておき、外部接続端子と
の配線接続部106と同様に、基板102の貫通孔の内
部から半導体搭載装置100の外側に突出するように一
体となった金属製の放熱用端子107Aとを接続させ
る。半導体素子101と外部回路とは、半導体素子の端
子部、ボンディングワヤイヤ108、配線104、外部
接続端子との配線接続部106、外部接続端子106
A、外部回路端末の順に接続されている。基板102は
金属平板120をコアとするもので、図2(a)のよう
に、その両面は絶縁層121で覆われており、この絶縁
層上に配線104やボンディングパッド110が設けら
れている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a surface mount semiconductor mounting device of the present invention will be described below with reference to the drawings. FIG. 1A is a perspective view of an essential part showing an internal structure of a surface mount semiconductor mounting device according to an embodiment.
1B is a sectional view of an external connection terminal portion, FIG. 2A is a sectional view including a wiring portion, FIG. 2B is a perspective view showing a bonding pad portion, and FIG. It is a perspective sectional view of a through-hole portion. In FIG. 1, 100 is a surface mount semiconductor mounting device, 101 is a semiconductor, 102 is a substrate, 103 is a mold resin (resin), 104 is wiring, 105 is a die pad, 106 is a wiring connection portion with an external connection terminal, and 106A is external. Connection terminal, 107 is a wiring connection portion with the heat dissipation terminal, 1
Reference numeral 07A is a heat dissipation connection terminal, 108 is a bonding wire, 110 is a bonding pad, and 111 is a pilot hole. In the surface mounting semiconductor mounting device of this embodiment, the semiconductor element 10 is provided on the surface of the substrate 102 on the semiconductor element 101 side.
1. The die pad portion 105 on which the semiconductor integrated circuit 1 is mounted, the semiconductor element 101 and the bonding pad portion 110 connected by the bonding wire 108, and the wiring 10 that reaches the wiring connection portion 106 from the bonding pad 110 to the external connection terminal.
4 is provided. Then, on the other surface of the substrate 102,
A metal external connection terminal 106A integrally formed so as to project from the inside of the through hole of the substrate 102 to the outside of the semiconductor mounting device 100 is provided, and the wiring connection portion 10 with the external connection terminal is provided.
6 is connected. In addition, if necessary, the substrate 102
On the semiconductor element 101 side of the wiring connection portion 1 to the heat dissipation terminal
07 (not shown) is provided and is made of an integrated metal so as to project from the inside of the through hole of the substrate 102 to the outside of the semiconductor mounting device 100, similarly to the wiring connecting portion 106 with the external connection terminal. The heat radiating terminal 107A is connected. The semiconductor element 101 and the external circuit include a terminal portion of the semiconductor element, a bonding wire 108, a wiring 104, a wiring connection portion 106 with an external connection terminal, and an external connection terminal 106.
A and the external circuit terminal are connected in this order. The substrate 102 has a metal flat plate 120 as a core, and both surfaces thereof are covered with an insulating layer 121 as shown in FIG. 2A, and the wiring 104 and the bonding pad 110 are provided on this insulating layer. .
【0009】ボンディングパッド110部には図2
(a)に示すように、金属箔124のソルダーレジスト
125(東京応化工業株式会社製、OPSR−5600
エポキシアクリレール)に覆われていない部分のみ無
電解メッキにより金がめっきされており、ここで、半導
体素子101の端子(パッド)とワイヤボンディングが
なされている。ボンディングパッド110部以外の、配
線104、外部接続端子との配線接続部106の金属箔
124は、ソルダーレジスト125覆われている。The bonding pad 110 is shown in FIG.
As shown in (a), the solder resist 125 of the metal foil 124 (manufactured by Tokyo Ohka Kogyo Co., Ltd., OPSR-5600) is used.
Gold is plated by electroless plating only in the portion not covered with the epoxy acryl rail, and here, the terminals (pads) of the semiconductor element 101 are wire-bonded. Except for the bonding pad 110, the wiring 104 and the metal foil 124 of the wiring connecting portion 106 to the external connection terminal are covered with the solder resist 125.
【0010】基板102の貫通孔部は、図2(b)に示
すように、基板の両面を絶縁する絶縁層121で貫通孔
部表面全体は覆われており、絶縁層上に形成された金属
箔124からなる外部接続端子との配線接続部106
は、貫通孔部を埋め、面実装半導体搭載装置100の外
側へ突出した金属からなる外部接続端子106Aに接続
している。As shown in FIG. 2B, the through-hole portion of the substrate 102 is covered with an insulating layer 121 that insulates both surfaces of the substrate, and the entire surface of the through-hole portion is covered with a metal formed on the insulating layer. Wiring connection section 106 with external connection terminal made of foil 124
Is connected to the external connection terminal 106 </ b> A made of a metal that fills the through hole and projects to the outside of the surface-mounting semiconductor mounting device 100.
【0011】本実施例の面実装半導体搭載装置は、この
ように、金属平板120をコアとした基板を用いてお
り、熱放散性が極めてよく、半導体素子101が搭載さ
れた面とは反対側の面全体に、基板102の貫通孔内か
ら一体となって外部へ突出するように設けられた金属か
らなる外部接続端子106Aを設けており、多端子(ピ
ン)化に対応できる構造である。又、外部接続端子10
6A側の面に放熱用端子107Aを設けていることに熱
放散性を一層良いものとしている。As described above, the surface-mounting semiconductor mounting device of this embodiment uses the substrate having the metal flat plate 120 as a core, has an excellent heat dissipation property, and is opposite to the surface on which the semiconductor element 101 is mounted. The external connection terminal 106A made of metal is provided on the entire surface of the substrate so as to integrally project from the through hole of the substrate 102 to the outside, and the structure is compatible with the increase in the number of terminals (pins). Also, the external connection terminal 10
The heat dissipation property is further improved by providing the heat dissipation terminal 107A on the surface of the 6A side.
【0012】次に、本発明の面実装半導体搭載装置の第
二の実施例をあげる。図3(a)は本実施例面実装半導
体搭載装置の内部構造を示す要部斜視図で、図3(b)
はその半導体素子を含む断面図である。図3中、301
は半導体素子、302は基板、303はモールドレジン
(樹脂)、304、303bは配線、306は外部接続
端子との配線接続部、306Aは外部接続端子、308
はボンディングワイヤ、310はボンディングパッド、
311はバイロットホール、320金属平板、321は
絶縁層、322は絶縁テープである。本実施例の面実装
半導体搭載装置は、配線303b、外部接続端子との配
線接続部306を基板302の半導体素子301のある
領域にも設け、外部接続端子との配線接続部306を介
して、外部接続端子306Aへと接続するものである。
第一の実施例が、ボンディングパットより外側に位置す
る貫通孔(外部端子)の数により、半導体搭載装置の端
子(ピン)数が制限されていたが、本実施例の場合は、
基板302の半導体素子301搭載領域からも端子(ピ
ン)をとることができ、半導体搭載装置の端子(ピン)
数の制限は大幅に緩和される。Next, a second embodiment of the surface mount semiconductor mounting device of the present invention will be described. FIG. 3A is a perspective view of an essential part showing the internal structure of the surface mount semiconductor mounting device according to the present embodiment, and FIG.
FIG. 3 is a cross-sectional view including the semiconductor element. 301 in FIG.
Is a semiconductor element, 302 is a substrate, 303 is a mold resin (resin), 304 and 303b are wiring, 306 is a wiring connection portion with an external connection terminal, 306A is an external connection terminal, 308
Is a bonding wire, 310 is a bonding pad,
Reference numeral 311 is a bilot hole, 320 is a metal flat plate, 321 is an insulating layer, and 322 is an insulating tape. In the surface mount semiconductor mounting device of the present embodiment, the wiring 303b and the wiring connection portion 306 for the external connection terminal are also provided in a region of the substrate 302 where the semiconductor element 301 is provided, and the wiring connection portion 306 for the external connection terminal is provided. It connects to the external connection terminal 306A.
In the first embodiment, the number of terminals (pins) of the semiconductor mounted device was limited by the number of through holes (external terminals) located outside the bonding pad, but in the case of this embodiment,
Terminals (pins) can be taken from the semiconductor element 301 mounting area of the substrate 302, and terminals (pins) of the semiconductor mounting device can be obtained.
The number limit is greatly relaxed.
【0013】本実施例の面実装半導体搭載装置は、図3
(b)に示すように、配線304b、外部接続端子との
配線接続部306と半導体素子301の間に絶縁テープ
322を設けることにより、このような構造を可能にし
ている。絶縁テープ322としては、ポリイミドテープ
の両面にシリコン変性ポリイミドからなる接着材層を設
けた半導体素子接着用のテープ(住友ベークライト製の
ITA−1030)等がある。本実施例は、第一の実施
例より更に、多端子(ピン)化に適した構造と言える。The surface mount semiconductor mounting device of this embodiment is shown in FIG.
As shown in (b), such a structure is made possible by providing the insulating tape 322 between the wiring 304b, the wiring connecting portion 306 to the external connection terminal, and the semiconductor element 301. As the insulating tape 322, there is a tape for adhering semiconductor elements (ITA-1030 manufactured by Sumitomo Bakelite), which has adhesive layers made of silicon-modified polyimide provided on both sides of a polyimide tape. It can be said that the present embodiment has a structure more suitable for the number of terminals (pins) than the first embodiment.
【0014】次いで、本発明の面実装半導体装置の第三
の実施例を挙げる。図4(a)は本実施例面実装半導体
装置の外部接続端子部の断面図であり、図4(b)は実
施例1や実施例2における外部接続端子部の断面図であ
る。図4中、402は基板、404は配線、406は外
部接続端子との配線接続部、406Aは外部接続端子、
420は金属平板、421は絶縁層である。本実施例の
場合、接続用端子406Aを設ける貫通孔の基板402
の配線403側(半導体素子搭載側)の孔径は小とし、
反対側の孔径は略、第一の実施例、第二の実施例と同様
に大きい孔径としている。この為、配線の引回しエリア
が増すこととなり、配線の自由度が増し、配線数を増や
すことが可能となる。Next, a third embodiment of the surface mount semiconductor device of the present invention will be described. FIG. 4A is a sectional view of the external connection terminal portion of the surface mounting semiconductor device of this embodiment, and FIG. 4B is a sectional view of the external connection terminal portion of the first and second embodiments. In FIG. 4, reference numeral 402 is a substrate, 404 is wiring, 406 is a wiring connection portion with an external connection terminal, 406A is an external connection terminal,
Reference numeral 420 is a metal flat plate, and 421 is an insulating layer. In the case of the present embodiment, the through-hole substrate 402 provided with the connection terminal 406A
The hole diameter on the wiring 403 side (semiconductor element mounting side) should be small,
The hole diameter on the opposite side is substantially the same as that of the first and second embodiments. For this reason, the wiring routing area is increased, the degree of freedom of wiring is increased, and the number of wirings can be increased.
【0015】次に、実施例の面実装半導体搭載装置の製
造方法を簡単に説明する。先ず、図5(a)に示すよう
な、多数の貫通孔530(とパイロットホール511)
を有する形状の42合金(42%Ni−鉄合金)からな
る金属平板520を用いて、厚さ5〜10μmの粘着性
あるいは接着性を有する絶縁層521を全面コーテイン
グした基材502Aを用意した。基材502Aの貫通孔
530部の表面も絶縁層521で覆われている。貫通孔
530の形状を図5(c)に示す。図5(c)(イ)の
半導体素子側が小孔となっているのは、第三の実施例の
もので、図5(c)(ロ)の半導体素子側と外部が同じ
孔径となっているのが、第一、第二の実施例のものであ
る。次に、基材502Aの一方の面に厚さ18μmの金
属箔(銅箔)524を積層し、図5(b)に示すよう
な、断面を持つ基材502Bを作製した。次いで、金属
箔(銅箔)524部を製版エッチングして、金属箔パタ
ーン524Aからなる、半導体素子搭載のためのダイパ
ッドや、ボンディングパッド、配線部、外部接続端子と
の接続用端子部を作製した。次いで、ダイパッドとボン
ディングパッド領域を除く基材502Bの半導体素子搭
載する面側の表面は厚さ20μmのソルダーレジストで
表面を被膜した後、ダイパッド、ボンディングパッド領
域には下地ニッケルメッキを施し、電解金メッキを行い
基板502を得た。尚、電解金メッキに代え無電解金、
あるいは、電解パラジウム、無電解パラジウムメッキを
行っても良い。次いで、このようにして作製された基板
を用い、半導体素子を基板のダイパッド部へダイボンデ
ィングして搭載し、半導体素子のパッドと基板のボンデ
ィングパッドとをワイボンディングにて結線した。この
後、封止用レジン(エポキシ樹脂、日東電工株式会社
製、np−190))にて半導体素子と配線等をモール
ドした後、半導体素子搭載側とは反対の面側から、片面
ティンディングされた貫通孔部に半田ボールを搭載する
かあるいは、半田ペーストをスクリーン印刷した後、溶
解して、基板の貫通孔部内部から半導体装置の外側に突
出した球状の半田ボールを形成して、本実施例の面実装
半導体搭載装置を作製した。Next, a method of manufacturing the surface mount semiconductor mounting device of the embodiment will be briefly described. First, as shown in FIG. 5A, a large number of through holes 530 (and pilot holes 511) are formed.
Using a metal flat plate 520 made of a 42 alloy (42% Ni-iron alloy) having a shape of, a substrate 502A having a thickness of 5 to 10 μm coated with an insulating layer 521 having adhesiveness or adhesiveness was prepared. The surface of the through hole 530 portion of the base material 502A is also covered with the insulating layer 521. The shape of the through hole 530 is shown in FIG. The small hole on the semiconductor element side in FIGS. 5 (c) and (a) is in the third embodiment, and the hole diameter is the same on the outside and the semiconductor element side in FIGS. 5 (c) and (b). These are those of the first and second embodiments. Next, a metal foil (copper foil) 524 having a thickness of 18 μm was laminated on one surface of the base material 502A to produce a base material 502B having a cross section as shown in FIG. 5 (b). Next, 524 parts of the metal foil (copper foil) were subjected to plate-making etching to prepare a die pad for mounting a semiconductor element, a bonding pad, a wiring part, and a terminal part for connection with an external connection terminal, which is composed of the metal foil pattern 524A. . Next, the surface of the base material 502B other than the die pad and the bonding pad area on the side on which the semiconductor element is mounted is coated with a solder resist having a thickness of 20 μm, and then the die pad and the bonding pad area are plated with nickel on the base and electroplated with gold. Then, a substrate 502 was obtained. In addition, instead of electrolytic gold plating, electroless gold,
Alternatively, electrolytic palladium or electroless palladium plating may be performed. Next, using the substrate manufactured in this manner, the semiconductor element was mounted on the die pad portion of the substrate by die bonding, and the pad of the semiconductor element and the bonding pad of the substrate were connected by the wi bonding. After that, a semiconductor element and wiring are molded with a sealing resin (epoxy resin, manufactured by Nitto Denko Corporation, np-190), and then one side is tied from the side opposite to the side on which the semiconductor element is mounted. The solder balls are mounted on the through holes, or the solder paste is screen-printed and then melted to form spherical solder balls protruding from the inside of the through holes of the substrate to the outside of the semiconductor device. An example surface mount semiconductor mounting device was produced.
【0016】次に、実施例の面実装半導体搭載装置に用
いられた基板の作製方法について、図6の工程図に基づ
いて、詳しく説明する。 先ず、板厚0.125mmの42合金(42%Ni−鉄
合金)の金属コイルに、エッチングプロセスにより、直
径0.5mmの貫通孔を1mm間隔で格子状に形成し
た。(A) 次に粘着性あるいは接着性を有する絶縁樹脂を貫通孔が
形成された金属コイルの全表面に形成し、基板の作製を
行なった。(B) この工程は、N,N−ジメチルホルムアミド135部、
P−フエニレジアミン5部、ピロメリット酸二無水物1
0部、トリエチルアミン3部からなる混合液と、メタノ
ールを1:1に混合した電着液中に、金属コイルを浸漬
し、50mmの間隔に設置したステンレス製の電極板を
陰極に、金属コイルを陽極になるように50Vの電圧を
10分間印加することで、金属コイルの全表面にポリア
ミック酸薄膜からなる絶縁層を形成した。片面の絶縁層
上に熱圧着あるいはラミネートすることにより厚さ18
μmの銅を成分とする金属箔を接着した。このとき、基
板は、絶縁層、金属板、絶縁層、金属箔の4層構造とな
っている。Next, a method of manufacturing the substrate used in the surface mount semiconductor mounting device of the embodiment will be described in detail with reference to the process chart of FIG. First, through-etching processes were used to form through holes having a diameter of 0.5 mm in a grid pattern at 1 mm intervals in a metal coil of 42 alloy (42% Ni-iron alloy) having a plate thickness of 0.125 mm. (A) Next, an insulating resin having adhesiveness or adhesiveness was formed on the entire surface of the metal coil in which the through holes were formed, and a substrate was manufactured. (B) This step comprises 135 parts of N, N-dimethylformamide,
P-phenylenediamine 5 parts, pyromellitic dianhydride 1
A metal coil was immersed in an electrodeposition solution in which 0 parts and 3 parts of triethylamine and 1: 1 of methanol were mixed, and a stainless steel electrode plate placed at a 50 mm interval was used as a cathode and a metal coil was used. By applying a voltage of 50 V for 10 minutes so as to serve as an anode, an insulating layer made of a polyamic acid thin film was formed on the entire surface of the metal coil. The thickness of 18 is obtained by thermocompression bonding or laminating on the insulating layer on one side.
A metal foil containing copper having a thickness of μm was bonded. At this time, the substrate has a four-layer structure including an insulating layer, a metal plate, an insulating layer, and a metal foil.
【0017】次に配線、ダイパッド、ボンディングパッ
ドの形成をおこなった。基板の両面に旭化成製のドライ
フイルムAQ−2536のラミネートをおこなった。
(C) 配線、ダイパッドボンディングパッドの形状をフオトマ
スクを用いて、露光、現像を行いレジストパターン膜を
形成し、このレジストパターン膜を耐腐蝕膜としてエッ
チングにより金属箔パターンの形成を行った。この後、
レジストの剥離を行い、配線の形成工程を終了した。
(D) 次に以下のようにしてダイパッド、ボンディングパッド
部に無電解メッキを行っい所望の面実装半導体装置搭載
用基板を得た。(E) 基板の配線を形成した面に、東京応化工業株式会社製ソ
ルダーレジスト(OPSR−5600 エポキシアクリ
レール)を15μmの厚さでスクリーン印刷にて塗布
し、露光後、現像を行った後に、150°Cのキュアを
行い、,ダイパッド、ボンディングパッドを除く表面に
ソルダーレジストを形成し、無電解ニッケルメッキでダ
イパッド、ボンディングパッドに膜厚3μmのニッケル
膜を形成した後、奥野製薬工業株式会社製無電解パラジ
ウム−リンメッキ液「ムデン−ノーブルPD」により膜
厚0.2μmのパラジウム膜を形成した。Next, wiring, die pads, and bonding pads were formed. Lamination of Asahi Kasei's dry film AQ-2536 was performed on both surfaces of the substrate.
(C) Wiring and die pad The shape of the bonding pad was exposed and developed using a photomask to form a resist pattern film, and the resist pattern film was used as a corrosion resistant film to form a metal foil pattern by etching. After this,
The resist was stripped off, and the wiring formation process was completed.
(D) Next, electroless plating was performed on the die pad and the bonding pad portion in the following manner to obtain a desired surface mounting semiconductor device mounting substrate. (E) A solder resist (OPSR-5600 epoxy acryl rail) manufactured by Tokyo Ohka Kogyo Co., Ltd. is applied to the surface of the substrate on which the wiring is formed by screen printing in a thickness of 15 μm, and after exposure and development, After curing at 150 ° C, a solder resist is formed on the surface excluding the die pad and the bonding pad, and a nickel film with a thickness of 3 μm is formed on the die pad and the bonding pad by electroless nickel plating. A palladium film having a thickness of 0.2 μm was formed by an electroless palladium-phosphorus plating solution “Mudden-Noble PD”.
【0018】[0018]
【発明の効果】本発明は、以上のように、熱放散性に優
れ、多端子(ピン)化に対応できる表面実装型半導体搭
載装置の提供を可能とするものであり、詳しくは、従来
のBGA(ボール・グリッド・アレイ)におけるスルホ
ールを用いた複雑な構造のものでなく、比較的簡単な構
造で、且つ安価に製造できるBGA(ボール・グリッド
・アレイ)の提供を可能とするものである。結局、半導
体素子の高集積化、高機能化に対応できる、面実装型半
導体搭載装置の提供を可能としている。As described above, the present invention makes it possible to provide a surface mount type semiconductor mounting device which is excellent in heat dissipation and can cope with the increase in the number of terminals (pins). It is possible to provide a BGA (ball grid array) that is not a complicated structure using through holes in a BGA (ball grid array) but has a relatively simple structure and can be manufactured at low cost. . In the end, it is possible to provide a surface-mounting type semiconductor mounting device which can cope with high integration and high functionality of semiconductor elements.
【図1】本発明の面実装半導体搭載装置の第一の実施例
図FIG. 1 is a diagram of a first embodiment of a surface mount semiconductor mounting device of the present invention.
【図2】本発明の面実装半導体搭載装置の第一の実施例
における要部の概略図FIG. 2 is a schematic view of a main part in a first embodiment of a surface mount semiconductor mounting device of the present invention.
【図3】本発明の面実装半導体搭載装置の第二の実施例
図FIG. 3 is a diagram of a second embodiment of a surface mount semiconductor mounting device of the present invention.
【図4】本発明の面実装半導体搭載装置の第三の実施例
図FIG. 4 is a diagram of a third embodiment of a surface mount semiconductor mounting device of the present invention.
【図5】本発明の面実装半導体搭載装置用基板図FIG. 5 is a substrate diagram for a surface mount semiconductor mounting device of the present invention.
【図6】本発明の面実装半導体搭載装置用基板の製造工
程図FIG. 6 is a manufacturing process diagram of a substrate for a surface-mounted semiconductor mounting device of the present invention.
【図7】従来のBGA(Ball Grid Arra
y)を説明するための図FIG. 7: Conventional BGA (Ball Grid Arra)
Figure for explaining y)
100 表面実装型半
導体装置 101 、301 半導体素子 102 、302 、402 基板 103 モールドレジ
ン(樹脂) 104 、304 、304b、404 配線 105 ダイパット 106 、306 、406 外部接続端子
との配線接続部 106A、306A、406A 外部接続端子 107 放熱用端子と
の配線接続部 107A 放熱用接続端
子 108 ボンディング
ワイヤ 110 ボンディング
パッド 111 パイロットホ
ール 120 、320 、420 金属平板 121 、321 、421 絶縁層 124 金属箔 125 ソルダーレジ
スト 322 絶縁テープ 502A、502B 基材 511 パイロットホ
ール 520 金属平板 521 絶縁層 524 金属箔(銅
箔) 530 貫通孔 701 半導体素子 702 基材 703 モールドレジ
ン(樹脂) 704、704A 配線 705 ダイパッド 706A 外部接続端子 708 ボンディング
ワイヤ 710 ボンディング
パッド 718 メッキ部 724 金属箔 750 スルーホール 751 熱伝導ビア100 surface mount type semiconductor device 101, 301 semiconductor element 102, 302, 402 substrate 103 mold resin (resin) 104, 304, 304b, 404 wiring 105 die pad 106, 306, 406 wiring connecting portion 106A, 306A with external connection terminal 406A External connection terminal 107 Wiring connection portion with heat dissipation terminal 107A Heat dissipation connection terminal 108 Bonding wire 110 Bonding pad 111 Pilot hole 120, 320, 420 Metal flat plate 121, 321, 421 Insulation layer 124 Metal foil 125 Solder resist 322 Insulation tape 502A, 502B Base material 511 Pilot hole 520 Metal flat plate 521 Insulating layer 524 Metal foil (copper foil) 530 Through hole 701 Semiconductor element 702 Base material 703 Mold resin ( Resin) 704, 704A Wiring 705 Die pad 706A External connection terminal 708 Bonding wire 710 Bonding pad 718 Plated part 724 Metal foil 750 Through hole 751 Thermal conduction via
Claims (6)
により覆った基材を用い回路を形成した基板に半導体素
子を搭載し、樹脂で封止した樹脂封止型半導体装置であ
って、前記基板の半導体素子を搭載した一方の面には、
半導体素子を搭載するためのダイパッド部と、半導体素
子と金属ワイヤーにより結線されるボンディングパッド
部と、該ボンディングパッドから前記貫通孔部まで達す
る配線とを設けており、前記基板の他方の面には、前記
配線と接続し、貫通孔の内部を埋め、且つ外部へ突出し
た金属製の外部接続端子を設けていることを特徴とする
面実装半導体搭載装置。1. A resin-encapsulated semiconductor device in which a semiconductor element is mounted on a substrate on which a circuit is formed by using a base material in which an entire surface of a metal plate having a through hole is covered with an insulating layer and which is sealed with a resin. , On one surface of the substrate on which the semiconductor element is mounted,
A die pad portion for mounting a semiconductor element, a bonding pad portion connected to the semiconductor element by a metal wire, and a wiring reaching from the bonding pad to the through hole portion are provided, and the other surface of the substrate is provided. A surface-mounted semiconductor mounting device comprising: a metal external connection terminal that is connected to the wiring, fills the inside of the through hole, and projects to the outside.
導体素子側が、面実装半導体搭載装置外側よりも小径で
あることを特徴とする面実装半導体搭載装置。2. The surface mounting semiconductor mounting device according to claim 1, wherein the through hole of the base material has a smaller diameter on the semiconductor element side than on the outside of the surface mounting semiconductor mounting device.
体素子搭載領域内に配線を設け、且つ、前記配線と接続
し、貫通孔の内部を埋め、且つ外部へ突出した金属製の
外部接続端子を設けていることを特徴とする面実装半導
体搭載装置。3. The external connection terminal according to claim 1, wherein the substrate is provided with a wiring in a semiconductor element mounting region and is connected to the wiring, fills the inside of the through hole, and projects to the outside. A surface mount semiconductor mounting device characterized by being provided with.
配線上に設けられた絶縁テープを介して固定されている
ことを特徴とする面実装半導体搭載装置。4. The surface mount semiconductor mounting device according to claim 3, wherein the semiconductor element is fixed via an insulating tape provided on the wiring of the substrate.
子側の面に、貫通孔の内部を埋め、且つ外部へ突出した
金属製の放熱用端子を設けたことを特徴とする面実装半
導体搭載装置。5. The surface mount semiconductor mounting device according to claim 1, wherein the surface of the external connection terminal side is provided with a metal radiating terminal that fills the inside of the through hole and projects to the outside. apparatus.
により覆った基材の片面に、半導体素子を搭載するダイ
パッド部と、半導体素子と金属ワイヤーにより結線され
るボンディングパッド部と、該ボンディングパッドから
前記貫通孔部まで達する配線とを形成したことを特徴と
する面実装装半導体搭載装置用基板。6. A die pad portion on which a semiconductor element is mounted, a bonding pad portion connected to the semiconductor element by a metal wire, and a bonding pad portion on one side of a base material in which the entire surface of a metal plate having a through hole is covered with an insulating layer. A substrate for a surface mounting semiconductor mounting device, characterized in that a wiring reaching from the bonding pad to the through hole portion is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20821894A JPH0855931A (en) | 1994-08-10 | 1994-08-10 | Surface mounting semiconductor mounting device and substrate for surface mounting semiconductor mounting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20821894A JPH0855931A (en) | 1994-08-10 | 1994-08-10 | Surface mounting semiconductor mounting device and substrate for surface mounting semiconductor mounting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0855931A true JPH0855931A (en) | 1996-02-27 |
Family
ID=16552635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20821894A Pending JPH0855931A (en) | 1994-08-10 | 1994-08-10 | Surface mounting semiconductor mounting device and substrate for surface mounting semiconductor mounting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0855931A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210770A (en) * | 2005-01-31 | 2006-08-10 | Toppan Printing Co Ltd | Semiconductor device mounting substrate and BGA package for semiconductor element |
| US7543377B2 (en) | 1996-03-28 | 2009-06-09 | Intel Corporation | Perimeter matrix ball grid array circuit package with a populated center |
-
1994
- 1994-08-10 JP JP20821894A patent/JPH0855931A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7543377B2 (en) | 1996-03-28 | 2009-06-09 | Intel Corporation | Perimeter matrix ball grid array circuit package with a populated center |
| JP2011160009A (en) * | 1996-03-28 | 2011-08-18 | Intel Corp | Method of reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the same |
| JP2014187410A (en) * | 1996-03-28 | 2014-10-02 | Intel Corp | Method for reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the board |
| JP2006210770A (en) * | 2005-01-31 | 2006-08-10 | Toppan Printing Co Ltd | Semiconductor device mounting substrate and BGA package for semiconductor element |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6025640A (en) | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device | |
| JP2002343899A (en) | Substrate for semiconductor package, semiconductor package | |
| JPH11340365A (en) | Insulating wiring board and resin-sealed semiconductor device | |
| JP2000299423A (en) | Lead frame, semiconductor device using the same, and method of manufacturing the same | |
| JP2002118204A (en) | Semiconductor device, semiconductor mounting substrate and method of manufacturing the same | |
| JPH11163024A (en) | Semiconductor device, lead frame for assembling the same, and method of manufacturing semiconductor device | |
| JP3513983B2 (en) | Manufacturing method of chip carrier | |
| JP3529915B2 (en) | Lead frame member and method of manufacturing the same | |
| JPH0855931A (en) | Surface mounting semiconductor mounting device and substrate for surface mounting semiconductor mounting device | |
| JPH08330356A (en) | Anisotropic conductive sheet with conductor layer and wiring board using the same | |
| JP3576228B2 (en) | Surface mount type semiconductor device | |
| JP3297959B2 (en) | Semiconductor device | |
| JPH09116045A (en) | BGA type resin-sealed semiconductor device using lead frame and manufacturing method thereof | |
| JP3992877B2 (en) | Manufacturing method of resin-encapsulated semiconductor device | |
| CN101958292A (en) | Printed circuit board, encapsulation piece and manufacture methods thereof | |
| JPH08139259A (en) | Lead frame, lead frame member, and surface mount semiconductor device using the same | |
| JP2612468B2 (en) | Substrate for mounting electronic components | |
| JP4622181B2 (en) | Manufacturing method of electronic component mounting board | |
| JP2652222B2 (en) | Substrate for mounting electronic components | |
| KR101168890B1 (en) | Leadframe and method of manufacturig same | |
| JPH08330472A (en) | Semiconductor device and manufacturing method thereof | |
| JP2872531B2 (en) | Semiconductor module substrate and semiconductor device using the same | |
| JP2003338579A (en) | Wiring board with heat sink | |
| JPH04119653A (en) | Integrated circuit element | |
| JP3403221B2 (en) | Lead frame with wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20030128 |