JPH0863593A - Method and device for 90-degree-rotation processing of image data - Google Patents

Abstract

PURPOSE: To provide a method and a device for the 90-degree rotation processing of an image for outputting inputted digital image data after 90- degree-rotation processing it at high speed. CONSTITUTION: In the case that image data written in an image memory is read out by using one image memory, a read-out address is designated so that the image is rotated by 90 degrees. Then, the image data to be inputted subsequently is written in the designated read-out address. The designated address of the image memory determines the storage address of a following original from a relative position with the storage address of a preceding original. Namely, when the horizontal scanning direction and the vertical scanning direction of the image memory are made a and b respectively, an access address is expressed by the multiple of the multiplier of (a), and in addition, if the address exceeds (ab-1), the residue of the division of the address by (ab-1) becomes the designated address. The 90 degree-rotation of the image can be realized by single algorithm by only initial-setting horizontal scanning width and vertical scanning width independently of input/output image size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital copying machine,
The present invention relates to an image processing apparatus such as a digital facsimile apparatus that digitally processes image data, and more particularly to an image processing method and an image processing apparatus for rotating input image data by 90 degrees.

[0002]

2. Description of the Related Art Conventionally, there has been known a technique for rotating an input image by 90 degrees and outputting the image in an image processing apparatus for digitally processing image data. Further, there are some proposals for reducing the processing time when rotating the image data by 90 degrees. For example, Japanese Unexamined Patent Publication No. 5-20450 has two circuits for calculating a designated address when inputting to an image memory and a designated address when outputting from an image memory, and by performing address conversion by the two circuits. A technique for performing image rotation processing is disclosed.

Another technique is disclosed in Japanese Patent Laid-Open No. 1-2512.
In Japanese Patent No. 86, in order to calculate the address of the rotated image data, the start address of the start line is calculated,
A method is shown in which the start address of the next line is calculated based on this, and the address of each pixel of each line is obtained from each start address.

[0004]

By the way, in any of the conventionally known image data rotation processes, after writing the image data in the image memory, the data is read out from the image memory by using the address conversion. The process is performed as one unit. Therefore, for example, in the case of sequentially processing a plurality of input image data, if the writing of data to the image memory and the reading of data from the image memory for the preceding image data are not completed, the succeeding image data is processed. Cannot write to image memory. That is, for example, in a digital copying machine, the next original image cannot be read while the data written in the image memory is being printed out. Further, it is not possible to print out while the read original image is being written in the image memory.

Therefore, in order to increase the copying speed in a digital copying machine, it is necessary to read an original at a high speed and write it in an image memory, read the data in the image memory at a high speed by address conversion, and print it out. As described above, the copying speed cannot be improved unless the time required for image reading and printout processing for one original image is shortened. It is not easy to increase the speed of such a device, which causes an increase in the cost of the device.

On the other hand, the structure for performing the processing of writing the input image data in the image memory and the processing of reading the data written in the image memory by rotating it by 90 degrees in parallel is, for example, an original document in the image memory. This can be achieved by preparing two pages. However, since the image memory is a memory having a large capacity and is expensive, the configuration including the image memory for two pages will eventually cause a cost increase.

As described above, in the conventional technique, the image data input process and the image data output process are performed in parallel by using only one image memory for one page, and 90
The inventor of the present application recognizes that there has been no technique or apparatus for performing high-speed rotation at a high speed. The present invention has been made against the background of such a conventional technique. One object is to use an image memory for one page of a document and devise a method of addressing the image memory.
It is an object of the present invention to provide a 90-degree rotation processing method of image data, in which the image data rotated by a degree is read from the image memory and, at the same time, newly input image data is written in the image memory.

Another object of the present invention is to provide only one page of image memory, and to perform processing of writing input data to the image memory and processing of reading an image rotated 90 degrees from the image memory. An object of the present invention is to provide an image processing device that can be operated in parallel. From another point of view of the object of the present invention,
It is an object of the present invention to provide a method and apparatus for implementing a new addressing algorithm for rotating image data by 90 degrees.

[0009]

According to one aspect of the present invention, there are a number in the main scanning direction and b number in the sub scanning direction (a,
When one page of image data in which pixels of (b is a positive integer) are arranged is sequentially input for a plurality of pages, only one image memory for one page having a pixel storage capacity of a × b is used. And a method for rotating the image data of each page input in the above order by 90 degrees, in which the pixel number a in the main scanning direction is (n-1) in synchronization with the pixel input of the input image data. ) A sequential multiple of the multiplied value (where n is the ordinal number of the input page), or when the sequential multiple exceeds (ab-1), specify the remainder value obtained by dividing the sequential multiple by (ab-1). The data is sequentially output as an address, the output designated address of the image memory is accessed, the image data stored at the designated address is read, and then,
A method of rotating image data by 90 degrees, characterized in that the input image data is written to the designated address, and the read image data is inverted line by line in the main scanning direction to obtain a 90 degree rotated image. .

According to another aspect of the present invention, one page of image data in which a number of pixels in the main scanning direction and b number of pixels in the sub-scanning direction (a and b are positive integers) are arranged is plural. An image processing apparatus for rotating the input image data of each page by 90 degrees when inputting in order of pages, the image memory for one page having a pixel storage capacity of a × b, In synchronization with the pixel input of the input image data,
A sequential multiple of a value obtained by multiplying the number of pixels a in the main scanning direction by (n-1) (where n is the order number of the input page), or when the sequential multiple exceeds (ab-1), the sequential multiple. Is divided by (ab-1) to sequentially output the designated value as the designated address, and the designated address output from the designated address means sequentially accesses the image memory to set the designated address of the image memory. Memory access means for reading the stored image data and then writing the input image data at the designated address, and means for inverting the pixel data read by the memory access means in the main scanning direction line by line. An image processing apparatus for performing 90-degree rotation processing on image data, which is characterized by including the above.

[0011]

According to the present invention, when one page of image data in which a pixels in the main scanning direction and b pixels in the sub scanning direction are arranged is sequentially input for a plurality of pages, one page's worth of image data is input. By using only one image memory, the image data of each page to be input can be rotated by 90 degrees, and the image data to be input next can be written in parallel.

Further, the size of the input image data to be rotated by 90 degrees may be any size, and only by setting the size in the processing circuit in advance, the image can be rotated by 90 degrees by a single algorithm. it can. Further, since the reading of the image from a certain address of the image memory and the writing of the image to the address are simultaneously performed, for example, the write-modify-read mode in which the same address is designated which is the high speed access mode of the dynamic RAM. Can be utilized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is based on this invention,
It is a conceptual diagram which shows the order at the time of accessing an image memory. The left side, center, and right side of FIG.
The first-page access, the second-page access, and the third-page access are shown, and the upper part shows how input image data is arranged in a page memory, which is an image memory. The lower part shows the order of reading the image data in the page memory by rotating it by 90 degrees.

As is apparent from FIG. 1, in the memory access according to the present invention, the storage address of the next image data is obtained from the relative position with respect to the storage address of the preceding image data. That is, the read address and the write address in the page memory match on a pixel-by-pixel basis. Further, the memory access sequence has a unique format depending on the number of image data to be processed.

More specifically, the address to be accessed in the page memory is obtained by the arithmetic sequence combined with the modulo operation, and the preceding image data (for example, the data of the first sheet) is synchronized with each pixel. ) And the subsequent image data (for example, data for the second sheet) are simultaneously input. The calculation of addressing in the page memory shown in FIG. 1 is performed when the number of vertical addresses (number of areas in which pixels can be stored) of the page memory is a and the number of horizontal addresses (number of areas in which pixels can be stored) is b. , As follows.

[0016]

[Equation 1]

The addressing of the page memory, ie the access of the pixels stored in the page memory, is done in multiples of a. When access is performed in order of a multiple of a, and the address value to be accessed exceeds the last address (ab-1) of the page memory, the remainder obtained by dividing the calculated address by (ab-1), that is, The result of the modulo operation becomes the next specified address. While performing such addressing, the pixel data is read from the specified address of the page memory, and the pixel data of the next page is written to the specified address from which the pixel data was read.
This enables continuous vertical / horizontal address conversion of image data.

FIG. 2 is a block diagram showing the outline of the overall configuration of a circuit for performing the image data 90 ° rotation processing according to the embodiment of the present invention. As shown in FIG. 2, the scanner unit 4
The image data read in 1 is converted into a digital signal, and line data consisting of a plurality of pixel data is sequentially given to the image memory 42. Scanner 41 and image memory 4
Although not shown, a line buffer may be interposed between the two. The write address of the pixel data given to the image memory 42 is calculated by the address calculation circuit 43. At the same time, the address calculation circuit 43 calculates a read address for reading the image data stored in the image memory 42. The write address and read address are
It has the same address as described above. Therefore, the input pixel data is stored at the address where the pixel data of the image memory 42 is read.

Pixel data read from the image memory 42 is temporarily stored in a line buffer (not shown) provided as needed, and a transposition processing circuit transposes the image in the main scanning direction line by line. Processing (mirror image processing) is performed and the result is given to the printer unit 45. And it is printed out. The data to be printed out is the image data read by the scanner unit 41 rotated by 90 degrees.

FIG. 3 shows a block diagram in which the address calculation circuit 43 described above is configured by hardware. Since the algorithm for accessing the image memory is simple, the circuit is also realized with a relatively simple configuration as shown in FIG. FIG.
In the circuit block shown in 1,
3,5,8,10,11,12,13,14,16,1
Reference numerals 8, 21, 23, 24 and 26 are registers or flip-flops for setting or holding input values.

The square blocks 2, 15 and 25 are multipliers. Furthermore, on the square block, "MO
Blocks 4, 9, 17, and 22 marked with "D" are modulo arithmetic units for performing modulo arithmetic. Blocks 6 and 19 in which a broken-line rectangle is drawn in a solid-line rectangular block
Represents a multiplexer for signal selection.

Further, 7 and 20 are adders. next,
The operation of the circuit block shown in FIG. 3 will be described. <Initial state> As an initial setting, registers 3, 11, 1
2, 16 and 26 are "1", "a", and "ab", respectively.
Input the values of "b" and "b (l-1)".

These initial setting values are input only once before the image formation is started and are not changed thereafter. Registers other than the above-mentioned initial setting registers are reset at the start of image formation. <Address Calculation for First Page> (1) Address Calculation for First Line The initial value “1” recorded in the register 3 is input to the remainder calculator 4 and the result is recorded in the register 5. At this point, the value of the register 5 is recorded in the register 1 for the address calculation of the next page.

Next, the value of the register 5 and the value of the register 10 storing the address of the preceding pixel are added and recorded in the register 8. By this operation, addresses are formed in the form of arithmetic progression. In this case, since the value of the register 10 is "0", "1" is stored in the register 8. Then
The value of the register 8 is given to the remainder calculator 9, and "(ab-
1) ”. Then, the remainder is recorded in the register 10. The value recorded in the register 10 is the address value of the second pixel of the first line. The first address value on all pages is "0", which is output by register 10 when the register is first reset.

Address values for reading and writing the third and subsequent pixels are calculated by the circuit portion 30 enclosed by a dotted line rectangle. That is, the value of the register 5 is added to the register 10 that stores the address value of the second pixel by the adder 7, and the result is recorded in the register 8. Then, the value recorded in the register 8 is input to the remainder calculator 9. The result is recorded in the register 10. The value of the register 10 becomes the address of the third pixel on the first line.

The address value of the first line is the circuit portion 30.
By repeating the above-mentioned calculation in (3), the data is sequentially output from the register 10. The multiplexer 6 selects the input from the register 5 and supplies it to the adder 7 until the address calculation for one line is completed. (2) Second line address calculation Since the first address of the second line is the bth address, "b" is the first value in the first page address calculation. Similar to the operation of the first line, register 1
An initial value “b” is input to 6 prior to the calculation. This value flows through the remainder calculator 17, the register 18, the multiplexer 19, the adder 20, the register 21, the remainder calculator 22, and the register 23, and becomes the address of the first pixel on the second line.

Similar to the first line, the address calculation for the second and subsequent pixels is performed in the circuit portion 31 inside the dotted rectangle. The multiplexer 19 selects the input from the register 5 and supplies it to the adder 20 until the address calculation of the second line is completed. (3) Address calculation of the third line When the address calculation of the first line is completed, the multiplexer 6 selects the input of the register 18. Therefore, adder 7
Then, the last address of the first line and the value of the register 18 are added, and the added value is recorded in the register 10 after the remainder calculation. This value is the address of the last pixel on the second line. And again multiplexer 6
Is switched to select the input from register 5,
The value of the register 5 and the value of the register 10 are added by the adder 7, the remainder operation is performed by the remainder operator 9, and the result is recorded in the register 10. This is the address of the first pixel on the third line.

After that, the calculation is repeated simultaneously with the address calculation of the first line. Thus, every time the calculation of each line is completed, the multiplexer 6 is switched and the above third
An operation for calculating the address of the line is required. As described above, the upper circuit of FIG.
In, the address calculation of the odd line is sequentially performed.

(4) Address calculation of the fourth line When the address calculation of the second line is completed, the multiplexer 19 selects the input from the register 18. Therefore, the adder 20 adds the value of the register 18 to the last address of the second line output from the register 23. The result is recorded in the register 21, and the value of the register 21 is remainder-calculated by the remainder calculator 22. The result is recorded in the register 23. The value recorded in the register 23 is
It corresponds to the address of the last pixel on the third line.
Then the multiplexer 19 is switched again to select the input of the register 5, the value of the register 23 and the register 5
And the value of are added in adder 20. Then, the result is recorded in the register 21, the remainder calculation is performed in the remainder calculator 22, and then the result is recorded in the register 23. This is the fourth
It becomes the address of the first pixel of the line.

After that, the calculation is repeated in the same manner as the address calculation of the second line. Thus, every time the calculation of each line is completed, the multiplexer 19 is switched to perform the above-described operation for calculating the address of the fourth line. As described above, the even-numbered line address calculation is sequentially performed in the lower circuit of FIG. 3, particularly in the circuit portion 31 surrounded by the dotted line.

(5) Parallel Calculation of Three or More Lines In the circuit of FIG. 3, a circuit for parallel calculation of the address calculation of the preceding odd line and the address calculation of the subsequent adjacent even line is shown. In order to calculate address operations of 3 lines or more in parallel, register 2
4, a circuit block starting from the multiplier 25 and the register 26, and a circuit similar to the circuit for performing the address calculation of the odd line or the even line described above is required.

The switching of the multiplexer when the calculation of each line is completed is switched to the input of the register 26 when the m-line parallel calculation is considered. In this case, since the initial value of the register 26 is l = m, b (m
-1). Of course, the circuit blocks from the circuit block for calculating the third line to the m-1th line are also required,
M circuit blocks such as circuit block portions 30 and 31 shown by dotted lines are also required.

Even in the case of performing parallel calculation of three lines or more, the basic circuit configuration is the same as the odd line arithmetic circuit or the even line arithmetic circuit of FIG. 3, so further description will be omitted. . In any case, when the circuit is configured so that three lines or more are operated in parallel, the address calculation can be speeded up.

<Address Calculation for Second and Later Pages> The value of register 5 was recorded in register 1 at the beginning of the operation of the first line of the first page, but this is processed prior to the address calculation of the second page. The value of register 1 and the value of register 11 are multiplied by the multiplier, and the result is recorded in register 3. This completes the initial setting of the address calculation of the odd line on the second page. The initial settings for the second and subsequent pages are similarly made.

In the address calculation of the even-numbered line on the second page, the same value as the register 1 should be recorded in the register 14 prior to the calculation, so this value and the register 1
The value of 2 is multiplied by the multiplier 15 and the result is stored in the register 1
Record at 6. This completes the initial setting of the address calculation for the even lines on the second page. Initial settings for the third and subsequent pages are similarly performed.

Although the address calculating circuit in FIG. 3 described above is configured by hardware, the address calculating circuit may be configured by software. Besides, the present invention can be variously modified within the scope of the claims.

[0037]

According to the present invention, a digital copying machine,
In a digital image processing apparatus such as a digital facsimile apparatus, only one image memory such as a page memory can be used to rotate an input image by 90 degrees and output it at high speed. In particular, according to the present invention, when the image sizes to be processed are different, the image can be rotated by 90 degrees based on a single algorithm simply by setting the main scanning width and the sub-scanning width of the image to be processed as initial values.

Therefore, when the present invention is implemented by hardware, the circuit configuration becomes easy. Further, according to the present invention, since the pixel data is read out and the pixel data is written by designating the same address of the image memory, the write-modify-read mode, which is the high-speed access mode of the dynamic RAM, is used to achieve high speed Image rotation processing can be performed.

When the present invention is applied to, for example, a digital copying machine, since image data can be input / output to / from an image memory at the same time, a device having a high copying speed capable of processing image reading and printing in parallel. can do.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining an access sequence of an image memory according to the present invention.

FIG. 2 is a schematic diagram showing the overall configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 3 is a circuit block diagram showing a hardware configuration example of an address calculation circuit according to an embodiment of the present invention.

[Explanation of symbols]

43 Address calculation circuit 1, 3, 5, 8, 10, 11, 12, 13, 14, 1
6,18,21,23,24,26 Register (flip-flop) 2,15,25 Multiplier 4,9,17,22 Remainder calculator 6,29 Multiplexer 7,20 Adder

Claims (2)

[Claims] 1. When one page of image data in which a number of pixels are arranged in the main scanning direction and b number of pixels (a and b are positive integers) in the sub-scanning direction are sequentially input for a plurality of pages. , A
A method for rotating the image data of each page input in the above order by 90 degrees by using only one image memory for one page having a pixel storage capacity of × b, the pixel of the input image data In synchronization with the input, the value obtained by multiplying the number of pixels a in the main scanning direction by (n-1) (where n is the order number of the input page) is a sequential multiple or a sequential multiple of (ab
-1) is exceeded, the sequential multiple is (ab-1).
The remainder value divided by is sequentially output as a designated address, the designated address output from the image memory is accessed, the image data stored at the designated address is read, and then the input image is stored at the designated address. A method for rotating image data by 90 degrees, wherein data is written and the read image data is inverted line by line in the main scanning direction to obtain a 90 degree rotated image. 2. When one page of image data in which a number of pixels are arranged in the main scanning direction and b number of pixels (a and b are positive integers) in the sub scanning direction are sequentially input for a plurality of pages. An image processing apparatus for rotating the input image data of each page by 90 degrees, comprising: an image memory for one page having a pixel storage capacity of a × b; and a pixel input of the input image data. Synchronously, a sequential multiple of a value obtained by multiplying the number of pixels a in the main scanning direction by (n-1) (where n is the order number of an input page), or when the sequential multiple exceeds (ab-1). , The sequential multiple (ab
An address designating means for sequentially outputting the remainder value divided by -1) as a designated address; and a designated address outputted from the address designating means,
Memory access means for sequentially accessing the image memory, reading image data stored at a specified address of the image memory, and then writing the input image data at the specified address; and pixel data read by the memory access means. And a means for reversing in the main scanning direction line by line, the image processing apparatus for rotating the image data by 90 degrees.