JPH0864525A - Crystal grain forming method and semiconductor device - Google Patents
Crystal grain forming method and semiconductor deviceInfo
- Publication number
- JPH0864525A JPH0864525A JP19815394A JP19815394A JPH0864525A JP H0864525 A JPH0864525 A JP H0864525A JP 19815394 A JP19815394 A JP 19815394A JP 19815394 A JP19815394 A JP 19815394A JP H0864525 A JPH0864525 A JP H0864525A
- Authority
- JP
- Japan
- Prior art keywords
- fine particles
- crystal grains
- crystal
- temperature
- deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
Abstract
(57)【要約】
【目的】 10 〜 40 Åの極微小サイズの結晶粒を形成
する技術を提供し、高信頼性の単一電子素子および短波
長発光のSi発光素子の製造を可能ならしめることにあ
る。
【構成】 基板温度を結晶相堆積の下限温度以下の低温
化に保ちつつ材料元素を堆積することにより、極微小サ
イズの微小粒を堆積する。この非晶質微小粒を結晶化温
度以上で熱処理することにより結晶微小粒と化する。本
発明の半導体装置は、上記結晶微小粒を絶縁性の薄膜で
はさみ、さらにそれを導電性の材料ではさんだ構造をな
す。導電性材料間に電圧をかけることにより、トンネル
電流で結晶微小粒に電流を注入し、発光動作を得る。
【効果】 単一電子素子を用いた大容量・高速・低消費
電力のLSIと、青〜緑色光素子とを用いて、大量デー
タ転送・処理の光/電気融合システムを実現することが
可能になる。
(57) [Abstract] [Purpose] Providing a technology to form ultra-fine crystal grains of 10 to 40 Å and enabling the production of highly reliable single-electron devices and Si light-emitting devices with short-wavelength emission. Especially. [Structure] By depositing a material element while maintaining the substrate temperature at a lower temperature equal to or lower than the lower limit temperature of the crystal phase deposition, ultrafine particles are deposited. The amorphous fine particles are heat-treated at a temperature equal to or higher than the crystallization temperature to be crystal fine particles. A semiconductor device of the present invention has a structure in which the above-mentioned crystal fine particles are sandwiched by an insulating thin film and further sandwiched by a conductive material. By applying a voltage between the conductive materials, a current is injected into the crystal fine particles by a tunnel current to obtain a light emitting operation. [Effect] A large-capacity, high-speed, low-power-consumption LSI that uses a single electronic element and a blue-green light element can be used to realize an optical / electric fusion system for large-volume data transfer / processing. Become.
Description
【0001】[0001]
【産業上の利用分野】本発明は、結晶粒を異種材料の上
に形成する方法に係わり、特に、量子サイズ効果の発す
る微小結晶粒を形成する方法に関する。また、本発明
は、単体で、もしくはSi集積回路に搭載して光インタ
ー・コネクト用発光素子として用いる半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming crystal grains on a different material, and more particularly to a method for forming fine crystal grains having a quantum size effect. The present invention also relates to a semiconductor device used alone or mounted on a Si integrated circuit as a light emitting element for optical interconnect.
【0002】[0002]
【従来の技術】エレクトロニクスのサブシステムである
大規模集積回路(Large Scale Integrated circuit;L
SI)は、素子を微細化することで大容量・高速・低消
費電力の性能を飛躍的に向上させてきた。しかし、今や
微細化は、従来の素子の動作原理の限界と目される0.1
μmの壁を目の当たりにするところまで来た。0.1μm
以降は、新たな動作原理の電子素子がLSIの発展を担
わなければならない。新たな素子とは、超微細構造で発
現する量子サイズ効果を利用したもので、特に、その原
理の簡潔さから、100 Å以下のサイズの微小結晶粒に発
現するクーロン・ブロッケイド現象を用いた単一電子素
子が主眼である。最近では、単一電子素子に関する理論
計算や、原理実験の結果が多く報じられるようになり、
その進展は著しい。しかしまた、この素子が新しく産業
を支えるようになるためには、素子製造技術の開発も欠
かせない。この分野はまだ黎明期にある。発明者らは、
先に、SiO2上で生ずるSi原子のマイグレーション
とその後の凝集現象により微小結晶粒を形成する技術を
報告した。2. Description of the Related Art Large scale integrated circuit (L) which is a subsystem of electronics.
(SI) has dramatically improved the performance of large capacity, high speed, and low power consumption by miniaturizing the elements. However, miniaturization is now regarded as the limit of the operating principle of conventional devices.
We have reached the point where we can see the wall of μm. 0.1 μm
After that, an electronic element having a new operating principle must play a role in the development of the LSI. The new device utilizes the quantum size effect that appears in the hyperfine structure, and in particular, due to the simplicity of its principle, it uses the Coulomb blockade phenomenon that appears in minute crystal grains with a size of 100 Å or less. One electronic device is the main focus. Recently, many results of theoretical calculations and principle experiments on single-electron devices have been reported,
The progress is remarkable. However, development of element manufacturing technology is also essential for this element to support new industries. This field is still in its infancy. The inventors
Previously, a technique for forming fine crystal grains by the migration of Si atoms generated on SiO2 and the subsequent aggregation phenomenon was reported.
【0003】また、今後のエレクトロニクスの潮流にお
ける新しい重要なうねりは、電子回路と光通信との融合
である。光ファイバによるデータの双方向大量伝送と高
速LSIによるデータ処理が、アメリカでも日本でも、
職場でも家庭でも日常の光景になる。その際、LSIと
光ケーブルとの接続部に光/電気変換素子が必要であ
る。受光発光素子としてはGaAs 系の化合物半導体素子
が代表的であるが、電子回路の主流であるSiLSIに
搭載出来ない。SiとGaAs が互いにドーパントの関係
にあり、化学的に相性が悪いためである。したがって、
Siを用いた光/電気変換素子が求められる。Si受光
素子は、これまでにも開発の歴史があり、フォト・ダイ
オード、フォト・トランジスタなど、実用化もされてい
る。しかし、発光に関しては、Siが間接遷移型のバン
ド構造を有するため実現が難しく、多孔質Siの可視発
光が発見された近年ようやく研究・開発が始まった。多
孔質Siは、陽極化成で生ずるSiの虫食い現象により
得られるもので、ジャパニーズ・ジャーナル・オブ・ア
プライド・フィジクス(Japanese Journal of Applied
Physics)第31巻(1992年)第L1219頁から
第L1222頁において論じられているように、直径 1
50 〜 280 ÅのSiO2 の粒によりなり、その中に、
SiO2 粒の1/3程度の直径(50 〜 80 Å)のSi
粒が内包されている。Si粒のサイズが100 Å以下と極
めて小さいため、量子サイズ効果によりバンド構造が直
接遷移型にシフトし、発光が可能である。この陽極化成
法では、Si粒のサイズを化成電流密度によって結果的
に制御している。このため、大量データ転送に望ましい
高周波数帯域すなわち青〜緑色の短波長域の発光に必要
な特に微小な 10 〜 40 ÅのSi粒を制御して形成する
ことは難しい。A new important swell in the future trend of electronics is the fusion of electronic circuits and optical communication. Bi-directional mass transmission of data by optical fiber and data processing by high-speed LSI
It becomes a daily scene both at work and at home. At that time, an optical / electrical conversion element is required at the connecting portion between the LSI and the optical cable. A typical GaAs-based compound semiconductor element is used as the light-receiving / emitting element, but cannot be mounted on SiLSI, which is the mainstream of electronic circuits. This is because Si and GaAs are in a dopant relationship with each other and are chemically incompatible. Therefore,
A photoelectric conversion element using Si is required. The Si light receiving element has a history of development so far, and has been put to practical use such as a photo diode and a photo transistor. However, with respect to light emission, it is difficult to realize since Si has an indirect transition type band structure, and research and development have finally started in recent years when the visible light emission of porous Si was discovered. Porous Si is obtained by the worm-eating phenomenon of Si that occurs during anodization, and it can be obtained by the Japanese Journal of Applied Physics.
Physics 31 (1992) L1219 to L1222, diameter 1
It consists of 50-280Å particles of SiO2, in which
Si having a diameter (50-80 Å) about 1/3 that of SiO2 grains
Grains are included. Since the size of Si particles is extremely small, 100 Å or less, the band structure is directly shifted to the transition type by the quantum size effect, and light emission is possible. In this anodization method, the size of Si grains is consequently controlled by the formation current density. For this reason, it is difficult to control and form particularly minute Si particles of 10 to 40 Å which are necessary for light emission in a high frequency band, that is, a short wavelength band of blue to green, which is desirable for mass data transfer.
【0004】[0004]
【発明が解決しようとする課題】単一電子素子は、 (e*
e)/2C (C ;微小粒の静電容量,e;素電荷量)が kT
(T=300K) より大きな時に安定して動作する。Cは粒が
小さいほど小さい。計算によれば、10 〜 80 Åが素子
動作のための該当範囲である。しかし、特に信頼性が必
要な場合には、 (e*e)/2C と kT の違いを十分大きく取
る必要があり、10〜 40 Åがこれに応える粒径範囲にな
る。一方、Si発光素子においては、粒径が発光波長に
対応しており、青〜緑色の発光には 10 〜 40 ÅのSi
微小粒が求められる。いずれの場合も、10 〜 40 Åの
極微小径でSi粒を形成する技術が必要である。A single electronic device is (e *
e) / 2C (C; electrostatic capacity of fine particles, e; elementary charge) is kT
Stable operation when larger than (T = 300K). The smaller the grains are, the smaller C is. According to the calculation, 10 to 80 Å is the applicable range for device operation. However, especially when reliability is required, the difference between (e * e) / 2C and kT needs to be sufficiently large, and 10 to 40 Å is the particle size range that can meet this requirement. On the other hand, in the Si light emitting device, the particle size corresponds to the emission wavelength, and for blue to green emission, 10 to 40 Å of Si is used.
Fine particles are required. In any case, a technique for forming Si particles with an extremely small diameter of 10 to 40 Å is required.
【0005】発明者らが先に報告した結晶粒の形成技術
は、基板温度とSiの堆積速度を制御して所望のサイズ
の結晶粒を堆積するものである。基板温度を低温化し
(ただし、Siが結晶相で堆積する240℃が下限)、
堆積速度を高速化すれば、10〜 40 ÅのSi結晶粒を形
成することも可能である。しかし、このように特にサイ
ズが小さい微小粒を形成する場合には面内均一性や製造
装置に関連して問題が生ずる。The crystal grain forming technique previously reported by the present inventors is to deposit crystal grains of a desired size by controlling the substrate temperature and the deposition rate of Si. Lower the substrate temperature (however, the lower limit is 240 ° C at which Si is deposited in the crystalline phase),
If the deposition rate is increased, it is possible to form Si crystal grains of 10 to 40 Å. However, problems such as in-plane uniformity and manufacturing equipment arise when forming fine particles having a particularly small size.
【0006】例えば、20 Åの微小粒を20 Åの間隔で形
成しようとすると、連続膜の膜厚に換算して2Å程度の
堆積をすることになる。1Å/sec. (図1参照,850
℃)で堆積するなら堆積時間は2秒ということになる。
ところで、堆積開始、停止のためにビーム・シャッタを
開閉すれば、Si照射ビームの断面形状は、シャッタが
横切るのに対応して非対称に変形する。この間、基板へ
のSi照射は不均一になり、堆積量の基板面内均一性は
低下する。開閉の遷移時間が定常照射の時間に比べて充
分短ければこの問題は無視できる。しかし、遷移時間が
たかだか 0.3 秒であっても、堆積時間が2秒と短かけ
れば、遷移時間の割合は3割に達し、実際のところ、無
視できない。[0006] For example, if it is attempted to form 20Å fine particles at intervals of 20Å, about 2Å will be deposited in terms of the film thickness of a continuous film. 1Å / sec. (See Fig. 1, 850
If it is deposited at (° C.), the deposition time is 2 seconds.
By the way, if the beam shutter is opened and closed to start and stop the deposition, the cross-sectional shape of the Si irradiation beam is asymmetrically deformed as the shutter crosses. During this time, the Si irradiation on the substrate becomes non-uniform, and the in-plane uniformity of the deposition amount deteriorates. If the open / close transition time is sufficiently shorter than the steady irradiation time, this problem can be ignored. However, even if the transition time is at most 0.3 seconds, if the deposition time is as short as 2 seconds, the proportion of the transition time reaches 30%, and in fact, it cannot be ignored.
【0007】また、通常、膜厚の基板面内均一化のため
に堆積中に基板回転を行なうが、均一化を達成するため
には、堆積終了までに最低でも1回転させなければなら
ない。これは、堆積時間2秒に対して 30 rpm の回転速
度に相当する。実際には、均一化の効果を充分働かせる
ため10回転くらいは必要で、300 rpm の回転速度が必
要である。300 rpm というのは真空内駆動装置としては
速い回転速度であり、この場合、装置の故障頻度の増加
という問題が生ずる。[0007] Usually, the substrate is rotated during the deposition in order to make the film thickness uniform in the surface of the substrate, but in order to achieve the uniformization, at least one rotation must be performed by the end of the deposition. This corresponds to a rotation speed of 30 rpm for a deposition time of 2 seconds. Actually, about 10 rotations are necessary to make the homogenizing effect sufficiently work, and a rotation speed of 300 rpm is necessary. 300 rpm is a high rotation speed for a vacuum drive device, and in this case, there is a problem that the frequency of failure of the device increases.
【0008】これらの問題を回避するには、より低速で
Si粒を堆積できる技術が必要になる。従来法では、堆
積速度を低速化すると、Si原子のマイグレーション長
が長くなるため結晶粒サイズが大きくなってしまい、10
〜 40 Åの極微小サイズの粒堆積は出来ない。To avoid these problems, a technique capable of depositing Si particles at a lower speed is required. In the conventional method, when the deposition rate is slowed, the migration length of Si atoms becomes long and the crystal grain size becomes large.
It is not possible to deposit very small particles of ~ 40Å.
【0009】本発明の課題は、高信頼性の単一電子素子
および青〜緑色発光のSi発光素子製造のために、10
〜 40 Åの極微小サイズの結晶粒を制御して形成する技
術を提供することである。また、Si発光素子に関して
は、本発明で形成した微小粒を利用した素子構造も提供
する。An object of the present invention is to produce a highly reliable single-electron device and a blue to green light emitting Si light emitting device.
It is to provide a technique for controlling and forming crystal grains with an extremely small size of up to 40 Å. Further, regarding the Si light emitting element, an element structure utilizing the fine particles formed in the present invention is also provided.
【0010】[0010]
【課題を解決するための手段】10 〜 40 Åの極微小サ
イズの結晶粒を1Å/sec. 以下の低速堆積で形成する本
発明の手段は次のとおりである。まず、基板温度を結晶
相堆積の下限温度(240℃)以下にまで低温化し、非
晶質Si微小粒を堆積する。次に、結晶化温度(240
℃)以上の熱処理を行ない、これを結晶化する。[Means for Solving the Problems] The means of the present invention for forming extremely fine crystal grains of 10 to 40 Å by low-speed deposition of 1 Å / sec. Or less is as follows. First, the substrate temperature is lowered to the lower limit temperature of crystal phase deposition (240 ° C.) or less, and amorphous Si fine particles are deposited. Next, the crystallization temperature (240
(.Degree. C.) or higher, and this is crystallized.
【0011】また、本発明で形成した微小粒を用いて発
光素子をなすためには次の構造を構成する。即ち、10
〜 40 Åの極微小サイズの結晶粒の上下を薄い絶縁性の
膜ではさみ、さらにその上下を導電性材料ではさんだ構
造を形成する。この構造において導電性材料間に電圧を
かけることにより、微粒子において発光現象を生ぜしめ
る。発光素子には、素子の断面において(通常、基板の
劈開面)発光させるものと、電極側から(基板の平面)
光を取り出すものがある。後者の場合には、絶縁性の膜
および取り出し側の導電性材料に透明な材料を用いる。
微粒子の層は一層でも複数層でもよい。Further, in order to form a light emitting device using the fine particles formed in the present invention, the following structure is constructed. That is, 10
A very small crystal grain of ~ 40 Å is sandwiched by a thin insulating film, and a conductive material is sandwiched between them. By applying a voltage between the conductive materials in this structure, a light emission phenomenon is caused in the fine particles. For the light emitting element, one that emits light in the cross section of the element (usually the cleaved surface of the substrate) and from the electrode side (the plane of the substrate)
Some take out light. In the latter case, transparent materials are used for the insulating film and the conductive material on the extraction side.
The fine particle layer may be a single layer or a plurality of layers.
【0012】[0012]
【作用】10 〜 40 Åの極微小サイズの結晶粒を低速堆
積で形成する手段について。[Function] Regarding means for forming ultra-fine crystal grains of 10 to 40 Å by low-speed deposition.
【0013】本発明の製造方法は、微小粒を乗せる絶縁
膜を所望の温度に加熱しつつ、これに、微小粒の構成元
素からなる原子もしくは分子を気相中から供給する。絶
縁膜を昇温しておくことにより、膜上に供給した構成元
素に熱エネルギーを与え、膜上移動(マイグレーショ
ン)、及びマイグレーションの結果として出会った元素
どうしの凝集を可能にする。Si原子をSiO2 膜表
面に照射したときの、膜表面におけるSi原子のマイグ
レーション長を基板温度の関数として図1に示す。マイ
グレーションが終了した時点で凝集が生じSi粒が発生
するため、マイグレーション長はおおよそSi粒の発生
間隔に相当し、間隔いっぱいにSi粒を成長させるとき
の粒径にも相当する。In the manufacturing method of the present invention, while heating the insulating film on which the fine particles are placed to a desired temperature, atoms or molecules consisting of the constituent elements of the fine particles are supplied from the gas phase. By raising the temperature of the insulating film, thermal energy is given to the constituent elements supplied on the film, and migration on the film (migration) and aggregation of elements encountered as a result of migration are possible. FIG. 1 shows the migration length of Si atoms on the film surface as a function of the substrate temperature when the surface of the SiO 2 film is irradiated with Si atoms. Since agglomeration occurs and Si particles are generated at the time when the migration is completed, the migration length roughly corresponds to the generation interval of Si particles, and also corresponds to the particle size when Si particles are grown to the full interval.
【0014】マイグレーション長は、図1に示すよう
に、基板温度およびマイグレーション種の供給速度(堆
積速度)により変化する。基板温度を下げれば、マイグ
レーションのために供給されるエネルギーが減るので、
マイグレーション長は減少する。供給速度(堆積速度)
を上げれば、単位面積当たりに存在するマイグレーショ
ン種の数が増加し、互いに出会う確率が増加する。わず
かの移動距離で他のマイグレーション種と出会い合体し
て凝集体となり移動が停止してしまうので、マイグレー
ション長はやはり短くなる。基板温度と堆積速度を駆使
して所望のサイズの結晶粒を堆積しようというのが従来
法である。この方法では、結晶相で堆積する温度に下限
があるため、既に述べたように、極微小サイズで微小粒
を形成しようとすると無視できない困難が生ずる。参考
のため従来法の堆積条件領域を図1中にライトグレーの
領域(領域1)で示す。As shown in FIG. 1, the migration length changes depending on the substrate temperature and the migration species supply rate (deposition rate). Since lowering the substrate temperature reduces the energy supplied for migration,
Migration length is reduced. Supply rate (deposition rate)
If the value is increased, the number of migration species existing per unit area increases, and the probability of encountering each other increases. The migration length is also shortened because other migration species meet and coalesce into agglomerates within a short distance to stop the migration. The conventional method is to use the substrate temperature and the deposition rate to deposit crystal grains of a desired size. In this method, there is a lower limit to the temperature at which the crystalline phase is deposited, so that it is difficult to ignore when attempting to form fine particles with an extremely small size, as described above. For reference, the deposition condition region of the conventional method is shown as a light gray region (region 1) in FIG.
【0015】本発明は、結晶相堆積の下限温度よりもさ
らに充分に基板温度を低温化してSiを堆積する。こう
することで、図1に示すように、遅い堆積速度でもマイ
グレーション長を充分短くすることができる。(本発明
の堆積条件領域は、図1中、ダークグレーで示した領域
(領域2)である。特性線のうち、この領域に入ってい
る部分が堆積条件になる。なお、結晶構造の最小単位の
サイズである格子定数よりもマイグレーション長の短い
領域は微小粒堆積には使わない。結晶の最小構造よりも
小さい粒が堆積するので、結晶たり得ないからであ
る)。しかし、結晶化温度より低温であるため、従来法
のように堆積工程それだけで結晶粒を得るわけにはいか
ない。微小粒は非晶質状態で堆積する。堆積後に結晶化
温度以上の温度で熱処理することにより、固相成長が生
じ非晶質微小粒は結晶相に遷移する。In the present invention, Si is deposited by further lowering the substrate temperature below the lower limit temperature of crystal phase deposition. By doing so, as shown in FIG. 1, the migration length can be sufficiently shortened even at a low deposition rate. (The deposition condition region of the present invention is a region (region 2) shown in dark gray in FIG. 1. Of the characteristic lines, the portion falling within this region is the deposition condition. The minimum unit of crystal structure Areas with a migration length shorter than the lattice constant, which is the size of, are not used for the deposition of fine grains, because grains smaller than the minimum crystal structure are deposited and cannot be crystallized). However, since the temperature is lower than the crystallization temperature, it is not possible to obtain crystal grains only by the deposition process as in the conventional method. The fine particles are deposited in an amorphous state. By performing heat treatment at a temperature equal to or higher than the crystallization temperature after the deposition, solid phase growth occurs and the amorphous fine particles transition to a crystalline phase.
【0016】10 〜 40 Åの極微小サイズの結晶粒を用
いた発光素子における作用について。About the action in the light emitting device using the crystal grains of extremely small size of 10 to 40 Å.
【0017】絶縁性の膜を薄く形成しておくことによ
り、これをはさむ導電性材料(電極として用いる)に電
圧をかけたとき、膜中にトンネル電流が流れる。絶縁性
の膜は極微小結晶粒を挟み込んでいるから、トンネル電
流は微小粒によるポテンシャルの井戸を介して流れる。
即ち、微小粒に電流が注入される。ポテンシャルの井戸
にキャリアが注入されれば、キャリアの再結合が生ず
る。この時、微小粒は量子サイズ効果により直接遷移型
のバンド構造にシフトしているから、再結合により主と
してフォトン即ち光が放出される。絶縁性の膜や電極に
透明のものを使えば、これらのものを透過して光が放出
され、電極側に光の出口を設けることができる。透明材
料の例としては、絶縁膜、導電膜で、それぞれ、SiO
2 やボロン/リン添加ガラス、および、Indium tin ox
ide(ITO)、などがある。By forming a thin insulating film, a tunnel current flows in the film when a voltage is applied to a conductive material (used as an electrode) sandwiching the insulating film. Since the insulating film sandwiches the extremely fine crystal grains, the tunnel current flows through the potential well of the fine grains.
That is, an electric current is injected into the fine particles. If carriers are injected into the potential well, carrier recombination occurs. At this time, since the fine particles shift to a direct transition type band structure due to the quantum size effect, mainly photons, that is, light are emitted by recombination. If a transparent insulating film or electrode is used, light is emitted through these films, and a light outlet can be provided on the electrode side. An example of the transparent material is an insulating film or a conductive film, each of which is SiO 2.
2, glass with boron / phosphorus addition, and Indium tin ox
ide (ITO), etc.
【0018】[0018]
(実施例1)本発明の製造方法により、直径 20 Åの結
晶Si微小粒を形成し、それをチャネルに用いて単一電
子トランジスタを作製した例について述べる。(Example 1) An example in which crystalline Si fine particles having a diameter of 20 Å were formed by the manufacturing method of the present invention and used as a channel to manufacture a single electron transistor will be described.
【0019】まず、作製したトランジスタの構造を図4
(c)に示す。ソース端子9、ドレイン端子10間に電
圧をかけ結晶Si微小粒5を介してソース・ドレイン間
電流を流し、この電流をゲート端子8にかける電圧でO
N/OFFする。ゲート端子8に電圧がかかっていない
時は、微小粒5において量子サイズ効果によって発現す
るクーロン・ブロッケイド現象のため、電流は流れない
(OFF状態)。ゲート端子8に電圧をかけ微小粒5間
のトンネル抵抗を量子抵抗(h/4(e*e) ,h;プランク定
数,e;素電荷量)以下にすれば、クーロン・ブロッケ
イドが破れて、電流が流れる(ON状態)。First, the structure of the produced transistor is shown in FIG.
It is shown in (c). A voltage is applied between the source terminal 9 and the drain terminal 10 to cause a source-drain current to flow through the crystalline Si microparticles 5, and the current is applied to the gate terminal 8 at O
N / OFF. When no voltage is applied to the gate terminal 8, a current does not flow (OFF state) due to the Coulomb blockade phenomenon that appears in the fine particles 5 due to the quantum size effect. If a voltage is applied to the gate terminal 8 and the tunnel resistance between the fine particles 5 is set to a quantum resistance (h / 4 (e * e), h; Planck's constant, e; elementary charge amount) or less, the Coulomb blockade is broken, A current flows (ON state).
【0020】以下、結晶Si微小粒およびそれを用いた
単一電子トランジスタの作製について順に説明する。抵
抗率 0.003 Ωcm の低抵抗Siウェハ1を用い、通常の
選択酸化法により、素子形成領域以外の表面に厚さ 250
0 Å のSiO2 膜2を形成し、素子分離領域とした
(図2(a)参照)。次に、このウェハを酸素雰囲気中
で熱処理し、素子形成領域の表面に厚さ 40 Å のSi
O2 膜2を形成した(図2(b)参照)。この上に、
CVD法により厚さ 1000 Å のタングステン膜3を堆
積し、これをマスクを用いたドライ・エッチングにより
図2(c)に示すようにパターニングした。これらは最
終的にはそれぞれソース、ドレインとして用いる。The production of crystalline Si fine particles and a single-electron transistor using the same will be described below in order. Using a low resistance Si wafer 1 with a resistivity of 0.003 Ωcm, a thickness of 250 is formed on the surface other than the element formation area by the normal selective oxidation method.
A SiO 2 film 2 of 0 Å was formed as an element isolation region (see FIG. 2A). Next, this wafer is heat-treated in an oxygen atmosphere to form a 40 Å thick Si film on the surface of the element formation region.
An O 2 film 2 was formed (see FIG. 2B). On top of this,
A 1000 Å thick tungsten film 3 was deposited by the CVD method, and this was patterned by dry etching using a mask as shown in FIG. 2C. These are finally used as a source and a drain, respectively.
【0021】試料を超高真空槽に導入して 125 ℃に加
熱し、この温度に保持しながら、電子ビーム蒸着法によ
り、基板のSiO2 膜2表面へ 0.1 Å/sec. の堆積速
度でSi原子を供給した。これにより、試料表面に直径
20 Å,高さ 10 Åの半球形非晶質Si微小粒4を 2
0 Åの間隔で 形成した(図3(a)参照)。この時、
堆積所要時間は20秒であり、30 rpm の速度で基板を
10回転させた。この後、500 ℃に昇温し、1時間の熱
処理を行なって、非晶質Si微小粒4を結晶化した。The sample was introduced into an ultra-high vacuum chamber and heated to 125 ° C., and while maintaining this temperature, an electron beam evaporation method was used to deposit Si atoms on the surface of the SiO 2 film 2 at a deposition rate of 0.1 Å / sec. Was supplied. This allows the diameter on the sample surface to
20 Å and 10 Å high hemispherical amorphous Si microparticles 4
They were formed at an interval of 0Å (see Fig. 3 (a)). This time,
The required deposition time was 20 seconds, and the substrate was rotated 10 times at a speed of 30 rpm. Then, the temperature was raised to 500 ° C. and heat treatment was performed for 1 hour to crystallize the amorphous Si fine particles 4.
【0022】次に、SiH4 ,O2 ,PH3 ,B2
H5 を原料ガスに用いた化学気相堆積法(Chemical Va
por Deposition;CVD)によりボロン/リン添加ガラ
ス6を堆積し、これを800℃の熱処理によるリフロー
で表面を平坦化し、結晶化したSi微小粒5のないとこ
ろで厚さ 50 Å 、あるところで厚さ 40 Å とした(図
3(b)参照)。Next, SiH4, O2, PH3, B2
Chemical vapor deposition using H5 as source gas (Chemical Vapor Deposition)
Boron / phosphorus added glass 6 is deposited by por deposition (CVD), the surface is flattened by reflow by heat treatment at 800 ° C., the thickness is 50 Å in the absence of crystallized Si fine particles 5, and the thickness is 40 in some places. Å (see Fig. 3 (b)).
【0023】再びタングステン膜3をCVD法により堆
積し、マスクを用いたドライエッチングでゲート電極7
の形状に成形した(図3(c)参照)。The tungsten film 3 is deposited again by the CVD method, and the gate electrode 7 is formed by dry etching using a mask.
It was molded into the shape (see FIG. 3 (c)).
【0024】層間絶縁膜としてSiO2 膜2をCVD
法により堆積し(図4(a)参照)、集積回路の製造工
程において通常に行なわれるとおり、配線(図4(b)
参照)及びパッシベーション膜形成を行ない、ゲート端
子8、ソース端子9、ドレイン端子10、基板電位端子
11を形成した(図4(c)参照)。CVD of SiO 2 film 2 as an interlayer insulating film
Method (see FIG. 4 (a)) and wiring (FIG. 4 (b)) as is normally done in the integrated circuit manufacturing process.
And a passivation film were formed to form a gate terminal 8, a source terminal 9, a drain terminal 10, and a substrate potential terminal 11 (see FIG. 4C).
【0025】基板電位端子11およびソース端子9を接
地し、ゲート端子8に負、ドレイン端子10に正の電圧
を印加してこの半導体装置の動作を調べ、ゲート電圧に
よってドレイン電流がねらいどおり ON/OFF することを
確認した。The substrate potential terminal 11 and the source terminal 9 are grounded, a negative voltage is applied to the gate terminal 8 and a positive voltage is applied to the drain terminal 10 to check the operation of this semiconductor device, and the gate voltage turns on the drain current as desired. I confirmed that it turned off.
【0026】(実施例2)本発明の製造方法により、直
径 20 Åの結晶Si微小粒を形成し、それを用いてSi
発光素子を作製した例について述べる。(Example 2) By the manufacturing method of the present invention, crystalline Si fine particles having a diameter of 20 Å are formed, and the Si particles are used.
An example of manufacturing a light emitting element will be described.
【0027】まず、作製したSi発光素子の構造を図6
(c)に示す。上部電極13、下部電極14間に電圧を
かけてトンネル電流を流し、結晶Si微小粒5にキャリ
アを注入することにより発光を得る。First, the structure of the manufactured Si light emitting device is shown in FIG.
It is shown in (c). A voltage is applied between the upper electrode 13 and the lower electrode 14 to cause a tunnel current to flow, and carriers are injected into the crystalline Si microparticles 5 to obtain light emission.
【0028】以下、作製の流れにしたがって順に説明す
る。抵抗率 0.003 Ωcm の低抵抗Siウェハ1を用い、
通常の選択酸化法により、素子形成領域以外の表面に厚
さ 2500 Å の酸化膜を形成し、素子分離領域とした
(図5(a)参照)。次に、このウェハを酸素雰囲気中
で熱処理し、素子形成領域の表面に厚さ 30 Å のSi
O2 膜2を形成した(図5(b)参照)。Hereinafter, the manufacturing process will be described in order. Using a low resistance Si wafer 1 with a resistivity of 0.003 Ωcm,
An oxide film having a thickness of 2500 Å was formed on the surface other than the element formation region by a normal selective oxidation method to form an element isolation region (see FIG. 5A). Next, this wafer is heat-treated in an oxygen atmosphere, and the surface of the element formation region is covered with Si having a thickness of 30 Å.
An O 2 film 2 was formed (see FIG. 5B).
【0029】試料を超高真空槽に導入して 125 ℃に加
熱し、この温度に保持しながら、電子ビーム蒸着法によ
り、基板のSiO2 膜2表面へ 0.1 Å/sec. の堆積速
度でSi原子を供給した。これにより、試料表面に直径
20 Å,高さ 10 Åの半球形非晶質Si微小粒4を 20
Åの間隔で 形成した(図5(c)参照)。この時、堆
積所要時間は20秒であり、30 rpm の速度で基板を1
0回転させた。この後、500℃に昇温し、1時間の熱
処理を行なって、非晶質Si微小粒4を結晶化した。The sample was introduced into an ultra-high vacuum chamber, heated to 125 ° C., and while maintaining this temperature, Si atoms were deposited on the surface of the SiO 2 film 2 of the substrate at a deposition rate of 0.1 Å / sec. Was supplied. This allows the diameter on the sample surface to
20 Å, 10 Å high hemispherical amorphous Si microparticles 4
It was formed at intervals of Å (see Fig. 5 (c)). At this time, the deposition time is 20 seconds, and the substrate is rotated at a speed of 30 rpm.
It was rotated 0 times. Then, the temperature was raised to 500 ° C. and heat treatment was performed for 1 hour to crystallize the amorphous Si fine particles 4.
【0030】次に、SiH4 ,O2 ,PH3 ,B2
H5 を原料ガスに用いた化学気相堆積法(Chemical Va
por Deposition;CVD)によりボロン/リン添加ガラ
ス6を堆積し、これを800℃の熱処理によるリフロー
で表面を平坦化し、結晶Si微小粒5のないところで厚
さ 40 Å 、あるところで厚さ 30 Å とした(図6
(a)参照)。Next, SiH4, O2, PH3, B2
Chemical vapor deposition using H5 as source gas (Chemical Vapor Deposition)
Boron / phosphorus added glass 6 is deposited by por deposition (CVD) and the surface is flattened by reflowing by heat treatment at 800 ° C. The thickness is 40 Å where there are no crystalline Si fine particles 5, and the thickness is 30 Å where (Fig. 6
(See (a)).
【0031】この上に、光学素子で通常に報告されるよ
うに、スパッタ法により Indium tin oxide(ITO)膜1
2を堆積した。そしてこれをマスクを用いたエッチング
で所望の形状の上部電極13に成形した。更にこの上部
電極13をマスクとしてボロン/リン添加ガラス6のエ
ッチングを行ない、電極領域以外のボロン/リン添加ガ
ラス6および結晶Si微小粒5を除去した(図6(b)
参照)。これは、結晶Si微小粒5を伝わって上部電極
13間に不要な電流が流れるのを防ぐためである。On top of this, an Indium tin oxide (ITO) film 1 was formed by sputtering, as is commonly reported for optical elements.
2 was deposited. Then, this was formed into an upper electrode 13 having a desired shape by etching using a mask. Further, the boron / phosphorus-added glass 6 was etched by using the upper electrode 13 as a mask to remove the boron / phosphorus-added glass 6 and the crystalline Si fine particles 5 other than the electrode region (FIG. 6B).
reference). This is to prevent unnecessary current from flowing between the upper electrodes 13 along the crystalline Si fine particles 5.
【0032】その後に、集積回路の製造工程において通
常に用いられている技術を使って、パッシベーションと
配線を行ない、素子作製を完了した(図6(c)参
照)。After that, passivation and wiring were carried out by using a technique usually used in the manufacturing process of the integrated circuit, and the device fabrication was completed (see FIG. 6C).
【0033】こうしてできた素子の上部電極端子15と
下部電極端子16に電圧を印加し観察したところ、青色
発光が観察された。即ち、本発明により所望の発光素子
が作製できたことを確認した。When a voltage was applied to the upper electrode terminal 15 and the lower electrode terminal 16 of the thus-produced device and the device was observed, blue light emission was observed. That is, it was confirmed that the desired light emitting element could be manufactured by the present invention.
【0034】[0034]
【発明の効果】本発明によれば、高信頼性の単一電子素
子および青〜緑色発光のSi発光素子が作製できるた
め、単一電子素子による大容量・高速・低消費電力のL
SIと青〜緑色Si発光素子を用い、大量データ転送・
処理の光/電気融合システムを実現することが可能にな
る。According to the present invention, a highly reliable single electron element and a blue to green light emitting Si light emitting element can be manufactured.
Large amount of data transfer using SI and blue-green Si light emitting element
It becomes possible to realize an optical / electrical fusion system of processing.
【図1】本発明の製造方法の原理を説明する図である。FIG. 1 is a diagram illustrating the principle of a manufacturing method of the present invention.
【図2】第1の実施例を示す図である。FIG. 2 is a diagram showing a first embodiment.
【図3】第1の実施例を示す図である。FIG. 3 is a diagram showing a first embodiment.
【図4】第1の実施例を示す図である。FIG. 4 is a diagram showing a first embodiment.
【図5】本発明の半導体装置の構造と第2の実施例を示
す図である。FIG. 5 is a diagram showing a structure of a semiconductor device of the present invention and a second embodiment.
【図6】本発明の半導体装置の構造と第2の実施例を示
す図である。FIG. 6 is a diagram showing a structure of a semiconductor device of the present invention and a second embodiment.
1…Siウエハ,2…SiO2 膜,3…タングステン
膜,4…非晶質Si微小粒,5…結晶Si微小粒,6…
ボロン/リン添加ガラス,7…ゲート電極,8…ゲート
端子,9…ソース端子,10…ドレイン端子,11…基
板電位端子,12…Indium tin oxide(ITO)膜,13
…上部電極,14…下部電極,15…上部電極端子,1
6…下部電極端子。1 ... Si wafer, 2 ... SiO 2 film, 3 ... Tungsten film, 4 ... Amorphous Si microparticles, 5 ... Crystalline Si microparticles, 6 ...
Boron / phosphorus-doped glass, 7 ... Gate electrode, 8 ... Gate terminal, 9 ... Source terminal, 10 ... Drain terminal, 11 ... Substrate potential terminal, 12 ... Indium tin oxide (ITO) film, 13
... upper electrode, 14 ... lower electrode, 15 ... upper electrode terminal, 1
6 ... Lower electrode terminal.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鯨井 裕 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Whalei 1-280, Higashikoigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.
Claims (4)
て、結晶粒の構成元素を一旦非晶質微小粒として堆積
し、これを熱処理することにより結晶化することを特徴
とする結晶粒の形成方法。1. A method of forming crystal grains on a different type of substrate, characterized in that the constituent elements of the crystal grains are once deposited as amorphous fine grains and are crystallized by heat treatment. Forming method.
子ビーム輸送により行なわれる特許請求の範囲第1項記
載の結晶粒の形成方法。2. The method for forming crystal grains according to claim 1, wherein the deposition of the constituent elements is performed by atomic / molecular beam transport in a vacuum.
の材料がSiO2である特許請求の範囲第1項記載の結
晶粒の形成方法。3. The method for forming crystal grains according to claim 1, wherein the constituent element of the crystal grains is Si and the material of the substrate is SiO2.
ギャップの大きい材料ではさみ、それをさらに電極では
さみ、電極間に電圧をかけることにより電荷を結晶粒に
注入してこれを発光させる半導体装置。4. The energy of the crystal grains is higher than that of the crystal grains.
A semiconductor device in which a material with a large gap is sandwiched, which is further sandwiched by electrodes, and electric charges are injected into crystal grains by applying a voltage between the electrodes to emit light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19815394A JP3256091B2 (en) | 1994-08-23 | 1994-08-23 | Crystal grain forming method and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19815394A JP3256091B2 (en) | 1994-08-23 | 1994-08-23 | Crystal grain forming method and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0864525A true JPH0864525A (en) | 1996-03-08 |
| JP3256091B2 JP3256091B2 (en) | 2002-02-12 |
Family
ID=16386350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19815394A Expired - Fee Related JP3256091B2 (en) | 1994-08-23 | 1994-08-23 | Crystal grain forming method and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3256091B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5260495A (en) * | 1991-08-23 | 1993-11-09 | Union Carbide Chemicals & Plastics Technology Corporation | Monoalkylene glycol production using highly selective monoalkylene glycol catalysts |
| US6103600A (en) * | 1997-09-24 | 2000-08-15 | Sharp Kabushiki Kaisha | Method for forming ultrafine particles and/or ultrafine wire, and semiconductor device using ultrafine particles and/or ultrafine wire formed by the forming method |
| JP2002518850A (en) * | 1998-06-19 | 2002-06-25 | イギリス国 | Single charge carrier transistor, method of retaining charge carriers in quantum dots, and detection method |
| US7098092B2 (en) | 2002-12-10 | 2006-08-29 | Electronics And Telecommunications Research Institute | Single electron device, method of manufacturing the same, and method of simultaneously manufacturing single electron device and MOS transistor |
| JP2009522754A (en) * | 2005-12-28 | 2009-06-11 | グループ フォア セミコンダクター インコーポレイテッド | Pixel structure for solid state light emitting devices |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5388954B2 (en) | 2010-06-14 | 2014-01-15 | キヤノン株式会社 | Light emitting device and manufacturing method thereof |
-
1994
- 1994-08-23 JP JP19815394A patent/JP3256091B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5260495A (en) * | 1991-08-23 | 1993-11-09 | Union Carbide Chemicals & Plastics Technology Corporation | Monoalkylene glycol production using highly selective monoalkylene glycol catalysts |
| US6103600A (en) * | 1997-09-24 | 2000-08-15 | Sharp Kabushiki Kaisha | Method for forming ultrafine particles and/or ultrafine wire, and semiconductor device using ultrafine particles and/or ultrafine wire formed by the forming method |
| JP2002518850A (en) * | 1998-06-19 | 2002-06-25 | イギリス国 | Single charge carrier transistor, method of retaining charge carriers in quantum dots, and detection method |
| JP4864202B2 (en) * | 1998-06-19 | 2012-02-01 | キネティック リミテッド | Single charge carrier transistor, method for holding charge carriers in quantum dots, and detection method |
| US7098092B2 (en) | 2002-12-10 | 2006-08-29 | Electronics And Telecommunications Research Institute | Single electron device, method of manufacturing the same, and method of simultaneously manufacturing single electron device and MOS transistor |
| JP2009522754A (en) * | 2005-12-28 | 2009-06-11 | グループ フォア セミコンダクター インコーポレイテッド | Pixel structure for solid state light emitting devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3256091B2 (en) | 2002-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6103600A (en) | Method for forming ultrafine particles and/or ultrafine wire, and semiconductor device using ultrafine particles and/or ultrafine wire formed by the forming method | |
| US6998697B2 (en) | Non-volatile resistance variable devices | |
| CN100375284C (en) | Methods of forming nonvolatile variable resistance devices and methods of forming silver selenide comprising structures | |
| KR100268936B1 (en) | A method of forming for quantum dot of semiconductor device | |
| US6060743A (en) | Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same | |
| US7015497B1 (en) | Self-aligned and self-limited quantum dot nanoswitches and methods for making same | |
| US6054349A (en) | Single-electron device including therein nanocrystals | |
| TWI385790B (en) | Polysilicon plug bipolar transistor for phase change memory | |
| JP2005268724A (en) | Electronic device and manufacturing method thereof | |
| KR102102252B1 (en) | Semiconductor device and its manufacturing method | |
| JP2002543596A (en) | Electrostatically controlled tunneling transistor | |
| CN105742291A (en) | Floating gate memory and preparation method and control method therefor | |
| JP3761319B2 (en) | Manufacturing method of semiconductor device | |
| JP3256091B2 (en) | Crystal grain forming method and semiconductor device | |
| US7190075B2 (en) | Method of forming smooth polycrystalline silicon electrodes for molecular electronic devices | |
| KR101200813B1 (en) | Flash memory device comprising metal nano particle and fabrication method thereof | |
| CN101253629B (en) | Memory device employing abrupt metal-insulator switching and method of operation thereof | |
| CN114094009B (en) | A resistive memory device based on multiple resistive switching layers and a method for manufacturing the same | |
| KR100947180B1 (en) | Method of manufacturing polysilicon thin film transistor | |
| US20180205031A1 (en) | Vertically integrated nanotube and quantum dot led for active matrix display | |
| JP4532892B2 (en) | Organic EL element and organic EL display device | |
| JP2523019B2 (en) | Field effect type semiconductor device | |
| JPH0878669A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN116504642A (en) | Active layer manufacturing method and semiconductor device | |
| KR20090011334A (en) | Flash memory device comprising metal nanoparticles and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071130 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081130 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081130 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091130 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101130 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101130 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111130 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111130 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121130 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |