JPH0864703A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to reduce the number of mask steps for the stacked gate forming process, prevent the reliability of the gate oxide film from decreasing, and improve the transistor characteristics and reduce the manufacturing cost. Provide a scaleable EEPROM. [Structure] First and second poly-Si layers 18 and 24 are laminated on a Si substrate 11, and the first poly-Si layer 18 and the substrate 11 are laminated.
A memory cell array in which a plurality of memory cell units, each of which is formed by connecting a plurality of cell transistors for performing writing and erasing by exchanging charges between them, are arranged, and each memory cell unit is connected to a bit line through a selection transistor, In an EEPROM having a peripheral circuit provided in the peripheral portion of the memory cell array, the select transistor and the transistor of the peripheral circuit have a structure in which first and second poly-Si layers 18 and 24 are laminated similarly to the cell transistor. First and second poly-Si layer 1 having a gate of
8 and 24 are in partial contact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device in which a plurality of memory cells having a MOS transistor structure are connected to form a memory cell unit.

[0002]

2. Description of the Related Art In recent years, a nonvolatile semiconductor memory device (EEPROM) which can be electrically rewritten and can be highly integrated.
As a unit, a plurality of memory cells are set as one unit, a data line (bit line) is connected to the unit, and the number of contacts with the data line is reduced to achieve high integration.
M is known. For example, it is known that a plurality of memory cells are connected in series to form a NAND cell. FIG. 13 is a plan view showing one NAND cell of this type of EEPROM, and FIGS.
It is A ', BB' sectional drawing.

Eight memory cells (cell transistors) M1 to M8 are formed in a region surrounded by an element isolation insulating film 82 of a p-type silicon substrate (or a wafer having a p-type well formed on an n-type silicon substrate) 81. Two selection transistors S1,
NAND cells having S2 are arrayed. NAN
As a memory cell forming the D cell, a floating gate 84 (84 ₁ , 84 ₂ , ...) Of a first-layer polycrystalline silicon film is formed on a substrate 81 via a first gate insulating film 83, and a second gate is formed. A control gate 86 (86 ₁ , 86 ₂ ,
…) Are formed.

The gate insulating films of the select transistors S1 and S2 are formed simultaneously with the second gate insulating film 85, and their gate electrodes 88 ₁ and 88 ₂ are formed simultaneously with the control gate 86. The control gate 86 of each memory cell is continuously formed in the row direction to form a word line. An n-type diffusion layer 87 serving as a source / drain is formed between the memory cells, and the source / drain is connected in series so as to be shared by adjacent ones to form a NAND cell.

Writing and erasing operations of this NAND cell type EEPROM are carried out by exchanging charges by a tunnel current between the substrate 21 and the floating gate 84. And
Such a NAND cell type EEPROM has a conventional NO
Compared with the R type, it has an advantage that the number of contacts is significantly reduced and high integration is possible.

A conventional process for forming these NAND cells will be described with reference to FIGS.

FIGS. 15 and 16 show the steps of forming memory cells and select gates in the bit line direction in the conventional stacked gate processing, and FIGS. 17 and 18 show the steps of forming memory cells and select gates in the word line direction. 19 and 20
Shows a process of forming a peripheral low voltage transistor. In each figure, (a) is a tunnel oxide film mask step, (b) is a first polysilicon layer mask step, (c) is an ONO mask step, and (d) is a low voltage gate oxide step. Later, (e) is after the second polysilicon cell mask step, (f) is after the second polysilicon peripheral mask step,
(G) shows after the etching step of the second polysilicon layer.

After the LOCOS or trench isolation process, the well formation and the channel formation, a laminated gate formation process is performed. Here, only the stacked gate forming process is illustrated. First, as shown in (a), a select gate oxide film is grown (step 1), and then a mask process is performed to define a tunnel oxide film region (step 2). Next, the select gate oxide film is removed (step 3), the resist is further removed (step 4), and a thin tunnel oxide film is grown as shown in (b) (step 5). After this, a first polysilicon layer is laminated (step 6) and a mask process is performed (step 7) to define the floating gate.

Next, the first polysilicon layer is selectively etched (step 8), the resist is further removed (step 9), and then an ONO layer is formed as shown in (c) (step 10). Then, a mask process for leaving the memory cell region covered with the resist is executed (step 11).

Next, as shown in (d), the ONO and the first polysilicon layer are removed in the peripheral transistor region (steps 12 and 13). Next, the resist is removed (step 14), the select gate oxide film is removed from the peripheral region (step 15), and the high voltage gate oxide film is grown (step 16). Then, a mask process for exposing only the peripheral region is executed (step 17). High voltage gate oxide is removed from this region (step 1
8). Then, the resist is removed (step 19).

Next, as shown in (e), a low-voltage gate oxide film is grown (step 20), and then a second polysilicon layer is laminated (step 21). This second polysilicon layer is used to form word lines, select gates and gates of peripheral transistors. And
A resist is applied on the second polysilicon layer and a mask process is performed (step 22). Subsequently, the second polysilicon layer is etched (step 23), ONO is etched (step 24), and the first polysilicon layer is further etched (step 25). Then, the resist is removed (step 26), after this so-called stacked gate etching process,
As shown in (f), a mask process is performed (step 2
7) Define peripheral transistors, then etch peripheral gates (step 28). Then, the resist is removed (step 29). The stacked gate forming process ends after performing the reoxidation process (step 30).

[0012] Here, the process of the conventional stacked gate processing described above will be described in the following itemized form.

(1) Growth of selective gate oxide film (2) PEP treatment of tunnel oxide film (FIGS. 15, 17 and 19)
(A)) (3) Etching treatment of SiO ₂ (4) Resist removal (5) Growth of tunnel oxide film (6) Formation of first polysilicon layer (7) PEP treatment of first polysilicon layer (Fig. 15) , (B) of FIGS. 17 and 19) (8) Etching of the first polysilicon layer (9) Removal of resist (10) Formation of ONO (11) PEP treatment of ONO ((of FIG. 15, FIG. 17 and FIG. 19) c)) (12) ONO etching (13) First polysilicon layer etching (14) Resist removal (15) SiO ₂ etching treatment (16) High voltage gate oxide film growth (17) Low voltage gate oxide film PEP treatment ((d) in FIGS. 15, 17 and 19) (18) SiO ₂ etching treatment (19) Resist removal (20) Low voltage gate oxide film growth (21) Second polysilicon layer formation (22) PEP treatment of the second polysilicon layer ((e) in FIGS. 16, 18 and 20) (23) Etching of the second polysilicon layer (24) Etching of ONO (25) First Etching (26) resist removal of Rishirikon layer (27) PEP process of the second polysilicon periphery (FIGS. 16, 18
And (f) in FIG. 20) (28) Etching treatment for the second polysilicon (29) Resist removal (((g) in FIGS. 16, 18 and 20) (30) Reoxidation treatment for stacked gate However, the conventional processing has the following problems: 6 times of mask process and 4 times of conventional process.
A stacked gate memory cell structure and peripheral transistors are formed by performing the oxidation process once. The final thickness of the select gate oxide film is
It is determined in the selective gate oxide film growing step (step 1) and the tunnel oxide film growing step (step 5). The thickness of the tunnel oxide film is determined only by the tunnel oxide film growth step (step 5). The final thickness of the high voltage gate oxide film is the high voltage gate oxide film growth step (step 16).
And the low voltage gate oxide film growth step (step 20). The thickness of the low voltage gate oxide film is determined only in the low voltage gate oxide film growth step (step 20). The disadvantage of this process is that it requires multiple mask steps and multiple oxidation steps.

Further, the select gate oxide film and the high breakdown voltage Vpv
There is a process in which the resist is directly deposited on the system oxide film, resulting in deterioration of reliability. Further, when the NH ₄ F-etching step and the low-voltage oxide region to NH ₄ F-etching a tunnel oxide portion in the resist mask by a resist mask, the reliability of the tunnel oxide film and the low-voltage oxide film is lowered due to contamination There is a problem.

[0015]

As described above, the conventional E
In the EPROM, a large number of mask steps (6 times) and a large number of oxidation steps (4 times) are required, resulting in a complicated manufacturing process and an increase in manufacturing cost. Further, there is a problem in that the reliability of the selective gate oxide film and the high breakdown voltage Vpp oxide film is lowered due to the contact with the resist, and the reliability of the tunnel oxide film and the low voltage oxide film is lowered due to etching contamination.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce the number of mask steps for forming a laminated gate, and to prevent contact with a resist and etching contamination. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of preventing the reliability of the gate insulating film from being deteriorated, improving the transistor characteristics and reducing the manufacturing cost, and a manufacturing method thereof.

[0017]

The essence of the present invention is to simplify the process steps and heat steps by using a two-layer poly laminated type having the same structure as the memory cell for the gate electrode of the peripheral transistor. In addition, the peripheral gate electrode and the select transistor may be formed of a third-layer polysilicon electrode which is not used for forming a memory cell to simplify the process.

That is, according to the present invention (claim 1), the first-layer conductive film and the second-layer conductive film are laminated on the semiconductor substrate, and writing and erasing are performed by exchanging charges between the first-layer conductive film and the substrate. A nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cell units, each of which is formed by connecting a plurality of cell transistors, is arranged; and a peripheral circuit provided in a peripheral portion of the memory cell array. The transistor has a gate having a structure in which a first-layer conductive film and a second-layer conductive film are stacked, and the first-layer conductive film and the second-layer conductive film are electrically connected to each other. .

According to the present invention (claim 2), a first-layer conductive film and a second-layer conductive film are laminated on a semiconductor substrate, and writing and erasing are performed by exchanging charges between the first-layer conductive film and the substrate. A plurality of memory cell units each having a plurality of cell transistors connected to each other are arranged, each memory cell unit being connected to a data line through a selection transistor, and a memory cell array provided in a peripheral portion of the memory cell array. In a nonvolatile semiconductor memory device including a peripheral circuit, the select transistor and the transistor of the peripheral circuit have a gate having a structure in which a first-layer conductive film and a second-layer conductive film are stacked, and It is characterized in that the film and the second-layer conductive film are electrically connected.

According to the present invention (claim 3), in the method for manufacturing a nonvolatile semiconductor memory device having the above structure, a first gate insulating film is formed in a cell transistor formation region on a semiconductor substrate, and the other region is formed. A step of forming a second gate insulating film having a thickness larger than that of the first gate insulating film, a step of forming a first-layer conductive film on the first and second gate insulating films, and a first-layer conductive film. Forming a third gate insulating film thicker than the first gate insulating film on the film, and removing at least a part of the third gate insulating film in the select transistor forming region and the peripheral circuit forming region, The step of forming the second-layer conductive film on the third gate insulating film and the exposed first-layer conductive film is performed simultaneously with the same mask in the cell transistor formation region, the selection transistor formation region, and the peripheral circuit formation region. Characterized in that it comprises a step of patterning the first layer and the second Soshirubedenmaku.

According to the present invention (claim 4), a first-layer conductive film and a second-layer conductive film are laminated on a semiconductor substrate, and writing and erasing are performed by exchanging charges between the first-layer conductive film and the substrate. A plurality of memory cell units each having a plurality of cell transistors connected to each other are arranged, each memory cell unit being connected to a data line through a selection transistor, and a memory cell array provided in a peripheral portion of the memory cell array. In the nonvolatile semiconductor memory device including a peripheral circuit, the selection transistor and the transistor of the peripheral circuit have a gate formed of a third-layer conductive film.

According to a fifth aspect of the present invention, in the method for manufacturing a nonvolatile semiconductor memory device having the above structure, a step of forming a first-layer conductive film on a semiconductor substrate via a first gate insulating film, A step of forming a second-layer conductive film on the first-layer conductive film through a second gate insulating film that is thicker than the first gate insulating film; and patterning the first-layer and second-layer conductive films. A step of forming a cell transistor, a step of forming a third-layer conductive film in a select transistor formation region and a peripheral circuit formation region through a third gate insulating film having a thickness larger than that of the first gate insulating film, and a third step Patterning the layer conductive film to form a selection transistor and a transistor of a peripheral circuit.

[0023]

According to the present invention, the gates of the selection transistor and the transistor of the peripheral circuit are formed together with the cell transistor.
Since the first-layer conductive film and the second-layer conductive film have a laminated structure, the respective gates can be patterned simultaneously using the same mask. Therefore, it is possible to reduce the number of times of the mask process for forming the stacked gate and the oxidizing process for forming the gate insulating film as compared with the conventional process, which greatly simplifies the manufacturing process and also the gate oxide film contamination process. Can be reduced. Therefore, low cost,
It is possible to achieve high reliability.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) The same oxide film is used for the select gate and the low voltage peripheral transistor, and the order of oxidation is changed so that the high voltage gate oxide film grows first and the tunnel oxide film grows last. The number of oxidation treatments is 4
From 3 times to 3 times, the overall oxidation time and temperature decrease. This reduces diffusion of channel formation and improves transistor characteristics. Further, if the manufacturing process is changed so that the stacked gate memory cell structure and the peripheral transistor can be formed at the same time, the number of mask processes is six.
The number of times is reduced from 5 to 5, resulting in a simple and inexpensive manufacturing process.

1 to 6 are sectional views showing the manufacturing steps of the EEPROM according to the first embodiment of the present invention. 1 and 2 show a process of forming memory cells and select gates in the bit line direction, and FIGS. 3 and 4 show a process of forming memory cells and select gates in the word line direction.
5 and 6 show a process of forming a peripheral low voltage transistor. In each figure, (a) is a low voltage gate oxide film mask step, (b) is a tunnel oxide film mask step, (c) is a first polysilicon layer mask step, and (d) is an ONO mask. After the process, (e) is after the second polysilicon film mask process, and (f) is polysilicon / ONO.
/ After the polysilicon structure etching process is shown.

The manufacturing process of this embodiment will be described below with reference to FIGS. After the LOCOS or trench isolation process and the well formation and channel formation, a laminated gate formation process is performed. Here, only the stacked gate forming process is illustrated.

First, as shown in FIG.
After forming the element isolation oxide film 12 by LOCOS, a high voltage gate oxide film (not shown) is grown on the substrate 11. (Step 1). Then, a mask process is performed to define a low voltage gate oxide film (step 2). Then, the high voltage gate oxide film is removed (step 3) and the low voltage gate oxide film (second gate insulating film) 13 is grown (step 5).

Next, as shown in (b), another mask process is performed (step 6) to define the tunnel oxide film region. That is, a pattern of the resist 15 having an opening in the cell transistor formation region is formed.

Next, as shown in (c), the exposed oxide film 13 is removed (step 7), and the resist 15 is further added.
Are removed (step 8), and then a tunnel oxide film (first gate insulating film) 17 is grown (step 9). After that, the first polysilicon layer (first-layer conductive film) 18 is formed (step 10). Next, a mask process (step 11) is performed to define the floating gate. That is, a pattern of the resist 19 having an opening in the slit of the floating gate is formed.

Next, as shown in (d), the first polysilicon layer 18 is etched (step 12). Then, after removing the resist 19 (step 13),
An ONO film (third gate insulating film) 21 is formed (step 14), a mask process is performed (step 15), and contacts are formed between the select gate and the first and second polysilicon layers for peripheral transistors. That is, a pattern of the resist 22 having a partial opening in the selection gate and peripheral transistor formation region is formed. The contact between the first and second polysilicon and the entire surface of the gate may be performed.

Next, as shown in (e), the ONO film 2
1 (step 16) and after removing the resist 22 (step 17), the second polysilicon layer (second
A layer conductive film 24 is formed (step 18). This second
The polysilicon layer 24 is used to form word lines, select gates and gates of peripheral transistors. And
A mask process is performed to define word lines, select gates and gates of peripheral transistors (step 19). That is, a pattern of the resist 25 for forming the gate is formed.

Next, as shown in (f), the second polysilicon layer 24 is etched (step 20), and ONO is performed.
The film 21 is etched (step 21), and the first polysilicon layer 18 is further etched (step 22).
Then, the resist 25 is removed (step 23). The stacked gate forming process ends after performing the reoxidation process step (step 24).

Here, the process of the stacked gate processing of the present embodiment described above will be described in the following items.

(1) Growth of high voltage gate oxide film (2) PEP treatment of low voltage gate oxide film ((a) of FIGS. 1, 3 and 5) (3) Etching treatment of SiO ₂ (4) Resist Removal (5) Growth of low voltage gate oxide film (6) PEP treatment of tunnel oxide film (Figs. 1, 3 and 5)
(B)) (7) Etching treatment of SiO ₂ (8) Removal of resist (9) Growth of tunnel oxide film (10) Formation of first polysilicon layer (11) PEP treatment of first polysilicon layer (Fig. 1) , (C) of FIGS. 3 and 5) (12) Etching of the first polysilicon layer (13) Removal of resist (14) Formation of ONO (15) PEP treatment of ONO ((of FIG. 1, FIG. 3 and FIG. 5) d)) (16) ONO etching (17) Resist removal (18) Formation of second polysilicon layer (19) PEP treatment of second polysilicon layer ((e) of FIGS. 2, 4 and 6) ( 20) Etching of the second polysilicon layer (21) Etching of ONO (22) Etching of the first polysilicon layer (23) Removal of resist ((f) in FIGS. 2, 4 and 6) (24) Re-stacking gate Oxidation treatment As described above, in this embodiment, the stacked gate memory cell structure and the peripheral transistor can be formed by performing the masking process five times and the oxidizing process three times. Can. The final thickness of the high voltage gate oxide film is the high voltage gate oxide film growth step (step 1).
And low-voltage gate oxide film growth height (step 5) and tunnel oxide film growth step (step 9). The final thickness of the low voltage (or selective) gate oxide film is determined in the low voltage gate oxide film growth step (step 5) and the tunnel oxide film growth step (step 9). The thickness of the tunnel oxide film is determined only by the tunnel oxide film growth step (step 9).

As described above, according to the present embodiment, the number of masking steps is reduced from 6 to 5, and the number of gate oxidation processes is reduced from 4 to 3 as compared with the conventional process. And by reducing the number of mask processes,
The manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, since the number of oxidation treatments is reduced, diffusion in channel formation is reduced, and transistor characteristics can be improved.

(Embodiment 2) When the same oxide film is used for the select gate and the low voltage peripheral transistor, the number of oxidation processes is reduced from 4 to 3 and the overall oxidation time and temperature are reduced. This reduces diffusion of channel formation and improves transistor characteristics. The fabrication process was modified so that the select gate and the gate of the peripheral transistor were simultaneously formed using the third polysilicon layer, and if the same oxide was used for the select gate and the low voltage peripheral transistor, the mask The number of steps is reduced from 6 to 4, resulting in a simple and inexpensive manufacturing process.

7 to 12 are sectional views showing the manufacturing steps of the EEPROM according to the second embodiment of the present invention. 7 and 8 show the formation of memory cells and select gates in the bit line direction, FIGS. 9 and 10 show the formation of memory cells and select gates in the word line direction, and FIGS. 11 and 12 show peripheral low voltage transistors. Shows formation. In each figure, (a) shows after the first polysilicon layer mask step,
(B) is after the second polysilicon film mask step, (c) is after the low voltage gate oxide film mask step, (d) is after the third polysilicon film mask step, and (e) is the etching of the third polysilicon film. It shows after the process.

The manufacturing process of this embodiment will be described below with reference to FIGS. After the LOCOS or trench isolation process and the well formation and channel formation, a laminated gate formation process is performed. Here, only the stacked gate forming process is illustrated.

First, as shown in FIG.
A tunnel oxide film (first gate insulating film) 17 is grown on it (step 1), and immediately after that, a first polysilicon layer (first layer conductive film) 18 is formed (step 2). Then
A mask process is performed (step 3) to define the floating gate. That is, a pattern of the resist 19 having an opening in the slit of the floating gate is formed. Then, after etching the first polysilicon layer 18 (step 4),
The resist 19 is removed (step 5).

Next, as shown in (b), an ONO film (second gate insulating film) 21 is formed (step 6), and then a second polysilicon layer (second conductive film) 24 is formed (step 6). Step 7). Then, a mask process is performed to define the word line (step 8). That is, a pattern of the resist 25 for forming the gate is formed.

Then, as shown in (c), the second polysilicon layer 24 is etched (step 9), and the ONO film 2 is formed.
Etching 1 (step 10) and further etching the first polysilicon layer 19 (step 11). Then, after removing the resist 25 (step 12), the tunnel oxide film 17 is removed (step 13), and a high voltage gate oxide film 30 used for reoxidation of the stacked gate memory cell structure is grown (step 14). ). Thereafter, a mask process is performed to define the region of the low voltage gate oxide film (step 15). That is, a pattern of the resist 32 that covers the area other than the high voltage gate formation region is formed.

Next, as shown in (d), the high voltage gate oxide film 30 is removed (step 16), and the resist 32 is formed.
(Step 17), the low voltage gate oxide film (third gate insulating film) 34 is grown (step 1).
8). After that, a third polysilicon layer (third-layer conductive film) 35 is formed (step 19). Next, another mask process (step 20) is performed to define the select gate and the gates of the peripheral transistors. That is, a pattern of the resist 36 for forming the select gate and the gate of the peripheral transistor is formed.

Next, as shown in (e), the third polysilicon layer 35 is etched (step 21), and the resist 36 is removed (step 22). The stacked gate forming process is completed by the reoxidation process step (step 2).
3).

Here, the process of the stacked gate processing of this embodiment described above will be described in the following items.

(1) Growth of tunnel oxide film (2) Formation of first polysilicon layer (3) PEP treatment of first polysilicon layer ((a) in FIGS. 7, 9 and 11) (4) 1 Polysilicon layer etching treatment (5) Resist removal (6) ONO formation (7) Second polysilicon layer formation (8) Second polysilicon layer PEP treatment (see FIGS. 7, 9 and 11 ( b)) (9) Etching of the second polysilicon layer (10) Etching of ONO (11) Etching of the first polysilicon layer (12) Removal of resist ((c) of FIGS. 7, 9 and 11) (13) ) Tunnel oxide film etching (14) High voltage gate oxide film growth and stacked gate reoxidation process (15) Low voltage gate oxide film PEP process (FIGS. 7, 9 and 11 (c)) (16) PEP formation of SiO ₂ etching (17) the resist is removed (18) low-voltage gate oxide growth (19) the third polysilicon layer (20) third polysilicon layer ((D) in FIGS. 8, 10 and 12) (21) Etching of the third polysilicon layer (22) Removal of resist ((e) of FIGS. 8, 10 and 12) (23) Third poly Re-oxidation Treatment of Silicon Layer As described above, in this embodiment, the stacked gate memory cell structure and the peripheral transistor can be formed by four masking steps and three oxidizing steps. The final thickness of the high voltage gate oxide film is determined by the high voltage gate oxide film growth process (step 1
4) and low voltage gate oxide film growth (step 18)
It is decided by and. The final thickness of the low voltage (or select) gate oxide is determined by the low voltage gate oxide growth process (step 1
8) alone. The thickness of the tunnel oxide film is determined only by the tunnel oxide film growth step (step 1).

Thus, according to the present embodiment, the effect of reducing the number of masking steps from 6 times to 4 times and the number of gate oxidation treatments from 4 times to 3 times can be obtained as compared with the conventional process. And by reducing the number of mask processes,
The manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, since the number of oxidation treatments is reduced, diffusion in channel formation is reduced, and transistor characteristics can be improved.

The present invention is not limited to the above embodiments. Although the NAND cell in which a plurality of memory cells are connected in series has been described in the embodiment, the present invention is not limited to this, and an AND cell or DI in which a plurality of memory cells are connected in parallel is used.
It can also be applied to NOR cells. It can also be applied to a NOR cell without a select gate. Further, the material of the conductive film is not limited to polysilicon, and can be appropriately changed according to the specifications. Further, the material, film thickness, etc. of the gate insulating film can be changed as appropriate according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0049]

As described above, according to the present invention, the gate electrode of the peripheral transistor is a two-layer poly laminated type having the same structure as the memory cell to simplify the process step and the heat step, or the peripheral gate electrode. Also, the selection transistor is formed by the third-layer polysilicon electrode not used for forming the memory cell, and the process is simplified, so that the number of mask steps for the stacked gate forming process can be reduced and the use of the resist It is possible to realize the nonvolatile semiconductor memory device and the manufacturing method thereof, which can prevent the reliability of the gate insulating film from being deteriorated due to contact with the substrate and etching contamination, and can improve the transistor characteristics and reduce the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first half of a process of forming a memory cell and a select gate in a bit line direction of an EEPROM according to a first embodiment.

FIG. 2 is a cross-sectional view showing the latter half of the process of forming memory cells and select gates in the bit line direction of the EEPROM according to the first embodiment.

FIG. 3 is a cross-sectional view showing the first half of the process of forming memory cells and select gates in the word line direction of the EEPROM according to the first embodiment.

FIG. 4 is a sectional view showing the latter half of the process of forming memory cells and select gates in the word line direction of the EEPROM according to the first embodiment.

FIG. 5 is a cross-sectional view showing the first half of the forming process of the peripheral low-voltage transistor of the EEPROM according to the first embodiment.

FIG. 6 is a cross-sectional view showing the latter half of the process of forming a peripheral low voltage transistor of the EEPROM according to the first embodiment.

FIG. 7 is a cross-sectional view showing the first half of the process of forming memory cells and select gates in the bit line direction of the EEPROM according to the second embodiment.

FIG. 8 is a sectional view showing the latter half of the process of forming memory cells and select gates in the bit line direction of the EEPROM according to the second embodiment.

FIG. 9 is a sectional view showing the first half of the step of forming memory cells and select gates in the word line direction of the EEPROM according to the second embodiment.

FIG. 10 is a sectional view showing the latter half of the process of forming memory cells and select gates in the word line direction of the EEPROM according to the second embodiment.

FIG. 11 is a cross-sectional view showing the first half of the forming process of the peripheral low voltage transistor of the EEPROM according to the second embodiment.

FIG. 12 is a cross-sectional view showing the latter half of the forming process of the peripheral low voltage transistor of the EEPROM according to the second embodiment.

FIG. 13 is a plan view showing one NAND cell of a conventional EEPROM.

14 is a sectional view taken along the line AA ′, BB ′ of FIG.

FIG. 15 is a cross-sectional view showing the first half of the step of forming memory cells and select gates in the bit line direction in the conventional stacked gate processing.

FIG. 16 is a cross-sectional view showing the latter half of the step of forming memory cells and select gates in the bit line direction in the conventional stacked gate processing.

FIG. 17 is a cross-sectional view showing the first half of the step of forming memory cells and select gates in the word line direction in the conventional stacked gate processing.

FIG. 18 is a cross-sectional view showing the latter half of the step of forming memory cells and select gates in the word line direction in the conventional stacked gate processing.

FIG. 19 is a cross-sectional view showing the first half of a peripheral low-voltage transistor formation process in conventional stacked gate processing.

FIG. 20 is a cross-sectional view showing the latter half of the process for forming a peripheral low-voltage transistor in conventional stacked gate processing.

[Explanation of symbols]

 11 ... Si substrate 12 ... Element isolation oxide film 13 ... Low voltage gate oxide film (second gate insulating film) 15, 19, 22, 25, 32, 36 ... Resist 17 ... Tunnel oxide film (first gate insulating film) 18 First polysilicon layer (first conductive film) 21 ONO film (second or third gate insulating film) 24 Second polysilicon layer (second conductive film) 34 Low voltage gate oxidation Film (third gate insulating film) 35 ... Third polysilicon layer (third layer conductive film)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (5)

[Claims] 1. A first-layer conductive film and a second-layer conductive film are stacked on a semiconductor substrate, and a plurality of cell transistors are connected to perform writing and erasing by transferring charges between the first-layer conductive film and the substrate. In a non-volatile semiconductor memory device including a memory cell array in which a plurality of memory cell units are arranged, and a peripheral circuit provided in a peripheral portion of the memory cell array, the transistors of the peripheral circuit include a first-layer conductive film. A nonvolatile semiconductor memory device having a gate having a structure in which a second-layer conductive film is laminated, and being electrically connected to the first-layer conductive film and the second-layer conductive film. 2. A first-layer conductive film and a second-layer conductive film are laminated on a semiconductor substrate, and a plurality of cell transistors for writing and erasing by transferring charges between the first-layer conductive film and the substrate are connected to each other. A non-volatile semiconductor including a memory cell array in which a plurality of memory cell units are arranged, each memory cell unit is connected to a data line through a selection transistor, and a peripheral circuit provided in a peripheral portion of the memory cell array. In the memory device, the selection transistor and the transistor of the peripheral circuit are:
A non-volatile semiconductor having a gate having a structure in which a first-layer conductive film and a second-layer conductive film are stacked, and electrically connecting the first-layer conductive film and the second-layer conductive film. Storage device. 3. A first-layer conductive film and a second-layer conductive film are stacked on a semiconductor substrate, and a plurality of cell transistors for writing and erasing by transferring charges between the first-layer conductive film and the substrate are connected. A non-volatile semiconductor including a memory cell array in which a plurality of memory cell units are arranged, each memory cell unit is connected to a data line through a selection transistor, and a peripheral circuit provided in a peripheral portion of the memory cell array. In the method for manufacturing a memory device, a first gate insulating film is formed in a cell transistor forming region on a semiconductor substrate, and a second gate insulating film having a film thickness thicker than the first gate insulating film is formed in other regions. A step of forming a first-layer conductive film on the first and second gate insulating films, and forming a third gate insulating film thicker than the first gate insulating film on the first-layer conductive film And a step of removing at least a part of the third gate insulating film in the select transistor forming region and the peripheral circuit forming region, and forming a second conductive film on the third gate insulating film and the exposed first conductive film. Non-volatile, including a step of forming and a step of patterning the first layer and the second layer conductive film using the same mask at the same time in the cell transistor formation region, the selection transistor formation region and the peripheral circuit formation region. Manufacturing method of semiconductor memory device. 4. A first-layer conductive film and a second-layer conductive film are stacked on a semiconductor substrate, and a plurality of cell transistors for writing and erasing by transferring charges between the first-layer conductive film and the substrate are connected. A non-volatile semiconductor including a memory cell array in which a plurality of memory cell units are arranged, each memory cell unit is connected to a data line through a selection transistor, and a peripheral circuit provided in a peripheral portion of the memory cell array. In the memory device, the selection transistor and the transistor of the peripheral circuit are:
A nonvolatile semiconductor memory device having a gate formed of a third-layer conductive film. 5. A first-layer conductive film and a second-layer conductive film are laminated on a semiconductor substrate, and a plurality of cell transistors for writing and erasing by transferring charges between the first-layer conductive film and the substrate are connected. A non-volatile semiconductor including a memory cell array in which a plurality of memory cell units are arranged, each memory cell unit is connected to a data line through a selection transistor, and a peripheral circuit provided in a peripheral portion of the memory cell array. In the method of manufacturing a memory device, a step of forming a first-layer conductive film on a semiconductor substrate via a first gate insulating film, and a second thicker film than the first gate insulating film on the first-layer conductive film. A step of forming a second-layer conductive film via a gate insulating film, a step of patterning the first-layer and second-layer conductive films to form a cell transistor, a select transistor formation region and a peripheral circuit type The third gate insulating film, which is thicker than the first gate insulating film, is interposed in the formed region.
A method of manufacturing a non-volatile semiconductor memory device, comprising: a step of forming a layer conductive film; and a step of patterning a third layer conductive film to form a select transistor and a transistor of a peripheral circuit.