JPH0865625A - Memory access device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the efficiency of initialization data writing process during TV manufacturing. [Structure] When a predetermined operation button of the remote controller 12 is operated, infrared rays are emitted from a built-in light emitting section and are received by a light receiving section incorporated in the CPU 1 of the TV microcomputer section 11.
Converted to the corresponding signal. The CPU 1 transmits the I ² C bus 5, the I ² C bus terminal 13 and the I ² C bus 14 to
The initialization data stored in the memory built in the PC 6 is read out and written in the NVRAM 3. NVRA
The initialization data written in M3 is read by the CPU 1 and transferred to a predetermined address of the built-in RAM based on the pointer table stored in the built-in ROM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device suitable for use in writing data to an IC memory in a television receiver, for example.

[0002]

2. Description of the Related Art Conventionally, when writing data in a non-volatile memory (NVRAM) in a television receiver (TV), a TV microcomputer 1 and a personal computer (PC) 6 for controlling the entire TV as shown in FIG. Are connected by a predetermined signal line 4 and an I ² C bus 5. The NVRAM 3 is connected to the I ² C bus 5.

When a predetermined signal is input from the PC 6, the parallel port (PIO) 2 supplies it to a CPU incorporating it. When a predetermined signal is supplied from the PIO 2, the CPU sets the I ² C bus 5, which was initially set in the master mode, to the slave mode.

The NVRAM 3 is an I ² C bus 5 from the PC 6.
It is adapted to store data supplied via the.

Next, the procedure will be described with reference to FIG. First, the user turns on the data transmission start switch of the PC 6 to start data transmission. PC6 is
A predetermined signal is transmitted to the PIO 2 of the TV microcomputer 1 via the signal line 4. This signal is P connected to the signal line 4.
After being received by IO2, it is supplied to the CPU.

When a predetermined signal is supplied from PIO2, the CPU sets the I ² C bus 5 in the slave mode. On the other hand, on the PC 6 side, the I ² C bus 5 is set to the master mode. As a result, the I ² C bus 5 is released to the PC 6, and the signal output from the PC 6 can be supplied to the CPU via the I ² C bus 5.

Next, the PC 6 transfers, for example, predetermined data stored in the built-in RAM to the NVRAM 3 via the I ² C bus 5. When the data transfer is complete, the PC
Reference numeral 6 now reads the data transferred to the NVRAM 3 and compares it with the predetermined data stored in the RAM of the PC 6 to confirm that the data has been correctly written to the NVRAM 3.

In this case, as described above, a predetermined signal is supplied (triggered) from the PC 6 side to the TV microcomputer 1 side via the signal line 4, and the predetermined data of the PC 6 is supplied to the TV microcomputer 1. Although it was supplied, the TV microcomputer 1 triggers the PC 6 to
It is also possible to supply the predetermined data of 1 to the TV microcomputer 1 via the I ² C bus 5.

That is, first, when the I ² C bus 5 on the PC 6 side is set in the slave mode and a predetermined data transfer start switch of the TV microcomputer 6 is turned on, the TV microcomputer 1
Transmits control start data to the PC 6 via the I ² C bus 5 to put the I ² C bus 5 in the slave mode.
When this control start data is received by the PC 6,
6 puts the I ² C bus 5 in master mode. And P
C6 stores the data stored in the RAM, for example, as I ² C.
Transfer to the NVRAM 3 via the bus 5.

When this transfer is completed, the PC 6 is now
The data transferred to VRAM3 is read out and it is read by PC6
NVRAM compared with the data stored in RAM
Confirm that this data was written correctly in 3.

When predetermined data is written in the NVRAM 3, the data is transferred by the CPU to the RAM incorporated in the TV microcomputer 1. The data transferred to the RAM is C controlled by a predetermined application program.
Reading or writing is performed by the PU.

At this time, the address of the data stored in the RAM and NVRAM 3 has the structure shown in FIG. 14 or 15. That is, in RAM,
The start address is set to a predetermined fixed address, and data is stored in order from that address. On the other hand, in the NVRAM 3, data is sequentially stored from the start address 00.

The NVR thus transferred to the RAM
The data of AM3 is stored in the same order as when it was stored in NVRAM3. Therefore, NVRAM3
When the data stored in the RAM is transferred to the RAM, efficient block transfer can be performed. In addition, NVR
Since the data start address of the data stored in the AM3 is not in the memory space of the CPU, the address 00 of the NVRAM3 is different from the start address of the RAM in the CPU, but the data arrangement order is the same. From the CPU, the data in the RAM and the data in the NVRAM 3 can be equally accessed in the same order.

As described above, when the data in the RAM is read or written by the predetermined application program, the order of the data stored in the RAM is the same as the order of the data stored in the NVRAM 3. Therefore, for example, when creating an application program, it is necessary to design carefully so that the size of data and the address at which the data is stored do not change between the RAM and the NVRAM 3.

That is, at the time of creating a program by the assembler, for example, label 1 EQU 0000H label 2 EQU 0002H label 3 EQU 0003H label 4 EQU 0005H is described, and an absolute address in RAM corresponding to the label name is set in advance and data is set. It is necessary to specify the length in advance.

Further, as shown in FIG.
There are two types, one with 8 bits per word and one with 16 bits per word.
The order and contents of data in the RAM 3 are the same, and access to them is basically possible by the same method.

[0017]

Conventionally, as described above, the T
For example, NVRAM connected to the I ² C bus 5 in V
Assuming that the arrangement order of the data stored in the IC or memory such as 3 and the arrangement order of the data stored in the RAM of the TV microcomputer in the TV are the same, an external jig (PC ), The data is directly written via the I ² C bus 5 in the TV.

In this case, the arrangement order of the data in the NVRAM 3 is determined in advance, and PC 6 to N are arranged in accordance with the arrangement order.
Data is written in the VRAM 3 via the I ² C bus 5, and a program is created by the assembler on the premise of the arrangement order of the data.

Therefore, from the PC 6 to the NVRAM 3 in the TV
When writing data to the memory, it is necessary to know the arrangement order of the data in the NVRAM 3 in advance. Also, NVRA
The program must be created so that the data is arranged in the same order as the arrangement order of the data stored in M3, which is a troublesome problem.

Further, when a relocatable program is created by a C compiler or the like, and the CPU temporarily transfers the data stored in the NVRAM 3 to the RAM and accesses it, the order of data arrangement in the RAM is such that the program is compiled. Alternatively, there is a problem that the desired data may not be accessible because the data may be different for each link.

Further, the format of the data stored in the NVRAM 3 and the format of the data stored in the RAM must be the same, and there is a problem that the data format of the NVRAM 3 cannot be changed.

The present invention has been made in view of such a situation, and the data in the relocatable RAM and N
The data stored in the VRAM 3 can be associated with each other. Even if the arrangement order of the data in the RAM is changed, the arrangement order of the data in the NVRAM remains fixed, and the I NVRA through the ² C bus 5
Data is written to M3 or data can be read from NVRAM3.

[0023]

A memory access device of the present invention stores one or a plurality of data having a predetermined size, and the stored data is accessed by an absolute address (for example, FIG. 2 RAM 29),
Second storage means for randomly storing the data and accessing the data by a relative address (eg, the NVR of FIG. 2).
AM3) and a pointer table storage means for storing a pointer table in which the relative address and size of this data stored in the second storage means are described in the order of the data stored in the first storage means (for example, FIG. ROM 2
8) and the first data to be stored based on the size of the data stored in the pointer table storage means.
Corresponding means (for example, the TV microcomputer 1 in FIG. 2) that associates the address of the storage means with the address of the second storage means, the address of the first storage means in which the data associated by the correspondence means is stored, and the second storage Data transfer means (for example, the TV microcomputer 1 in FIG. 2) for transferring data from the first storage means to the second storage means or from the second storage means to the first storage means based on the address of the means is provided. Characterize.

The second storage means may store structure type data.

Further, the data transfer means can sequentially transfer the data supplied from the external device to the first storage means.

[0026]

In the memory access device according to the first aspect, the RAM 29 stores one or more data having a predetermined size, and the stored data is accessed by the absolute address. Also, with NVRAM3,
The data is stored randomly and the data is accessed by relative address. Further, the ROM 28 stores a pointer table in which the relative address and size of this data stored in the second storage means are described in the order of the data stored in the first storage means.

Further, the TV microcomputer 1 determines, based on the size of the data stored in the pointer table storage means, the address of the first storage means in which this data is stored and the second storage means.
The addresses of the storage means are associated with each other, and the address of the first storage means in which the associated data is stored, and the second
Data is transferred from the first storage means to the second storage means or from the second storage means to the first storage means based on the address of the storage means. Therefore, the arrangement order of the data stored in the NVRAM 3 can be fixed regardless of the arrangement order of the data stored in the RAM 29.

In the memory access device according to the second aspect, the RAM 29 can store structure type data. Therefore, NVRAM3
The arrangement order of the data stored in the RAM 29 and the arrangement order of the data stored in the RAM 29 can be the same, and the data can be transferred in block units.

In the memory access device according to the third aspect, the TV microcomputer 1 can sequentially transfer the data supplied from the external device to the NVRAN 3.
Therefore, under the control of the TV microcomputer 1, the initialization data stored in the externally connected device is read out and the NV in the TV is read.
It can be written in RAM3.

[0030]

1 is a block diagram showing the configuration of an embodiment of a TV microcomputer section of a television receiver (TV) to which the memory access device of the present invention is applied. The TV microcomputer unit 11 includes a CPU (TV microcomputer) 1 and NVRAM 3, and the TV microcomputer 1 and NVRAM 3 can transmit and receive data to and from each other via the I ² C bus terminal 5.

The TV microcomputer section 11 is adapted to receive remote control data from the remote control 12 and perform a predetermined tuning control. Also, via the I ² C bus terminal 13,
It is connected to an external personal computer (PC) 6 connected to the TV microcomputer section 11, and can transmit and receive data via the I ² C bus 14.

FIG. 2 is a block diagram showing a more detailed structure of the TV microcomputer 1 shown in FIG. TV microcomputer 1
The remote control reception processing unit 21 is configured to receive, for example, infrared rays emitted from the light emitting unit built in the remote controller 12 and convert the infrared rays into a corresponding signal. The OSD display control processing unit 23 controls the built-in OSD display function unit 24 to read the font data of a predetermined character or graphic stored in the font ROM 25, convert it into the corresponding RGB signal, and then supply it to the CRT 26. Has been done.

The accumulator 27 is adapted to perform a predetermined arithmetic processing. The ROM 28 stores a system program, an application program, and program control data, and further stores a pointer table described later. RAM29 is
The application program stored in the ROM 28 is expanded and executed, and various data is stored and accumulated as control data and a transmission or reception buffer.

The PIO control processing section 30 is adapted to receive predetermined data via the parallel port (parallel I / F) 31 or transmit predetermined data via the parallel port 31. SIO control processing unit 32
Via the serial port (serial I / F) 33
Receives predetermined data, or serial port 33
Predetermined data is transmitted via the.

The interrupt control processing unit 34 is adapted to detect interrupts of the TV microcomputer 1, set priorities, switch level interrupts or edge interrupts, or control interrupt enable or disable. The timer processing unit 35 is configured to perform predetermined timer processing, counter measurement processing, watchdog timer processing, and the like.

The I ² C bus control processing unit 36, the I ² C bus 5
Various ICs are controlled via the.

The respective units in the TV microcomputer 1 are connected via an internal bus 22 so that they can mutually input / output control signals and data.

The signal processing IC 37 is connected to the TV microcomputer 1 via the I ² C bus 5, and the I ² C bus control processing unit 3
Under the control of 6, predetermined signal processing is performed. The AV input / output processing IC 38 is connected to the TV microcomputer 1 via the I ² C bus 5, and the I ² C bus control processing unit 3
By the control of 6, the input / output of the AV signal is switched.

The nonvolatile memory (NVRAM) 3 is I ²
It is connected to the TV microcomputer 1 via the C bus 5 and stores initialization data and the like under the control of the I ² C bus control processing unit 36. The volume control IC 39 is I ² C
It is connected to the TV microcomputer 1 via the bus 5, and the audio signal is controlled by the control of the I ² C bus control processing unit 36. The TELETEXT processing IC40
It is connected to the TV microcomputer 1 via the I ² C bus 5, I ² C
The TELETEXT is controlled by the bus control processing unit 36.
It is designed to receive (character multiplex in Japan) broadcasts or perform predetermined control.

The I ² C bus terminal 13 outputs control data or data supplied from the TV microcomputer 1 via the I ² C bus 5 to an external device connected thereto, or outputs data from the external device. It is designed to be entered.

Next, the NVRAM 3 of the TV microcomputer section 11
A method of writing the initialization data (setting information) will be described below. The initialization data used by the microcomputer control program of the TV microcomputer 1 include "channel information", "volume sound information", "image quality information", "deflection system IC setting information", "TELETEXT IC setting information", “Destination setting information” and “Specification setting information for each model”.

When the TV is shipped, default values of these information, destination-specific information or model-specific specification information are written in the factory, and further, default values such as various TV image setting information are preset. To be done.

When the power switch of the TV is turned on, the TV microcomputer 1 first transfers these data stored in the NVRAM 3 to the RAM 29 and refers to the data stored in the RAM 29 to control the TV. I'm trying to do.

This is because the access speed of the NVRAM 3 is generally slow, and if various set values are read from the NVRAM 3 and various ICs are controlled based on the data, processing cannot be performed at a practical speed. Therefore, when the power of the TV is turned on, the data in the NVRAM 3 is transferred to the RAM 29, which has a faster access speed than the NVRAM 3, and only when the data in the RAM 29 is changed, the data in the NVRAM 3 corresponding to the data is updated. I'm trying to do.

As a method of writing the above-mentioned initialization data in the NVRAM 3 when manufacturing the TV in the TV having the configuration as shown in FIG. 1 or 2, first, a method of directly writing in the NVRAM 3 using a jig can be considered.

Also, the TV microcomputer 1 uses the I ² C bus 14
Alternatively, there is a method of reading data stored in the external PC 6 and writing the data in the NVRAM 3 in response to a command from an external device connected via a 3-wire bus (serial bidirectional bus) not shown, for example, a personal computer (PC) 6. Conceivable.

Further, the PC 6 directly writes data to the NVRAM 3 via the I ² C bus 14 or the NVRAM 3
A method of directly reading the data from 3 can be considered. This method was described above in the prior art.

Further, the PC 6 and the TV microcomputer 1 communicate with each other via the I ² C bus 14, and the data supplied from the PC 6 is written in the NVRAM 3 by the TV microcomputer 1 or stored in the PC 6. A method of reading out is conceivable.

Furthermore, the TV microcomputer 1 and the PC 6 are connected to I ² C.
The TV microcomputer 1 reads out the initialization data stored in the PC 6 by connecting with the bus etc.
A method of writing to the NVRAM 3 of the V-microcomputer unit 11 can be considered.

FIG. 3A is a diagram showing data storage addresses when the data storage area in the RAM 29 is relocatable. Thus, the address where the data is stored is designated by the label name, and the start address is a relative address. That is, when creating (coding) a program, the areas and sizes of each data are defined in order of data numbers, and after compiling, a program (execution module) is created by a very general method of linking with a linker. The respective data may be arranged in the data storage area in the RAM 29 in the order of the data number different from that when the area is designated at the time of creating the program.

On the other hand, FIG. 3B is a diagram showing storage addresses of data in the data storage area of the NVRAM 3.
In this way, the start address of NVRAM 3 is fixed at address 00, and data is stored in the order of data numbers.

In this way, when the data order of the data stored in the RAM 29 and the data order of the data stored in the NVRAM 3 are different, the data in the NVRAM 3 is read as R
If this processing is performed in the TV microcomputer 1 when transferring to the AM 29, the TV microcomputer 1 sequentially reads out the data stored in the NVRAM 3 and transfers it to an address corresponding to a predetermined label in the storage area in the RAM 29. Just copy it.

However, using the jig, the NVRAM 3
In the case of directly writing data to the HDD, the data writing order cannot be easily changed.

FIG. 4A shows that a program (execution module) is developed by a relocatable program development method using a C compiler and a linker, and the program is executed in the RAM 29.
FIG. 6 is a diagram showing addresses of respective data arranged in a RAM 29 when expanded to. In this way, each data is arranged in an order different from the data number order.

FIG. 4B shows a NVRAM using a jig.
3 is a diagram showing a data arrangement when each data is stored in FIG. In this way, each data is stored in the NVRAM 3 in the order of the data number.

Therefore, a pointer table as shown in FIG. 4C is stored in the ROM 28, and data is moved between the RAM 29 and the NVRAM 3 based on this table. NVRAM in the pointer table
In the order of data stored in 3, the relative address (address corresponding to the label name) on the RAM 29 where each data is stored and the size of the data (number of bytes) are described. As for the size of each of them on the pointer table, the relative address on the RAM 29 where each data is stored is 2 bytes, and the size of the data is 1 byte.

For example, when the power of the TV is turned on,
A processing procedure for transferring data from the NVRAM 3 to the RAM 29 will be described with reference to the flowchart shown in FIG.

First, in step S1, as shown in FIG.
Table number P00 of the pointer table shown in (c)
1 is set in the NVRAM read pointer register. Next, in step S2, the first data pointer value in the pointer table, that is, the address corresponding to the label A001 is set in the data pointer register.

Next, in step S3, the number of bytes of the first table number in the pointer table is read and set in the counter register. Then, in step S4, the data for the number of bytes set in the counter register is read from the NVRAM 3 and is designated by the data pointer value (address corresponding to the label A001) set in the data pointer register. It is transferred to the storage area of the RAM 29.

Next, in step S5, 3 is added to the data pointer value stored in the data pointer register. As a result, the data pointer value specifies the address of the next table number P002.
Then, the label A002 stored at this address
The address corresponding to is read and stored in the data pointer register.

Next, in step S6, the address of the NVRAM 3 is calculated from the table number and the number of data of each data, and stored in the NVRAM read pointer register. For example, when the NVRAM 3 is composed of 8 bits per word, the data corresponding to the table number 5 of the pointer table is a byte obtained by adding the number of bytes of each data of the table numbers 1 to 4 in the NVRAM 3. Set the number 5 to the start address 0 of NVRAM3.
It can be seen that it is stored in the address 5 obtained by adding to the address.

Similarly, in the NVRAM 3, the data corresponding to the table number 2 of the pointer table is stored in the address 1 obtained by adding the byte number 1 of the data of the table number 1 to the start address 0 of the NVRAM 3. You can see that it is done. In the present case,
Address 1 corresponding to table number 2 of the pointer table is stored in the NVRAM read pointer register.

In step S7, for all table data described in the pointer table,
It is determined whether the processing is completed. When it is determined that the processing has been completed for all the table data described in the pointer table, the processing is completed. When it is determined that the processing has not been completed for all the table data described in the pointer table, the process proceeds to step S8, and the number of bytes (2 bytes) of the next table (in this case, table number P002) is read. , Store in counter register.

Next, in step S9, NVRAM3
Is read from the address (1 in this case) of the NVRAM 3 calculated in step S6 by the number of bytes stored in the counter register, and R indicated by the data pointer stored in the data pointer register is read.
The data is transferred to the storage area corresponding to the address in the AM 29.

Next, returning to step S5, step S5
The processing from S9 to S9 is repeated. In this way, NVRA
The data stored in M3 can be transferred to a predetermined data storage area of the RAM 29.

Next, referring to FIG. 4, the procedure for transferring the data stored in the RAM 29 to the NVRAM 3 will be described. First, the data stored at the address corresponding to the label A001 in the data storage area of the RAM 29 shown in FIG. The table number of the NVRAM 3 corresponding to the label A001 of the RAM 29 is P001 from the pointer table shown in FIG.
Therefore, the data read from the address corresponding to the label A001 of the RAM 29 is transferred to the start address of the NVRAM 3.

Next, the data stored in the address corresponding to the label A002 of the RAM 29 is read. RA
The table number of the NVRAM 3 corresponding to the label A002 of M29 is P002 from the pointer table, and the number of bytes defined in the table number before the table number P002 (in this case, the table number P001) is added. In the present case, it is 1 byte defined in the table number P001. That is, NVRAM3
The corresponding address in is the address 1 obtained by adding 1 to the start address 00 of the NVRAM 3.

Therefore, the data read from the address corresponding to the label A002 of the RAM 29 is transferred to the address 1 of the NVRAM 3.

In this way, the data in the RAM 29 can be sequentially transferred to the NVRAM 3.

When rewriting the data in the NVRAM 3 by the user's operation, first, the corresponding data in the RAM 29 is changed. Next, the table number corresponding to the data changed in the RAM 29 is retrieved from the pointer table stored in the ROM 28, and NV
The corresponding address of RAM3 is calculated. And RA
The changed data is read from M29, and the changed data is written in the calculated address of NVRAM3.

FIG. 6 is a diagram showing a procedure for directly writing data to the NVRAM 3 from a jig such as the PC 6 connected to the TV microcomputer section 11, for example. First, the write start switch is turned on on the PC 6 side. When the write switch is turned on, the PC 6 operates in the service mode (N
A signal corresponding to the start of the VRAM write mode) is transmitted to the serial port (serial IF) 33 of the TV microcomputer 1 of the TV microcomputer unit 11 via a control line (not shown).
Then, the PC 6 sets the I ² C bus 14 in the slave mode. As a result, the data transmitted from the TV microcomputer unit 11 can be received.

The TV microcomputer 1 includes the SIO control processing unit 32.
Under the control of, upon receiving this signal via the serial port 33, it reads the pointer table data stored in the ROM 28, via the internal bus 22, I ²
It is supplied to the C bus control processing unit 36. The I ² C bus control processing unit 36 sends this signal to the I ² C bus 5 and the I ² C bus terminal 1.
3 and via the I ² C bus 14 to the PC 6 side. Then, the I ² C bus 5 is set to the slave mode. As a result, the data transmitted from the PC 6 can be received.

The PC 6 can rewrite the data in the NVRAM 3 according to the data arrangement of the NVRAM 3 at the time of designing, if the arrangement of the data stored in the NVRAM 3 is not changed from the data arrangement at the time of designing. If the data arrangement stored in the NVRAM 3 is changed with respect to the data arrangement at the time of designing, NVRA can be calculated from the pointer table data.
The address in M3 can be calculated and the data in NVRAM3 can be rewritten.

FIG. 7 shows, in a RAM 29 for data of an execution module obtained by defining data in a structure format, compiling or assembling it, and linking the data in a program created by, for example, C or an assembler. The arrangement order in FIG. The structure format is, for example, a structure used in the C language or assembler, and is a data format in which its members are taken in continuous areas.

By defining the data in the structure format as described above, the data can be sequentially arranged in the RAM 29. Therefore, the arrangement order of the data in the RAM 29 and the arrangement order of the data in the NVRAM 3 can be made the same, and the data stored in the RAM 29 can be stored in the N order.
When data is transferred to the VRAM 3 or data stored in the NVRAM 3 is transferred to the RAM 29, the data can be transferred in the order in which they are arranged.

As a result, the initialization data can be written in the NVRAM 3 at the time of production or shipment by the same procedure as the conventional one. However, in this case, NVRAM3
All the data in must be defined in one structure format. For this reason, when writing directly to each member of this structure in the program, the description becomes long and unwieldy.

In order to improve this, for example, a data variable having an independent name corresponding to each member of the structure is defined, and when the power is turned on, the data in the structure format is changed to the data having the corresponding independent name. Make sure to copy it to a variable. Then, when the TV microcomputer 1 rewrites this data, the value of the data variable of each independent name, the data of the structure format, and all the corresponding data in the NVRAM 3 are rewritten.

As a result, in the program, data variables having independent names can be used for description, and it becomes easy to handle.

Next, a procedure for writing the initialization data into the NVRAM 3 from the jig (PC) 6 under the control of the TV microcomputer 1 will be described.

[0080] As shown in FIG. 8, I ² to the TV microcomputer 1
The NVRAM 3 is connected via the C bus 5, and the PC 6
TV microcomputer 1 through I ² C bus 14 and I ² C bus 5
When connected to PC, first, as shown in FIG.
When the operation button for instructing the initialization start of 6 is operated, the control signal for instructing the initialization start by the PC 6
TV microcomputer 1 through I ² C bus 14 and I ² C bus 5
Sent to.

When the TV microcomputer 1 receives from the PC 6 a control signal for instructing the start of initialization via the I ² C bus 5, it initializes the initialization data stored in a memory (not shown) in the PC 6, The data is read via the I ² C bus 5 and the I ² C bus 14, and the read data is written to a predetermined address of the NVRAM 3 via the I ² C bus 5.

In this case, the arrangement order of the data in the RAM 29 of the TV microcomputer 1 and the arrangement order of the data in the NVRAM 3 do not have to be the same as described above.
The microcomputer 1 may sequentially read the initialization data stored in the memory of the PC 6 and transfer it to the NVRAM 3.

Further, as shown in FIG. 10, the button corresponding to the start of initialization is provided on the TV microcomputer 1 side.
When the initialization starts, the initialization button of the TV microcomputer 1 is first operated. Next, from the TV microcomputer 1, PC6
The initialization data stored in the internal memory is read out via the I ² C bus 5 and the I ² C bus 14.

Then, the read initialization data is I
² Written to NVRAM 3 via C bus 5.

Next, as shown in FIG. 11, the TV microcomputer 1 and the NVRAM 3 are connected via the I ² C bus 5, and T
When the V-microcomputer 1 and the jig (PC) 6 are connected to the serial port (SIO (serial IF)) 33 of the TV microcomputer 1 via a predetermined signal line 51, first, as shown in FIG. , When the button corresponding to the initialization start of the PC 6 is operated, a control signal instructing the initialization start is supplied from the PC 6 to the serial port 33 of the TV microcomputer 1 via the signal line 51.

When a control signal instructing the start of initialization is supplied to the serial port 33 of the TV microcomputer 1, the TV microcomputer 1 reads the initialization data from the PC 6 via the signal line 51, and outputs the read signal. It is supplied to the NVRAM 3 via the I ² C bus 5. As a result, NVRAM3
Initialization data is written in a predetermined address of.

Further, when the TV microcomputer 1 is provided with a button for instructing the initialization start, as shown in FIG. 10, when the button for instructing the initialization start of the TV microcomputer 1 is operated, T
The V-microcomputer 1 reads the initialization data stored in the memory (not shown) in the PC 6 through the signal line 51,
Transfer to the NVRAM 3 via the I ² C bus 5. Then, the initialization data is written in a predetermined address of the NVRAM 3.

In the above-mentioned practical example, the NVRAM which is an electrically rewritable RAM is used.
An NVRAM built in the CPU can be used, or a RAM backed up by a battery or a RAM backed up by a large capacity and low current leakage capacitor can be used.

Further, in the above embodiment, the I ² C bus is used for the connection with the external device, but it is also possible to use the 3-wire bus or the parallel bus.

Further, in the above-mentioned embodiment, the case where the invention is applied to the microcomputer of the TV is explained.
It can be applied to all home appliances such as R (video tape recorder), CD (compact disc), and radio. Further, it can be applied not only at the time of production or shipping but also at the time of repair.

Further, when transmitting the pointer table data in the ROM to the PC, the label name is defined in ASCII format for each table in addition to the address or the number of bytes in each table, and it is sent to the PC. be able to. As a result, since a specific data name can be sent to the PC, comparison by data name can be performed, and address comparison processing can be simplified.

[0092]

According to the memory access device of the first aspect, the first storage means has a predetermined size of 1
One or more data is stored and the stored data is accessed by an absolute address. Further, the second storage means randomly stores the data, and the stored data is accessed by the relative address. Further, the pointer table storage means stores a pointer table in which the relative address and size of this data stored in the second storage means are described in the order of the data stored in the first storage means. Further, the correspondence means associates the address of the first storage means for storing this data with the address of the second storage means based on the size of the data stored in the pointer table storage means, and further,
Based on the address of the first storage means for storing the predetermined data by the transfer means and the address of the second storage means,
Since this data is transferred from the first storage means to the second storage means or from the second storage means to the first storage means, the arrangement order of the data stored in the first storage means is the second order.
It can be fixed regardless of the arrangement order of the data stored in the storage means. Therefore, even if the products have different specifications, the arrangement order of the data to be stored in the first storage means can be made the same, so that the compatibility can be provided.
It is possible to increase productivity.

According to the memory access device of the second aspect, since the second storage means can store the data of the structure structure, the data stored in the first storage means , The arrangement order of the data stored in the second storage means can be made the same, and the data can be transferred in block units. Therefore, data transfer can be performed relatively easily.

According to the memory access device of the third aspect, since the data transfer means transfers the data supplied from the external device to the first storage means in order, it is controlled by the data transfer means. The initialization data stored in the externally connected device can be read and written in the first storage means in order.

[Brief description of drawings]

FIG. 1 is a connection diagram of a TV microcomputer unit 11 and a PC 6 of a television receiver to which a memory access device of the present invention is applied.

FIG. 2 is a diagram showing a detailed configuration of a CPU (TV microcomputer) 1 in FIG.

FIG. 3 is a diagram showing a data arrangement of a relocatable RAM 29 and a data arrangement of an NVRAM 3.

FIG. 4 is a diagram showing a data arrangement of a RAM 29, a data arrangement of an NVRAM 3, and a pointer table in a ROM 28.

[FIG. 5] When the power is turned on, the TV microcomputer 1 has the NVRAM 3
5 is a flowchart showing a procedure for transferring the initialization data of the above to the RAM 29.

FIG. 6 is a diagram showing a procedure of writing data from the PC 6 to the NVRAM 3.

FIG. 7: RAM when data is structured
It is a figure which shows the data arrangement in 29, and the data arrangement in NVRAM3.

[FIG. 8] PC 6 and TV microcomputer 1 are connected to an I ² C bus 5, 14
It is a figure at the time of connecting via via.

FIG. 9 is a diagram illustrating a procedure when an initialization start control button is provided on the PC 6.

FIG. 10 is a diagram showing a procedure when the TV microcomputer 1 is provided with an initialization start control button.

11 is a diagram showing a case where the PC 6 and the TV microcomputer 1 are connected via a signal line 41. FIG.

FIG. 12 is a diagram showing a configuration of an example of a conventional memory access device.

FIG. 13 is a diagram showing a procedure for writing data to the conventional NVRAM 3.

FIG. 14 is a diagram showing a data arrangement of a conventional RAM and NVRAM.

FIG. 15 is a diagram showing a data arrangement of NVRAM having 8 bits or 16 bits per word.

[Explanation of symbols]

1 TV microcomputer 2 PIO (parallel IF (parallel port)) 3 NVRAM 4 signal line 4 5 I ² C bus 6 PC 11 TV microcomputer section 12 remote controller 13 I ² C bus terminal 14 I ² C bus 22 CPU internal bus (internal bus) ) 23 OSD display control processing unit 24 Built-in OSD display function unit 25 Font ROM 26 CRT 27 Accumulator 28 ROM 29 RAM 30 PIO control processing unit 32 SIO control processing unit 33 Serial IF 34 Interrupt control processing unit 35 Timer processing unit 36 I ² C bus control processing unit 37 signal processing IC 38 AV input / output processing IC 39 volume control IC 40 TELETEXT processing IC 51 signal line

Claims (3)

[Claims] 1. A first storage means for storing one or more data having a predetermined size, the data being accessed by an absolute address, the data being randomly stored, and the data being stored by a relative address. A second storage means to be accessed and a pointer table in which the relative address and size of the data stored in the second storage means are described in the order of the data stored in the first storage means. Pointer table storage means, and the first data stored based on the size of the data stored in the pointer table storage means
Addressing means for associating addresses of the memory means with addresses of the second memory means, address of the first memory means for storing the data associated by the memory means, and address of the second memory means And a data transfer unit for transferring the data from the first storage unit to the second storage unit or from the second storage unit to the first storage unit based on the data access unit. 2. The memory access device according to claim 1, wherein the second storage unit stores structure type data. 3. The memory access device according to claim 1, wherein the data transfer unit sequentially transfers the data supplied from an external device to the first storage unit.