JPH086790A - Processor controller - Google Patents

Abstract

(57) [Summary] [Object] To provide a processor control device that enables accurate interrupt processing control when an interrupt occurs during scalar execution in a pipeline. [Structure] A macro instruction can be executed in a pipeline, a plurality of macro instructions can be executed simultaneously, and an occurrence timing instruction unit IGM that knows the exception occurrence timing of the instruction and a scalar single execution control unit that controls scalar execution and single execution And an instruction address holding unit IA0, a request type holding unit RQA, and an instruction sequence holding unit SEQ0.
The single scalar execution holding unit MIE0, the read size holding unit RBA, the write size holding unit ACA, the request address holding unit SAR, the request automatic insertion instruction unit LST2, and the exception occurrence timing of the above instruction are in the middle of instruction execution. If it is, the request re-issue unit SARQ that enables the request to be re-issued after the exception handling is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor controller, and more particularly to controlling instruction processing of a pipeline processor. With the demand for faster processors,
Although super-pipeline and super-scalar technology have been proposed and used, super-scalar execution executes multiple instructions at the same time, so multiple exceptions occur at the same time, but the processor requires accurate interrupt handling control. It

[0002]

2. Description of the Related Art In a conventional superscalar processor,
If an exception occurs during scalar execution, that is, while executing multiple instructions at the same time, in order to guarantee an accurate interrupt, the instruction code of the execution instruction at that time is analyzed at the interrupt destination and those instructions are emulated after the exception processing is completed. When it is necessary to complete the operation and restart the execution from the next instruction sequence, or eliminate the overflow exception of the operation instruction and check it with software, insert a dedicated instruction after the operation instruction to cut the exception. It is provided.

[0003]

However, the former emulation has a drawback that the recovery process is complicated and takes a long time. When the latter dedicated instruction is used, the conventional architecture inherits the assets. In this case, it is necessary to change and extend the architecture, which is difficult to apply.

Therefore, considering a system in which superscalar execution is performed and interrupts are processed by microcode without changing the interrupt timing or the like as before,
Consider the problems that exist in that case.

In a system that does not execute in superscalar, each macro instruction executes in units of one instruction, so that the interrupts generated for instructions are in the instruction execution order and
It was limited to one. However, when an instruction is executed in superscalar, when an exception occurs, the instruction that should originally be behind the instruction in which the exception occurred is canceled, and it is necessary to execute again after the exception processing is completed.

Therefore, as a method of restart processing, it was considered to read the instruction sequence in the memory from the interrupt address or the like, analyze it, and then execute the restart instruction. However, the processing becomes complicated and the processing speed increases as described above. The decline is unavoidable. Further, if the branch instructions are executed at the same time, it is difficult to continue the execution from the branch destination because the branch operation is interrupted midway.

In the present invention, in consideration of these points, the instruction sequence analysis and the scalar execution state etc. are easily determined,
An object of the present invention is to provide a processor control device capable of easily completing and canceling an instruction.

[0008]

In order to achieve the above object, according to the invention of claim 1 of the present invention, as shown in FIG. 1, a macro instruction can be executed in a pipeline, and a plurality of macro instructions can be executed simultaneously. In other words, in a superscalar-executable processor, an instruction address holding unit IA0 that holds an instruction address of a macro instruction that can be read / written by microcode, and a request type of a macro instruction that can be read / written by microcode are held. The request type holding unit RQA, the instruction sequence holding unit SEQ0 that holds the instruction sequence of the macro instruction that is readable and writable by microcode, and whether the macro instruction that can be read and written by the microcode is scalar execution (multiple instruction execution). Holds a single scalar execution that holds whether it is a scalar execution And MIE0, read size holding unit RBA indicating a read request size macroinstructions
And a write size instructing unit ACA that is readable and writable by microcode and that indicates the write size of a request for a macro instruction, a request address holding unit SAR that is readable and writable by microcode, that holds the address of the request, and a microcode Shows that the request is divided into two when the request of the macro instruction that can be read and written crosses the boundary.
It has a request automatic insertion instructing section LST2 indicating that the latter half request of the hardware is automatically inserted, and an occurrence timing instructing section IGM indicating whether the exception occurrence timing is in the middle of instruction execution or an instruction break.

If the exception generation timing is in the middle of instruction execution, a request re-issuing section SARQ that enables the request to be reissued after the exception processing, and if the exception generation timing is an instruction break, the request is reissued. Request re-issue section SADQ that allows you to fix
To provide.

Further, in the pipe E1, as described in the invention of claim 2 of the present invention, an instruction address holding an instruction address of a macro instruction or a leading address of an instruction sequence including the instruction which can be read by microcode. Holding part I
AD, a request type holding unit RQD that holds a request type of a macro instruction or an instruction sequence including the macro instruction that is readable and writable by microcode, and a macro instruction that is readable and writable by microcode or an instruction sequence that includes the macro instruction A size holding unit ACD that holds the size of the request, a request address holding unit SAD that holds the address of the request that is readable and writable by microcode, and a macro instruction that is readable and writable by the microcode, or an instruction sequence including the macro instruction. Instruction sequence holding unit S for holding the instruction sequence of
Read / write with EQD and microcode,
A single scalar execution holding unit MI that holds whether a macro instruction or an instruction sequence including the macro instruction is scalar execution or single execution.
ED, a general register write instruction unit GRWD indicating that there is a general register write by a macro instruction readable / writable by a microcode or an instruction sequence including the macro instruction, and a macro instruction readable / writable by a microcode or the macro instruction A GR number holding unit R1WAD for an operation instruction that holds a general register write number of an operation instruction among an instruction string that includes the instruction, and a general register write of a load instruction in a macro instruction that can be read / written by microcode or an instruction string that includes the instruction It has a GR number holding unit R1WLD for load instructions that holds a number.

According to the third aspect of the present invention, the GR number holding unit R1WL for the load instruction is included among the instructions being executed by the scalar.
After clearing D and request type holding unit RQD,
Only the operation command can be completed by operating the request reissue unit SADQ. The request reissue unit SAD is cleared by clearing the operation instruction GR number holding unit R1WAD.
Operating Q allows only load and store instructions to complete.

According to the fourth aspect of the present invention, the request reissue unit SADQ is provided during the restart processing for an exception in the middle of a macro instruction.
Then, the request reissue unit SARQ is continuously operated so that the pending request and the writing to the general register can be completed.

According to a fifth aspect of the present invention, the single scalar execution holding unit MIE is provided for an exception in the middle of a macro instruction.
For example, if 0 is checked, it is judged that the exception occurred at the time of scalar execution when it is "1", and that it occurred at the time of single execution when it is "0". The scalar execution holding unit MIED is checked, and when it is “1”, it is determined that the exception occurred at the time of scalar execution, and when it is “0”, it is determined that the exception occurred at the time of single execution, and the restart processing from the exception processing is performed. To be able to change.

According to a sixth aspect of the present invention, the single scalar execution holding unit MIE0 is checked, and when it is "1", the instruction sequence holding unit SEQ0 is checked, and the instruction sequence of the scalar execution instruction sequence in which the exception has occurred is checked. Indicates that when the instruction sequence holding unit SEQ0 is “1”, the order is operation instruction → load store instruction, and when this is “0”, the order is load store instruction → operation instruction, and single scalar execution hold The section MIED is checked, and when it is "1", for example, the instruction sequence holding section SE
The QD is checked, and the instruction sequence of the scalar execution instruction sequence in which the exception has occurred is the order of operation instruction → load store instruction when this instruction sequence holding unit SEQD is “1”, and the load order when this is “0”. It indicates that the order is a store instruction → arithmetic instruction, and the restart processing from the exception processing can be changed by these pieces of information.

According to the seventh aspect of the present invention, when an exception occurs in an operation instruction, the request of the load / store instruction that is being executed at the same time is suppressed so that the exception due to the request does not occur, and the request can be re-injected. To do.

According to the eighth aspect of the present invention, when an exception occurs in an operation instruction, a request for a load / store instruction that is being executed at the same time is suppressed so that an exception due to the request does not occur. , It is possible to cancel the instruction execution completion of either or both of the load / store instruction and the operation instruction.

According to the ninth aspect of the present invention, when an exception is detected during instruction execution, if single execution is performed, the instruction next to the instruction that generated the exception is re-executed based on the address held in the instruction address holding unit IA0. If a fetch is performed and an exception occurs in a load / store instruction due to scalar execution, and the scalar instruction sequence is in the order of load / store instruction, operation instruction, and branch instruction, only the load / store instruction is completed, and refetch is performed from the operation instruction. An exception occurred in the load store instruction during scalar execution,
When the scalar instruction sequence is in the order of the operation instruction, the load store instruction, and the branch instruction, the operation instruction and the load store instruction are completed and the branch instruction is refetched.

According to the tenth aspect of the present invention, when an exception is detected at the break of an instruction, if it is a single execution, refetch is performed from the next instruction, that is, the address held in the instruction address holding unit IA0, and the load is stored by the scalar execution. When an exception occurs in an instruction and the scalar instruction sequence is in the order of load / store instruction, operation instruction, and branch instruction, only the load / store instruction is completed, refetch is performed from the operation instruction, and the exception occurs in the load / store instruction in scalar execution. When the generated scalar instruction sequence is the operation instruction, the load store instruction, and the branch instruction in this order, the operation instruction and the load store instruction are completed, and the refetch is performed from the branch instruction.

In the eleventh aspect of the present invention, when an exception is detected at a break of an instruction, an exception occurs in the arithmetic instruction in the scalar execution, and the scalar instruction string is in the order of the arithmetic instruction, the load store instruction, and the branch instruction. , If only the arithmetic instruction is completed, re-fetching is performed from the load / store instruction, an exception occurs in the arithmetic instruction during scalar execution, and the scalar instruction sequence is the load / store instruction, arithmetic instruction, and branch instruction in this order, the execution mode is changed. Set to single mode and re-fetch from the load / store instruction again.

According to the twelfth aspect of the present invention, when an interrupt occurs due to an addressing exception or an operation exception during scalar execution, the execution mode is set to single mode and refetching is performed from the next instruction to simplify the state at the time of interrupt. Generate an interrupt again in the activated state.

According to the thirteenth aspect of the present invention, when an exception of an instruction type occurs at the time of scalar execution, the load / store instruction and the arithmetic instruction are completed, the execution mode is set to the single mode, and the refetch is performed from the subsequent instructions. Perform exception processing after completing all the issuable instructions.

In the fourteenth aspect of the present invention, when the exception occurs again in the single mode and the processing is completed, the scalar mode is returned to at the time of the restart processing.

[0023]

When an interrupt occurs during the execution of an instruction, the exception detector detects this and analyzes the exception factor. For example, a TLB (Transla) is an exception due to a request instruction.
error lookup, etc. are analyzed. Then, it is determined whether the occurrence of this interrupt is an instruction break or an instruction is being executed.
Identify by looking at the GM. For example, when IGM = “0”, it is determined that the instruction is being executed, and when IGM = “1”, it is determined that the interrupt occurs at the break of the instruction.

When an interrupt is generated during the execution of an instruction, it is checked whether the single scalar execution holding unit MIE0 is "1" or "0", and when MIE0 is "0", it is judged to be a single execution and restarted. The address is set as the restart address because it is executed from the next instruction whose restart address is held in the instruction address holding unit of the pipe P1 (not shown).

However, the single scalar execution holding unit MIE0
Is "1", the scalar execution is performed, so the instruction sequence holding unit SEQ0 is checked. This SEQ0 is "0"
At this time, since the start of a plurality of instructions that are being scalar-executed is a load / store instruction (LS instruction), the instruction held by the instruction address holding unit IA0 is restarted by adding 4 which is the number of bytes of the instruction length. Set as an address.

When the instruction sequence holding unit SEQ0 is "1", the start of a plurality of instructions is an operation instruction (ALU instruction), so that the instruction next to the load / store instruction in which the interrupt has occurred is restarted. The address held in the address holding unit IA0 plus 8 is set as the restart address.

Then, exception processing, for example, in the case of a TLB fault, exception processing such as TLB entry replacement is performed, and the execution mode is returned to the scalar mode. Then, the request reissue unit SADQ reissues the request in which the exception has occurred and completes it.

Further, when there is a request issued in the cycle next to the request in which the exception has occurred, this is executed by the request re-exit unit SARQ. by the way,
When the generation timing instruction unit IGM = “1”, it means that an interrupt occurs at the break of the instruction, so exception processing is performed and the single scalar execution holding unit MIED is set to “0”.
At this time, it is determined to be single execution, the address of the instruction held in the instruction address holding unit IA0 of the pipe P0 is set as the restart address, and the request reissue unit SADQ reissues the request in which the exception occurred.

However, the single scalar execution holding unit MIED
Is "1", it is determined to be scalar execution, and then the instruction sequence holding unit SEQD is checked. When this SEQD is "0", the start of a plurality of instructions that are being scalar-executed is a load / store instruction (LS instruction), so the instruction byte holding section IAD sets the number of bytes of the instruction to 4 The added value is set as the restart address.

When the instruction sequence holding section SEQD is "1", the start of a plurality of instructions is an operation instruction (ALU instruction), so that the instruction next to the load / store instruction in which the interrupt has occurred is restarted. The address held in the address holding unit IAD plus 8 is set as the restart address.

Then, the request reissue unit SADQ reissues the request in which the exception has occurred, and completes the request. Thus, even when a plurality of instructions are being executed, when an exception occurs, exception processing for the exception is performed, the instruction in which the exception has occurred is executed again, and other instructions can be executed.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. 2 is an explanatory diagram of a pattern of instruction sequences simultaneously executed in a pipeline, FIG. 3 is an explanatory diagram of a pipeline and interrupt timing, FIG. 4 is a schematic diagram of a data processing device embodying the present invention, and FIG. 5 is one embodiment of the present invention. Example configuration diagram, Figure 6
Is a request control circuit configuration diagram, FIG. 7 is an operation explanatory diagram when an interrupt occurs during execution of an instruction (exception due to a request instruction), and FIG. 8 shows an interrupt occurrence at an instruction break (other than a request TLB fault). Operation explanatory diagram, FIG. 9
Is an operation explanatory diagram when an interrupt occurs at an instruction break (an exception occurs in the LS instruction). FIG. 10 shows an address specification exception (ADEX exception) or an operation exception (OPE).
(X exception) occurs, and FIG. 11 is an operation explanatory diagram when an instruction-related exception occurs.

First, FIG. 2 shows an instruction sequence pattern when superscalar execution is performed. In FIG. 2, LS indicates a load / store instruction, ALU indicates an arithmetic instruction, and BR indicates a branch instruction. Therefore, FIG. 2A shows a case where the instruction sequence is arranged in the order of operation instruction → load store instruction → branch instruction, and these three instructions are input at the same time, and b shows two instructions of operation instruction → load store instruction are executed simultaneously. In the case of “c”, two instructions of the operation instruction → branch instruction are simultaneously executed, “d” is the load / store instruction → operation instruction → three instructions of the branch instruction are simultaneously executed, and “e” is the load / store instruction →
The case where two operation instructions are executed simultaneously and the letter f shows the case where two load store instructions and branch instructions are executed simultaneously.

FIG. 3 shows an example of the pipeline structure and the interrupt timing in this pipeline. The control of each part of the present invention and the structure of the pipeline in the case of the embodiment use the control of FIG. Further, the instruction length of the instruction to be executed by the scalar is fixed, for example, 4 bytes.

In FIG. 3, P3 to P0 and E1 respectively indicate stages of the respective pipes, P3 is a fetch stage, P2 is a decode stage, P1 is an operation stage,
P0 is a memory access stage, and E1 is a general register (GR) write back stage. And
Indicates that the simultaneous execution instructions shown in a to f of FIG.

Further, in FIG. 3, EI is a signal End Instruct indicating that the instruction can be completed.
It is a section. If there is an exception factor when this signal is on, an interrupt occurs. REQ is a request, and a request for reading is output for a load instruction, and a request for storing is output for a write instruction. ST0 and ST1 indicate stage signals for transferring control to the request.

INT0 and INT1 are stage signals for transferring control to interrupts. There are patterns shown in FIGS. 3 (A), 3 (B) and 3 (C) at the timing at which an interrupt occurs.

FIG. 3A shows a case where an interruption occurs at an instruction break. This interrupts with the EI of the pipe P0 of the instruction. The instruction that generated the exception is the instruction, and if the request of the instruction is the exception factor, the request is suppressed and the stage ST1 does not exist. Therefore, the instruction is incomplete. In addition, the instructions in it also stop during execution. ×
The marks indicate these states. The asterisk indicates the occurrence of an interrupt factor.

FIG. 3B also shows a case where an interrupt occurs at an instruction break. In this case, it is the instruction that generated the interrupt.
This is the case when an interrupt occurs due to an attempt to execute an instruction that should not be executed, such as an undefined instruction or an instruction with an addressing exception. In this case, the interrupt is detected at the timing one ahead. If it is detected at the same timing as in FIG. 3A, the execution may end, so the interrupt is made at the immediately preceding timing. Therefore, as shown in FIG. 3 (B), the interrupt timing is the EI of the instruction, and (A)
Same timing as. Since the request for the instruction in this case does not generate an exception, the stages ST0 and ST1 for the request REQ are executed and the request is completed. But request by R
Stage ST0 is not executed for EQ.

FIG. 3C shows a case where an interrupt is made in the middle of an instruction. For example, this is the case when an exception such as a page fault occurs during continuous writing to the memory multiple times. In this case, the interrupt trigger is request R
This is the EQ stage signal ST0. This stage signal S
When T0 is ON, an interrupt is triggered if there is an exception factor.

FIG. 4 shows a data processing apparatus embodying the present invention. Reference numeral 1 denotes a memory control circuit, which has a data cache 2 and an instruction cache 3, and has a central processing unit CPU.
It reads and writes data and commands based on access requests from the.

The data cache 2 is provided with a primary cache 4 and a TLB 5. The TLB 5 checks from the CPU whether the data to be accessed exists in the primary cache 4 and, if it exists, reads it out and sends it to the CPU. If it does not exist, the CPU is notified of it.

The instruction cache 3 as well as the primary cache 6
And TLB7 are provided. The TLB 7 checks whether or not the instruction of the access destination from the CPU exists in the primary cache 6, and if it exists, it is read and passed to the CPU, and if it does not exist, it is notified to the CPU.

The CPU has a reading section 8, a decoding section 9, and a computing section 1.
0, memory access unit 11, write back unit 12, instruction buffer 13, read buffer 1
4, a general register 15, an exception detection unit 16, a request control circuit 17, a logic and microprogram holding unit 18, a deviation value addition unit 19, a request address holding unit SAR, a scalar single execution control unit SSMS and the like are provided. Note that P3 to P0 and E1 indicate pipe stages.

The exception detection unit 16 detects the occurrence of an exception such as a TLB fault or an addressing exception and its cause. Request control circuit 17
When the overflow occurs in the arithmetic unit 10, the subsequent request execution is blocked. As shown in FIG. 6, when the arithmetic unit 10 overflows and an exception occurs, an exception generation signal “1” is generated. Is output and the logic circuit 23 is turned off. Following this, when the request REQ is output from the request generation circuit 21, the logic circuit 23 is turned off, so this can be suppressed.

FIG. 6 shows a request stage circuit. The request generation circuit 21 is composed of request generation control logic, and reference numerals 22 and 24 are flip-flops for generating the request stage. When an exception occurs as a result of the operation performed by the operation unit 10, the exception occurrence signal “1” is output, the logic circuit 23 is turned off, and the stage signal ST0 of the request REQ is suppressed.

As described above, when the operation instruction and the load instruction are simultaneously executed, if the operation instruction causes an exception, the request REQ of the load instruction is suppressed. Therefore, after the interrupt is generated, the execution is switched to the single execution and the first instruction is executed. It is possible to execute again from. If the request control circuit 17 is not provided, it is difficult to realize an accurate interrupt because the load instruction is completed first when the load instruction after the operation instruction is simultaneously executed by the scalar execution. .

Logic and microprogram holding unit 1
Reference numeral 8 holds a logic circuit and a microprogram for performing interrupt control in the present invention, and when an interrupt occurs in addition to the SARQ or SADQ composed of microinstructions, depending on the exception factor thereof. Holds operating microprograms, etc. For example, when a TLB fault occurs, a microprogram corresponding thereto is stored, and when an overflow occurs in the arithmetic unit, a microprogram corresponding to this is stored.

The deviation value adding unit 19 calculates an address for reading an instruction and adds an offset value to the base value. Then, the address obtained from the addition result is used as the request address holding unit S
Hold by AR.

Also, a scalar single execution control unit SSMS for controlling the scalar execution and the single execution is provided. Figure 5
FIG. 3 is a configuration diagram of an embodiment of the present invention, in which the instruction address holding unit IA0, the request type holding unit RQA, the instruction sequence holding unit SEQ0, the single scalar execution holding unit MI.
E0, read size holding unit RBA, write size instructing unit ACA, request address holding unit SAR, request automatic insertion instructing unit LST2, generation timing instructing unit IG
M, request reissue part SARQ, SADQ, instruction address holding part IAD, request type holding part RQD, size holding part ACD, request address holding part SAD, instruction sequence holding part SEQD, single scalar execution holding part MIED, general register writing Instruction unit GRWD, operation instruction GR number holding unit R1WAD, load instruction GR
It has a number holding unit R1WLD and the like.

In addition to this, the GR number holding unit R1W for the operation instruction
A, GR number holding unit R1WL for load instruction, generation timing instruction unit IGM indicating whether instruction exception occurrence timing is in the middle of instruction execution or instruction break, register TBB in which data for register write is written, and provided in each command register The write path A, a multiplexer for selecting write data from the data via the write path or the data from the preceding stage of the pipe, a pipeline control circuit PC, etc. are provided.

In practice, the instruction address holding unit IA0 and the request automatic insertion instructing unit L, which are arranged next to the pipe P0, are arranged.
ST2, write size instruction unit ACA, read size holding unit RBA, request type holding unit RQA, request address holding unit SAR, single scalar execution holding unit MI
E0, instruction sequence holding unit SEQ0, GR for operation instruction
Number holding unit R1WA, GR number holding unit R1 for load instruction
The instruction address holding unit IAD, the size holding unit ACD, the request type holding unit RQD, the request address holding unit SAD, the single scalar execution holding unit MIED, and the instruction sequence holding unit S that are lined up next to the WL and the pipe E1.
The EQD, the GR number holding unit R1WLD for the load instruction, the GR number holding unit R1WAD for the operation instruction and the like are configured by registers.

In these registers, command information (instruction can be continuously executed when an interrupt occurs) from the upper pipe (P1 or P0) is set for each clock during normal operation. Once the interrupt is generated, the control is passed to the interrupt processing microinstruction holding unit 18-1 composed of, for example, a microcode RAM, and the microprogram corresponding to the interrupt selectively operates.

This microprogram analyzes the execution state of the macro instruction at the time of occurrence of an interrupt, and the instruction SARQ to be completed after exception processing and the instruction S to be re-executed at restart.
The ADQ is separated and the command information of the instruction to be re-executed is cleared. This clearing is performed from the write path A provided in each command register in the figure. The data to be written is preset in the register TBB.

Next, the operation of the present invention will be described. A: When an interrupt occurs during the execution of an instruction (exception due to a request instruction),
B, an interrupt occurs at an instruction break, C, an interrupt occurs at an instruction break (when an exception occurs at the LS instruction), D, an addressing exception (ADEX) / operation exception (OPEX) The case where an exception occurs, E, an instruction-related exception occurs, and the like will be described. In addition,
The control of each flowchart shown in these descriptions is performed by the logic and microprogram holding unit 18 shown in FIG.

A. When an Interrupt Occurs During Execution of an Instruction (Exception by Request Instruction) A case where an interrupt occurs during execution of an instruction will be described with reference to FIGS. 7 and 9. In this case, it is an example of FIG.
The instruction that caused the exception is in pipe P0. Also, for example, T
It is assumed that an LB fault has occurred.

(1) When an interrupt occurs during the execution of an instruction, the exception detection unit 16 shown in FIG. 4 detects this and analyzes the exception factor. Then, as an exception due to the request instruction REQ, the occurrence of the TLB fault is analyzed in the data cache 2. Then, this is notified to the logic and microprogram holding unit 18, and the microprogram for coping with the TLB fault is selectively operated based on this.

(2) First, the generation timing instructing unit IGM is checked to determine whether an interrupt occurs at an instruction break or during instruction execution. For example, when IGM = "0", it is determined that the instruction is being executed, and when IGM = "1", it is determined that the interrupt occurs at the break of the instruction.

(3) When IGM = “0”, FIG.
As shown in (C), it is determined that the instruction is being executed. Then, the single scalar execution holding unit MIE0 is read and "0" is read.
In the case of, for example, single execution is determined, and in the case of "1," it is determined as scalar execution. In the case of single execution, the restart address is the instruction address holding unit I of the pipe P1.
The address of the next instruction held in A1 (not shown) is set as the restart address.

(4) In the case of scalar execution, the instruction sequence holding unit SEQ0 is checked, and in the case of "0", for example, the heads of a plurality of instructions being scalar executed are load / store instructions (LS instructions). , In order to restart from the instruction next to the load / store instruction in which the interrupt has occurred, the address held in the instruction address holding unit IA0 plus 4 which is the number of bytes of the instruction length is set as the restart address.

(5) When the instruction sequence holding unit SEQ0 is "1", the head of the plurality of instructions is the arithmetic instruction (ALU).
Since this is an instruction), in order to restart from the instruction next to the load / store instruction in which the interrupt has occurred, the address held in the instruction address holding unit IA0 plus 8 is set as the restart address.

(6) Then, exception processing is performed. For example, T
In the case of an LB fault, the TLB entries are exchanged and the execution mode is set to the scalar mode. This may be in single mode, and running in single mode will result in poor performance, so it should be in scalar mode.

(7) The request reissue unit SADQ composed of microinstructions requests the request REQ that generated the exception.
To complete this. (8) Request reissue unit SA composed of microinstructions
The RQ executes this when there is a request issued in the cycle next to the request REQ that generated the exception.

(9) Then, execution is performed from the restart address, and the restoration is completed. By the way, in the above (2), when the generation timing instruction unit IGM = “1”, it means that the interrupt occurs at the break of the instruction, and the control as shown in FIG. 9 is performed.

(1) 'Exception processing is performed based on the exception factor, and, for example, the TLB entry is rewritten. (2) ′ Then, the single scalar execution holding unit MIED is checked, and when MIED = “0” is determined to be single execution, the address of the instruction held in the instruction address holding unit IA0 of the pipe P0 is set as the restart address. Then, the request reissue unit SADQ composed of microinstructions re-executes the request in which the exception occurred.

(3) 'However, when the single scalar execution holding unit MIED = "1", it is judged to be a scalar execution, and then the instruction sequence holding unit SEQD is checked. When this SEQD is “0”, the start of a plurality of instructions that are scalar-executed is a load / store instruction (LS instruction).
The address held in the instruction address holding unit IAD plus 4 which is the number of instruction length bytes is set as the restart address.

When the instruction sequence holding unit SEQD is "1", the heads of a plurality of instructions are operation instructions (ALU instructions), so that the instruction address holding unit IAD is restarted from the load store instruction in which the interrupt has occurred. A value obtained by adding 8 to the address held in is set as the restart address.

Then, the request reissue unit SADQ reissues the request in which the exception has occurred to complete the request. Then, execution is performed from the restart address and the process returns. B. When Interrupt Occurs at Instruction Break A case where an interrupt occurs at instruction break will be described with reference to FIG. This case is an example of FIGS. 3A and 3B, and is a case other than the request and the TLB fault.

(1) When an interrupt occurs at the break of an instruction, the exception detection unit 16 shown in FIG. 4 detects this and reads the interrupt factor to determine whether it is an operation exception (OPEX) or an addressing exception (ADEX). , Determine otherwise. The operation exception is, for example, when an undefined instruction enters the pipe, and corresponds to FIG. 3 (B). The addressing exception is, for example, a memory address alignment exception. It is necessary to deter both.

(2) In the case of an operation exception or an addressing exception, the route moves to the route (B) and then to FIG. In this case, the instruction that caused the exception is the instruction in the pipe next to the currently executing instruction.

(3) However, if it is neither an operation exception nor an addressing exception, it is judged whether it is an instruction exception. An instruction type exception is, for example, when a TLB fault occurs when an instruction is read, and this is also performed by checking the interrupt factor. (C) for imperative exceptions
The process moves to the route No. and moves to FIG. 11 described later.

(4) If it is not an instruction type exception, it is determined by checking the interrupt factor whether the exception instruction, that is, the instruction that caused the exception is a load store instruction (LS instruction) or an operation instruction (ALU). In this case, the exception of the operation instruction and the exception of the load / store instruction do not occur at the same time. In the case of an exception of the load / store instruction, the route of (A), that is, the control of (1) ′, (2) ′, (3) ′, etc. described with reference to FIG. 9 is performed.

(5) In the case of an arithmetic instruction, the single scalar execution holding unit MIED determines whether the instruction execution mode is single execution or scalar execution. Since the request of the load / store instruction is suppressed by the exception signal of the operation instruction, the instruction execution mode is determined by checking the single scalar execution holding unit MIED shown in FIG. For example, when the single scalar execution holding unit MIED is "1", it is a scalar execution, and when it is "0", it is a single execution. In single execution, there is no instruction that is executing at the same time as the instruction that caused the interrupt, so the restart address after exception processing may be the instruction stored in the instruction address holding unit IA0 of the pipe P0. At this time, the instruction address holding unit I of the pipe E1
AD contains the start address of the instruction sequence including the instruction that generated the exception.

(6) In scalar execution, there is an instruction that is being executed at the same time as the instruction that caused the interrupt, so it is necessary to check the instruction sequence. Therefore, the instruction sequence is determined by the instruction sequence holding unit SE shown in FIG.
Check QD and do. This instruction sequence holding unit S
When the EQD is, for example, "1", the operation instruction ALU is at the head, and when the EQD is "0", the load / store instruction LS is at the head. At this time, since the operation instruction is the exception, the operation instruction is completed and the operation instruction is executed after the operation instruction. That is, the restart address is the instruction sequence holding unit SE
When QD is "1", the address is held in IAD + 4, and when the instruction sequence holding unit SEQD is "0", the address is held in IAD.

(7) Here, the re-execution from the address held in the instruction address holding unit IAD means that the execution is restarted from the load / store instruction, the execution mode is changed to the single execution mode, and the execution is re-executed. By executing the instruction first by itself and then executing the operation instruction, the operation instruction alone causes an exception again and interrupts. This ensures accurate interrupts and further simplifies processing.

(8) When the head is an arithmetic instruction, the restart address is set as IAD + 4, and exception processing, eg overflow processing, is performed on the arithmetic instruction. Then, the execution mode is set to the scalar mode, and the instruction that generated the exception, that is, the operation instruction, is fetched again by the request re-sending unit SADQ composed of micro-instructions and completed.
Return.

C. If an interrupt occurs at the break of the instruction (when an exception occurs in the LS instruction), (1) ′,
As described in (2) 'and (3)', the control based on FIG. 9 is performed.

D. When an Addressing Exception (ADEX) / Operation Exception (OPEX) Occurs A case where an addressing exception (ADEX) or an operation exception (OPEX) occurs will be described with reference to FIG. This case corresponds to (B) in (2) of FIG.

In this case, the processing flow is in the case where an exception that needs to suppress the execution of the instruction occurs, and the interrupt is accepted at a timing one cycle earlier. Therefore, it is necessary to look at the information for the pipe one level above.

(1) Single scalar execution holding unit MIE0
Is checked to determine whether the instruction execution mode is single execution or scalar execution. (2) In the case of single execution, in this state, the instruction itself is aborted and the process is handed over to the OS. Therefore, the execution mode is set to the scalar mode, control is passed to the OS as an exception process, and the interruption process is performed. This instruction will not be executed any further.

(3) In the case of scalar execution, the restart address is set by the one written in the instruction address holding unit IA0. Then, the execution mode is set to the single mode, and the instruction in which the exception has occurred is detected. Then, the request reissue unit SADQ normally terminates the instruction of FIG. 3B and returns.

That is, in FIG. 8, the instruction causing the exception is shown in FIG. Therefore, FIG.
The instructions contained in (B) may be completed unconditionally. Further, since there is a possibility that scalar execution is also performed in FIG. 3B, it is difficult to determine which instruction caused the exception. Therefore, all the instruction strings in FIG. 3B are completed, and the instructions are executed one by one in the single execution mode from the beginning of the instruction string. As a result, when an exception occurs, it is interrupted by a single execution, so the exception is processed at that time.

E. When an Instruction Exception Occurs A case where an instruction exception occurs will be described with reference to FIG. This case corresponds to (C) in (3) of FIG. Since the exception in this case is an instruction-related exception, for example, a case where a TLB fault occurs when an instruction is read, the exception processing is executed after all the executable instructions are completed. If scalar execution is performed when an interrupt occurs, the load / store instruction is completed, the single execution mode is set, and the instruction is reexecuted after the load / store instruction. When there are no more instructions being executed in the pipe, it interrupts in single mode, so exception processing is executed at this time.

(1) When an interrupt occurs, the single scalar execution holding unit MIED is checked to determine whether the instruction execution mode is single execution or scalar execution. When this single scalar execution holding unit MIED is "0", for example, it is determined to be single execution. In the case of single execution, exception processing for the exception occurrence is performed, the cause of the exception occurrence is eliminated, the execution mode is set to the scalar mode, the instruction in which the exception occurred is executed again, and the operation returns.

(2) In the case of scalar execution, the instruction sequence holding unit SEQD is checked and, for example, this is "0".
At this time, it is determined that the first instruction is the load / store instruction. Finish this for this load store instruction,
In order to restart from the next instruction, the address written in the instruction address holding unit IAD plus the number of bytes 4 of the instruction length is set as the restart address.

(3) Also, the instruction sequence holding unit SEQD
Is "1", it is determined that the first instruction is the arithmetic instruction ALU. At this time, check if there is a request command,
If not, the address written in the instruction address holding unit IAD of (2) above plus the instruction length byte number 4 is set as the restart address. If there is a request command, the request command is terminated, and the restart address is set as the restart address obtained by adding 8 to the address written in the command address holding unit IAD.

(4) Then, the execution mode is set to the single mode, the instructions are sequentially executed one by one, and the instruction in which the exception is occurring is detected. Then, the corresponding process is performed, the request reissue unit SADQ re-executes the instruction in which this exception occurred, and returns.

In the above description, the instruction length is 4 bytes, but the present invention is not limited to this.

[0089]

According to the present invention described in claim 1 and claim 2, when various interrupts occur in the instruction sequence in the superscalar control, the complicated instruction code is not analyzed at high speed. It becomes possible to execute interrupt processing.

According to the present invention described in claim 3, it is possible to complete only the operation instruction or the load / store instruction. According to the present invention described in claim 4, the pending request and the writing to the general register can be completed.

According to the present invention described in claim 5, it is possible to judge whether the exception occurred at the time of scalar execution or at the time of single execution, and change the process of restarting from the exception process.

According to the present invention described in claim 6, it is possible to judge whether the order of the instruction sequence at the time of scalar execution is the order of operation instruction → load store instruction or the reverse order of load store instruction → operation instruction. , It is possible to change the restart processing from exception processing.

According to the present invention described in claim 7, when an exception such as an overflow occurs in an operation instruction, the request of the load / store instruction being executed at the same time is suppressed, the exception due to the request is prevented, and the request is re-executed. Can be input.

According to the present invention described in claim 8, it is possible to cancel the instruction execution completion of either or both of the load / store instruction and the operation instruction from the instruction sequence during the superscalar execution.

According to the present invention described in claim 9, when an exception is detected during the execution of an instruction, it is determined from which instruction the instruction can be refetched, and the correct restart processing can be performed. Claim 1
According to the present invention described in No. 0, when an exception is detected at the break of an instruction, it is possible to determine from which instruction the instruction can be refetched, and the correct restart processing can be performed.

According to the present invention described in claim 11,
When an exception is detected at an instruction break, it can be refetched from the load / store instruction. According to the twelfth aspect of the present invention, the interrupt can be generated again in a simplified state at the time of the interrupt.

According to the thirteenth aspect of the present invention, exception processing can be performed after completion of all issuable instructions. According to the present invention described in claim 14,
It is possible to generate an exception again in the single mode, perform the exception processing, and then return to the scalar mode to efficiently perform the restart processing.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an explanatory diagram of patterns of instruction sequences for simultaneous execution in a pipeline.

FIG. 3 is an explanatory diagram of pipeline stages and interrupt timings.

FIG. 4 is a schematic diagram of a data processing device embodying the present invention.

FIG. 5 is a configuration diagram of an embodiment of the present invention.

FIG. 6 is a block diagram of a request control circuit according to the present invention.

FIG. 7 is an operation explanatory diagram of the present invention when an interrupt occurs during execution of an instruction (exception due to request instruction).

FIG. 8 is an operation explanatory diagram of the present invention when an interrupt occurs at a break of an instruction (other than a request TLB fault).

FIG. 9 is an operation explanatory diagram of the present invention when an interrupt occurs at an instruction break (an exception occurs at an LS instruction).

FIG. 10 is an operation explanatory diagram of the present invention when an addressing exception (ADEX exception) or an operation exception (OPEX exception) occurs.

FIG. 11 is an explanatory diagram of the operation of the present invention when an instruction type exception occurs.

[Explanation of symbols]

IGM generation timing instruction section IBB Register to write data for writing A write path IA0 instruction address holding section RQA request type holding section SEQ0 instruction sequence holding section MIE0 single scalar execution holding section RBA read size holding section ACA write size instruction section SAR request address holding unit LST2 request automatic insertion instruction unit SARQ request re-output unit SADQ request re-output unit IAD instruction address holding unit RQD request type holding unit ACD size holding unit SAD request address holding unit SEQD instruction sequence holding unit MIED single scalar execution holding Section GRWD General register write instruction section R1WAD Operation instruction GR number storage section R1WLD Load instruction GR number storage section PC Pipeline Control circuit LMC logic microprogram holder SSMS scalar single execution control unit

Front page continuation (72) Toru Watanabe Inventor Toru Watanabe 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Takumi Maruyama 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture (72) Invention Shinya Kato 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Ponchai Chong Suvarna Paisan, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Katsunori Takeshita, Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Fukushima, Fujitsu Limited (72) Inventor Takumi Nonaka 1015 Kamiotanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Kanagawa, Ltd. Address within Fujitsu Limited (72) Inventor Atsushi Soukawa 3-4-30 Masuizumi, Kanazawa-shi, Ishikawa Stock Company within Fujitsu Hokuriku Systems

Claims (14)

[Claims] 1. A generation timing instruction unit IGM capable of executing a macro instruction in a pipeline and further executing a plurality of macro instructions at the same time, and knowing an exception generation timing of the instruction.
And a scalar single execution controller that controls scalar execution and single execution, and holds the instruction address of a macro instruction that can be read and written by microcode in a processor that does not accept an interrupt between a branch instruction and a subsequent instruction. Instruction address holding unit IA0
And a request type holding unit RQA that holds a request type of a macro instruction that is readable and writable by microcode, and an instruction sequence holding unit SE that holds an instruction sequence of a macro instruction that is readable and writable by microcode
Q0, a single scalar execution holding unit MIE0 that can be read / written by microcode and holds whether the macro instruction is scalar execution or single execution, and a read size that indicates the read size of a macro instruction request that can be read / written by microcode. A holding unit RBA, a write size holding unit ACA that is readable and writable by microcode and that indicates the write size of a request for a macro instruction, and a request address holding unit S that is readable and writable by microcode and that holds the address of the request.
A request that indicates that the request is divided into two when the AR and microcode readable / writable macro instruction requests cross the boundary, and that the latter half of the request is automatically inserted by hardware. A processor including an automatic insertion instructing unit LST2 and a request reissue unit SARQ that enables reissuing a request after exception processing when the exception occurrence timing of the above instruction is in the middle of instruction execution Control device. 2. An instruction address holding unit IAD, which holds an instruction address of a macro instruction or a start address of an instruction string including the instruction, which can be read by microcode, and a macro instruction which can be read / written by microcode, or includes the instruction. A request type holding unit RQD that holds the type of request of the instruction sequence, a size holding unit ACD that holds the size of the macro instruction or the request of the instruction sequence that includes it that can be read / written by microcode, and read / write by microcode A possible request address holding unit S that holds the address of the above request
AD, an instruction sequence holding unit SEQD that holds an instruction sequence of a macro instruction or an instruction sequence including the macro instruction that is readable and writable by microcode, and a macro instruction that is readable and writable by the microcode or an instruction sequence that includes the scalar is a scalar. A single scalar execution holding unit MIED for holding execution or single execution, and a general register write instructing unit GRW indicating that there is a general register write by a macro instruction or an instruction sequence including the same that can be read / written by microcode
D, a macro instruction readable / writable by microcode, a GR number holding unit R1WAD for an operation instruction that holds a general register write number of an operation instruction in an instruction sequence including the macro instruction, and a macro readable / writable by microcode GR number holding unit R1WLD for load instruction that holds the general register write number of the load instruction in the instruction or the instruction sequence including it, and if the exception occurrence timing of the above instruction is the break of the instruction, the request is issued again after the exception processing 2. The processor control device according to claim 1, further comprising a request re-output unit SADQ that enables correction. 3. Among the instructions being executed by the scalar, after clearing the GR number holding unit R1WLD for the load instruction and the request type holding unit RQD, only the operation instruction can be completed by operating the request reissue unit SADQ. 3. The processor control device according to claim 2, which is capable of completing the load / store instruction only by clearing the operation instruction GR number holding unit R1WAD and operating the request reissue unit SADQ. 4. A request re-output unit SADQ and a request re-output unit S during restart processing for an exception in the middle of a macro instruction.
3. The processor control device according to claim 2, wherein the pending request and the write to the general register can be completed by continuously operating the ARQ. 5. For an exception in the middle of a macro instruction, the single scalar execution holding unit MIE0 is checked, and when it is "1", the exception occurs at the time of scalar execution, and when it is "0", the exception is raised. It is determined that the exception occurred at the time of single execution, and the single scalar execution holding unit MIED is checked for the exception at the break of the macro instruction. When this is "1", the exception occurs at the time of scalar execution, and "0". 3. The processor control device according to claim 2, wherein at that time, the exception is judged to have occurred at the time of single execution, and the restart processing from the exception processing can be changed. 6. A single scalar execution holding unit MIE0 is checked, and when it is, for example, "1", the instruction sequence holding unit SEQ0 is checked, and the instruction sequence of the scalar execution instruction string in which the exception has occurred is the instruction sequence holding. When the part SEQ0 is, for example, "1", it is in the order of operation instruction → load / store instruction, and when it is "0", it is in the order of load / store instruction → operation instruction, and the single scalar execution holding unit MIED is checked. This is, for example, "1"
When the instruction sequence holding unit SEQD is “1”, for example, the instruction sequence holding unit SEQD checks the instruction sequence holding unit SEQD, and the instruction sequence of the scalar execution instruction sequence in which the exception occurs is the order of operation instruction → load store instruction, This is "0"
3. The processor control device according to claim 2, wherein the order is such that the load / store instruction is followed by the operation instruction, and the restart processing from the exception processing can be changed by these pieces of information. 7. When an exception occurs in an operation instruction, the request for the load / store instruction that is being executed at the same time is suppressed so that the exception due to the request does not occur and the request can be re-injected. The processor control device according to claim 2. 8. When an exception occurs in an operation instruction, a request for a load / store instruction that is being executed at the same time is suppressed so that an exception due to the request does not occur. 3. The processor control apparatus according to claim 2, wherein it is possible to cancel the instruction execution completion of either or both of the instructions. 9. When an exception is detected during instruction execution, if single execution is performed, refetch is performed from the instruction next to the instruction that generated the exception based on the address held in the instruction address holding unit IA0, and scalar execution is performed. When a load / store instruction causes an exception and the scalar instruction sequence is in the order of load / store instruction, operation instruction, and branch instruction, only the load / store instruction is completed, refetch is performed from the operation instruction, and the load / store instruction is executed by the scalar execution. When an exception occurs in the scalar instruction sequence and the scalar instruction sequence is in the order of the operation instruction, the load store instruction, and the branch instruction, the operation instruction and the load store instruction are completed, and the refetch is performed from the branch instruction. Item 2. The processor control device according to item 2. 10. When an exception is detected at the break of an instruction and if it is a single execution, the next instruction, that is, the instruction address holding unit I.
When refetching is performed from the address held in A0, an exception occurs in the load / store instruction during scalar execution, and the scalar instruction string is in the order of load / store instruction, operation instruction, and branch instruction, only the load / store instruction is completed. If an exception occurs in the load / store instruction due to refetching from the operation instruction and scalar execution, and the scalar instruction sequence is in the order of operation instruction, load / store instruction, and branch instruction, the operation instruction and load / store instruction are completed, and the branch instruction 3. The processor control device according to claim 2, wherein the refetch is performed from the. 11. When an exception is detected at an instruction break, an exception occurs in an arithmetic instruction during scalar execution, and when the scalar instruction sequence is an arithmetic instruction, a load store instruction, and a branch instruction, only the arithmetic instruction is completed. If the exception occurs in the arithmetic instruction during scalar execution and the scalar instruction sequence is load / store instruction, arithmetic instruction, branch instruction in that order, set the execution mode to single mode and reload. The processor control device according to claim 2, wherein refetching is performed from a store instruction. 12. When a scalar execution causes an interrupt due to an addressing exception or an operation exception, the execution mode is set to single mode, refetching is performed from the next instruction, and the interrupted state is simplified again. 3. The method according to claim 2, wherein
A processor controller as described. 13. When a scalar type instruction causes an instruction-type exception, the load / store instruction and operation instruction are completed, the execution mode is set to single mode, refetching is performed from the subsequent instructions, and all issues are issued. The processor control device according to claim 2, wherein exception processing is performed after completion of possible instructions. 14. The exception occurs again in the single mode,
The processor control device according to claim 2, wherein when the processing is completed, the scalar mode is returned to at the time of the restart processing.