JPH086851A - Cache memory controller - Google Patents

Abstract

(57) [Summary] [Purpose] A dirty entry in a large capacity cache memory is searched at high speed. In a cache memory control device for retrieving update information of a cache memory 13 that holds a part of data in a main memory 12, the line area is provided for each line area of the cache memory 13, and the line area corresponds to the corresponding data of the main memory. When the updated data different from the above is held, the linear list configuration information storage area 13c for storing the line information indicating the information of the line area for which the data is updated immediately before and the linear list configuration information storage area 13c are stored. The route processing unit 14d that stores route information indicating the latest updated line area information, and the cache based on the route information of the route processing unit 14d and the line information of the linear list configuration information storage area 13c. The line area of the memory 13 is searched in a linear list, and the data of each corresponding line is written back to the main memory. The control circuit executes Interview process 14
a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control device which is applied to a computer system using a relatively large scale cache memory and retrieves update information of the cache memory.

[0002]

2. Description of the Related Art In an electronic computer system, at present, the processing capability of a processor is greatly improved, and a difference in data transfer rate between a main memory operating at a relatively low speed and a processor becomes a bottleneck in data processing. There is. Therefore, by interposing a cache memory that can operate at a relatively high speed between the processor and the main memory, and allowing the processor to access the cache memory, it is possible to fully demonstrate its processing capability. Become.

However, in a computer system equipped with a cache memory, since the write data from the processor is temporarily stored in the cache memory, there is a period in which the latest data is not reflected in the main memory. And
In order to minimize the loss of the latest data even when a processor or cache memory fails while the latest data is not reflected in this main memory, dirty entries (update items) in the cache memory Need to be erased as appropriate to match the contents of the data in the cache memory and the data in the main memory, and the function of searching the dirty entry in the cache memory is required.

FIG. 14 shows the configuration of the conventional cache memory.
As shown in, for example, each cache item set on a line-by-line basis has a one-to-one correspondence with dirty (update) of the item part
/ A tag area is stored in which clean (unupdated) information is stored, and all tag areas are sequentially scanned by software to search for dirty entries. In FIG.
The “line No.” indicates line information indicating the arrangement of each block in the cache memory, and the “cache entry” indicates information actually arranged on the line. Indicates whether the data is dirty or clean. Furthermore, the "tag area" is an area that stores a bit string required for cache memory operation depending on the computer system, and the dirty / clean bit in this area indicates whether the cache entry corresponding to the tag area is dirty. Is.

[0005]

According to the conventional method shown in FIG. 14, the dirty entry search process takes time because all the tag areas in the cache memory are sequentially scanned by software to search for the dirty entry. . This tendency is more remarkable as the capacity of the cache memory, that is, the wider the scanning area is. On the other hand, since the cache memory is becoming wider year by year, the time required for the search is expected to further increase.

The present invention has been made in view of the above situation, and an object of the present invention is to control a cache memory capable of retrieving a dirty entry at a higher speed even if the cache memory has a large capacity. To provide a device.

[0007]

That is, the present invention provides a cache memory control device for retrieving update information of a cache memory holding a part of data in a main memory, the cache memory control device being provided for each line area of the cache memory. When the line area holds updated data different from the corresponding data in the main memory, update storage means for storing line information indicating the information of the line area whose data was updated immediately before, and the update storage means. A route storage unit that stores route information indicating the latest updated line region information, and a line region of the cache memory is linearly based on the route information of the route storage unit and the line information of the update storage unit. A cache that executes a flash process that searches in a list and writes the data of each applicable line back to the main memory. It is obtained by so and a shoe controller.

[0008]

With the above structure, only the necessary line areas are searched in the form of a linear list, so that even a cache memory with a large capacity can be searched for dirty entries at a higher speed.

[0009]

【Example】

[First Embodiment] A first embodiment in which the present invention is applied to a control device for controlling the entire area of a cache memory will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration thereof. 11 is a CPU for executing calculations, 12 is a bus-connected main memory, and 13 is interposed between the CPU 11 and the bus to which the main memory 12 is connected. Is the cache memory that has been created.

The cache memory 13 has a data area 13a for holding a part of the data in the main memory 12 by writing by the CPU 11, a tag area 13b for storing a bit string required for the operation of the cache memory 13 and each cache. It has a linear list configuration information storage area 13c which is information added for each entry and which is an area for storing other dirty line information immediately before that.

A cache memory control circuit 14 is provided to control the tag area 13b and the linear list configuration information storage area 13c of the cache memory 13. The cache memory control circuit 14 includes a control circuit 14a for realizing a configuration of a linear list and a flash process using the linear list, a tag information buffer 14 used for writing / reading the tag area 13b, and the linear list configuration information. A list information buffer 14c used for writing / reading the storage area 13c and a route processing section 14d which is a work area for constructing a linear list and a flash processing operation.
Have.

Next, the specific operation of the first embodiment will be described. FIG. 2A exemplifies a specific configuration of the cache memory 13 that searches for a dirty entry using a linear list. In the figure, "Line number (N
o. ) ”Indicates the line of each cache entry, and“ cache entry ”indicates the data itself, and together form the data area 13a. In FIG. 2A, the data is stored in the cache and then updated. Whether or not it is shown as dirty (updated) / clean (not updated). Here, the number of times value in parentheses indicates the order when each data is updated. Also, the "tag area" depends on the computer system as described above, and the cache memory 13
The "linear list" is an area for storing a bit string necessary for operation, and is the information added for each cache entry, and is for the other line area that is dirty immediately before the dirty cache entry. Shows information.
Null in the figure indicates an initial value.

The "route" shown in FIG. 2 (B) exemplifies a specific configuration of the route processing unit 14d of the cache memory control circuit 14, which is specifically used as a work area for constructing a linear list. Is composed of a memory capable of storing arrangement information of one line.

FIG. 3 is a flowchart showing the contents of the processing for constructing the linear list, and FIG. 4 is a flowchart showing the contents of the processing for retrieving the dirty entry based on the linear list.

When the CPU 11 writes data to the data area 13a of the cache memory 13, the value of the route, which is the line information of the cache entry that was dirty last time, is stored in the linear list configuration information storage area corresponding to the current cache line. Save and update route with line number of current line. This series of operations is shown in FIG. That is, in FIG. 3, the relevant portion of the linear list configuration information storage area 13c of the dirty current line is updated and set with the contents of the route processing unit 14d (step A1), and then the contents of the route processing unit 14d are changed to dirty. The line number of the current line. The update setting is performed at step A2.

The operation of the above processing contents will be specifically confirmed with reference to FIG. Null information is stored as an initial value in the route processing unit 14d,
For example, the line N of the data area 13a of the cache memory 13
o. When 3 is first dirty, the contents of the route processing unit 14d indicate that the line number of the same cache entry. Is updated to “3”. Then, the null information, which is the first stored content of the route processing unit 14d, replaces the line number. No. 3 linear list configuration information storage area 13c.

Then, the line number of the data area 13a. When 2 becomes dirty, the current information "3" of the route processing unit 14d indicates the line number. It is stored in the second linear list configuration information storage area 13c. Then, the contents of the route processing unit 14d are the line number of the same cache entry. Is updated to "2".

As shown in FIG. 2, for example, when a total of 5 cache entries become dirty by repeating such operations, the cache memory 13 is flushed next.

In order to perform the flush processing of the cache memory 13, first, as shown in FIG. 4, the value of the route processing unit 14d is referred to (step B1) and it is judged whether or not the value is null (step). B2). If it is null, the flash process is terminated. If not, the process proceeds to the flash process of the line indicated by the route processing unit 14d (step B3), and the line is flashed (step B4).
), After updating the route processing unit 14d with the contents of the corresponding linear list configuration information storage area 13c (step B5),
The line in the linear list configuration information storage area 13c is updated with null information (step B6).

Regarding the above processing contents, the operation will be specifically confirmed in accordance with FIG. Cache memory 13
In order to retrieve the dirty entry for the flash processing of the data area 13a, the contents of the route processing section 14d are first referred to (step B1). When it is determined that the value of the route processing unit 14d is null (step B2), the flash process is terminated at that point. However, since the value initially shown by the route processing unit 14d is "6", the line N
o. Proceed to flash operation 6 (step B3).

Line No. The line No. 6 is flushed (step B4), and the line number of the cache entry to be flushed next. That is, after updating and setting the route processing unit 14d with the content "1" of the linear list configuration information storage area 13c (step B5), the line in the linear list configuration information storage area 13c is initialized with null (step B).
6).

Subsequently, the line No. The cache line of No. 1 is flushed, and the line number of the cache entry to be flushed next. That is, the route processing unit 14d is initialized with the content "5" of the linear list configuration information storage area 13c, and then the linear list configuration information storage area 13c is initialized by null.

By repeating the above-described flush processing operation from the route processing unit 14d until null returns, all the dirty entries in the data area 13a of the cache memory 13 can be flushed.

[Second Embodiment] A second embodiment in which the present invention is applied to a control device for controlling only dirty entries within a specified limited range in a cache memory will be described below with reference to the drawings. Explain.

FIG. 5 shows a circuit configuration thereof, which is basically the same as that shown in FIG. 1, so that the same portions are denoted by the same reference numerals and the description thereof will be omitted. Then
In the cache memory control circuit, in addition to the control circuit 14a, the tag information buffer 14b, the list information buffer 14c, and the route processing unit 14d, the current line pointer 14e indicating the line position during the flush process, and the line immediately before the flush process Backup pointer 14f indicating the dirty line position outside the flash range, end line pointer (indicated as "U line pointer" in the figure) 14g indicating the end line position of the cache memory area to be flushed, and the cache memory area to be flushed It has a start line pointer 14h (indicated as "L line pointer" in the figure) indicating the start line.

Next, the specific operation of the first embodiment will be described. FIG. 6A exemplifies a specific configuration of the cache memory 13 that searches for a dirty entry using a linear list. In the figure, "Line number (N
o. ) ”Indicates the line of each cache entry, and“ cache entry ”indicates the data itself, and together form the data area 13a. In FIG. 6A, the data is stored in the cache and then updated. Whether or not it is shown as dirty (updated) / clean (not updated). Here, the number of times value in parentheses indicates the order when each data is updated. The "tag area" 13b is an area for storing a bit string required for operating the cache memory 13 depending on the computer system as described above, and the "linear list" 13c is line information added for each cache entry. Yes, information about the line area that was dirty immediately before it is used to form a linear list of cache entries that are dirty is stored. Null in the figure indicates an initial value.

The "route" shown in FIG. 6 (B) exemplifies a specific configuration of the route processing unit 14d of the cache memory control circuit 14, which is specifically used as a work area for constructing a linear list. Is composed of a memory capable of storing arrangement information of one line.

When the CPU 11 writes data to the data area 13a of the cache memory 13, the value of the route, which is the line information of the cache entry that was dirty last time, is stored in the linear list configuration information storage area corresponding to the current cache line. Save and update route with line number of current line. This series of operations is shown in FIG.

That is, FIG. 7 shows the processing contents for constructing the above-mentioned linear list configuration information storage area 13c. First, the corresponding portion of the linear list configuration information storage area 13c of the dirty current line is processed by the route processing section. 14d is updated and set (step C1), and then the contents of the route processing section 14d are changed to the dirty line No. The update setting is performed at step C2.

The operation of the above processing contents will be specifically confirmed with reference to FIG. Null information is stored as an initial value in the route processing unit 14d,
For example, the line N of the data area 13a of the cache memory 13
o. When 3 is first dirty, the contents of the route processing unit 14d indicate that the line number of the same cache entry. Is updated to “3”. Then, the null information, which is the first stored content of the route processing unit 14d, replaces the line number. No. 3 linear list configuration information storage area 13c.

Then, the line number of the data area 13a. When 2 becomes dirty, the current information "3" of the route processing unit 14d indicates the line number. It is stored in the second linear list configuration information storage area 13c. Then, the contents of the route processing unit 14d are the line number of the same cache entry. Is updated to "2".

As shown in FIG. 6, by repeating such operations, for example, when a total of five cache entries become dirty, the flush process with the limited range of the cache memory 13 is performed next.

However, in order to construct the continuous linear list configuration information storage area 13c from the cache entry that became the last dirty after executing the range-limited flash processing, before executing this range-limited flush processing, The line information of the dirty cache entry must be saved in. Therefore, in the dirty entry search within the limited range, the start line pointer 14h that stores the start line position of the limited range, the end line pointer 14g that stores the end line position of the limited range, and the current line pointer that stores the line information during the flush process A backup pointer 14f for backing up 14e and line information is provided in the cache memory control circuit 14.

FIG. 8A shows a linear list configuration information storage area.
13 illustrates a specific configuration of the cache memory 13 that searches for dirty entries in a limited range according to 13c. Here, for example, the line No. is set to limit the range of the flash process. 1 and line No. Two
Only the flash shall be processed.

Further, the cache memory of FIG. 8 (A)
FIG. 8B shows a specific configuration of the stored contents of the current line pointer 14e and the backup pointer 14f corresponding to the contents of FIG.
An example is shown in (C).

The dirty entry search based on the linear list configuration information storage area 13c constructed as described above and the flush processing for the limited range of the cache memory 13 will be described below with reference to FIG.

At the beginning of the process, the current line pointer 14e based on the value of the route processing unit 14d is first set as an initialization.
Update (step D1) and backup pointer 14f
The null initialization (step D2) is performed, and all the subsequent flash processing operations are performed using the current line pointer 14e.

That is, the value of the current line pointer 14e is referred to (step D3) and it is judged whether or not the value is null (step D4). If it is null, the cache flush is ended, and otherwise. Current line pointer
Line information is read from the linear list configuration information storage area 13c of the line area of the cache memory 13 shown by 14e, and this is newly updated and set in the current line pointer 14e (step D5).

Next, this updated and set current line pointer
It is judged whether or not the line information of 14e is within the range specified by the start line pointer 14h and the end line pointer 14g (step D6). If it is out of the range, the line information of the current line pointer 14e is set to the backup pointer 14f. After the update is set (step D7), the cache memory indicated by the current line pointer 14e is displayed as in step D5.
The line information is read from the linear list configuration information storage area 13c of the 13 line areas, and the current line pointer is newly read.
14e is updated and set (step D8), and the processing from step D3 is repeated again.

If it is determined in step D6 that the line information of the current line pointer 14e is within the range specified by the start line pointer 14h and the end line pointer 14g, the line in the cache memory 13 is flushed. Then, after the current line pointer 14e is updated and set with the line information of the linear list configuration information storage area 13c of the flash-processed line (step D10), the linear list configuration information storage area 13c is updated with null. Set (step D11).

Thereafter, it is judged whether or not the value indicated by the backup pointer 14f is null (step D12), and if it is not null, the linear list configuration information storage area 13c of the relevant line of the cache memory 13 indicated by the content of the backup pointer 14f. Is updated with the value of the current line pointer 14e (step D14), and the process returns to step D3.

If the content of the backup pointer 14f is null in step D12, the last dirty line area of the cache memory is designated by the start line pointer 14h and the end line pointer 14g. Since it indicates that the line information has been included in the route information, the route processing unit 14d is updated with the value of the current line pointer 14e, and the last dirty line information is updated (step D
13) and returns to the processing from step D3.

Regarding the above processing contents, the operation will be specifically confirmed in accordance with FIG. Cache memory 13
In order to search for a dirty entry for the flash processing of the data area 13a, the line number of the line area of the cache memory where the search is started. “6” is route processing unit 14
Copy from d to current line pointer 14e (step D1
), The contents of the backup pointer 14f are initialized to null (step D2).

Next, referring to the contents of the route processing unit 14d, if the value is null, the flashing process is terminated, but first, since the value indicated by the current line pointer 14e is "6",
This is judged (step D4), and this line N
o. It is judged that the line area of No. 6 is out of the specified range (step D6), and the line No. of the current cache line.
"6" is saved in the backup pointer 14f (step D7), and the current line pointer 14e is updated with the line information "1" of the corresponding linear list (step D8).

Then, in order to retrieve the next dirty entry for the cache memory flush process, the contents of the current line pointer 14e are referred to (step D3), and since the value of the current line pointer 14e is "1", the cache is cached. Line No. of memory 13 Proceed to the operation of the 1 line area.

This is judged because the current line is within the specified range (step D6), and the line No. The flash processing of the line area of No. 1 is executed (step D9). After updating the current line pointer 14e with the content "5" of the corresponding linear list of 1 (step D10), and further updating the content of the linear list with null (step D11),
Since the current backup value is "6", it is determined that this is not null (step D12), and then the line number.
The linear list of the line area 6 is updated with "5" indicated by the current line pointer 14e.

By repeating such an operation from the linear list until a null is returned, within the designated range, in this case, the line number. 1 and line No. Now all dirty entries in 2 can be flushed.

[Third Embodiment] A third embodiment of the present invention will be described below with reference to the drawings. FIG. 10 shows the circuit configuration thereof. 21 is a CPU for executing an operation, 22 is a main memory connected to a bus, and 23 is a cache interposed between the CPU 21 and a bus connected to the main memory 22. It is a memory.

The cache memory 23 has a data area 23a for holding a part of the data in the main memory 22 by writing by the CPU 21 and a tag area 23b for storing a bit string required for the operation of the cache memory 23. Have.

A cache memory control circuit 24 is provided to control the cache memory 23. The cache memory control circuit 24 is a control circuit 24 that performs overall control for realizing flash processing.
a, an interrupt request generation circuit 24b that generates an interrupt request to the CPU 21, and line information indicating the line area when the line area in the cache memory 13 holds updated data different from the corresponding data in the main memory 22. A table area 24c to be held as a table, a table pointer 24d and a table area 24c for pointing the point position when writing / reading the table area 24c.
Has a limit pointer 24e for holding the limit position of the pointing point of the table pointer 24d according to the storage capacity of the.

Next, the specific operation of the third embodiment will be described. FIG. 11A illustrates the state of the cache memory 23 having dirty entries, and FIG. 11B illustrates the state of the table area 24c and the table pointer 24d of the cache memory control circuit corresponding to the cache memory 23. is there.

In FIG. 11A, "line number (N
o. ) ”Indicates the line position of each cache entry. Further, the “cache entry” indicates the data itself, and whether or not the data has been updated after being stored in the cache memory 23 in FIG. 11A is described as dirty (update) / clean (unupdated) in the figure. is there. here,
The count value in parentheses indicates the order in which each data was updated. The "tag area" 23b is an area for storing a bit string required for operating the cache memory 23, which depends on the computer system as described above.

On the other hand, the table area of FIG. 11 (B)
Reference numeral 24c is a storage area for storing the line information of the dirty entry, is composed of m table entries, and the table pointer 24d points the displacement within the table area 24c. Here table area 24c
The number m of table entries in the cache memory 23 is “m = n” when the number of dirty entries corresponding to the total number n of lines in the cache memory 23 is a target, and the number of dirty entries corresponding to a specific number of lines is a limit pointer 24e. It will be equal to the specified number.

FIG. 12 is a flowchart showing the processing contents for constructing the table area 24c, which is mainly executed by the operation control of the control circuit 24a. When the CPU 21 writes data in the cache memory 23, the table area 24 designated by the table pointer 24d
The line number that became dirty to the table entry of c.
Is stored (step E1) and after the table pointer 24d is incremented (step E2), it is determined whether or not the value of the table pointer 24d becomes the specific number of the table area 24c pointed to by the limit pointer 24e (step E3).

If the specified number of limit pointers 24e has not been reached, the processing for this dirty entry ends, but if the specified number of limit pointers 24e has been reached and the range for performing the flush process is exceeded. When the determination is made, the interrupt request generation circuit 24b generates an interrupt request signal to the CPU 21 so that the CPU 21 does not write any more data into the cache memory 23. A series of processing operations for this interrupt is shown in FIG.

FIG. 13 is a flow chart showing the contents of the flash processing of the cache memory 13 and other processing based on the table area 24c constructed by the processing of FIG. 12, which is mainly executed by the operation control of the control circuit 24a. Is.

The interrupt request generation circuit 24b generates an interrupt request signal to the CPU 21 (step F1), and the CPU
The control circuit 24a which prevents further writing from 21 to the cache memory 23 then decrements the table pointer 24d (step F2) and then the value of the table pointer 24d becomes "0"("Null" in the figure).
It is confirmed that the flash processing and other processing have not been completed yet (step F3).

Then, the control circuit 24a reads the line information from the table area 24c in accordance with the instruction point of the table pointer 24d, and flashes the line area of the cache memory 23 according to the line information (step F4).

After that, the table entry in the table area 24c is initialized according to the instruction point of the table pointer 24d to set "0" (Null), and the processing from step F1 is repeated again.

Then, in step F3, the table pointer
When the value of 24d becomes "0" (Null), all the processing of FIG. 13 is completed. The above-described operation will be confirmed in accordance with the contents of FIGS. 11 (A) and 11 (B).

First, "0" is stored in the table pointer 24d, and the line No. of the cache memory 23 is stored. When 3 is first dirty, the No. 3 of the table area 24c designated by the table pointer 24d. 0 table entry, dirty entry line number. The line information "3" is stored (step E1), and the table pointer 24d is incremented to "1" (step E2).

Subsequently, the line No. of the cache memory 23.
2 becomes dirty, the No. of the table area 24c designated by the table pointer 24d. No. 1 table entry has a dirty entry line number. The line information "2" is stored (step E1), and the table pointer 24d is incremented to "2" (step E2).

By repeating such an operation, the process shown in FIG.
As shown in FIG. 6, when the cache entry of the cache memory 23 at the total of 5 places becomes dirty, it is determined that the value “5” of the table pointer 24d becomes equal to the specific number “5” preset in the limit pointer 24e. Then, (step E3), the interrupt request generation circuit 24 prevents the CPU 21 from further writing to the cache memory 23.
An interrupt request signal is generated from b to the CPU 21 (step E4), and the cache processing of the cache memory 23 shown in FIG. 13 is executed.

That is, in FIG. 13, first, the CPU 21
To the cache memory 23 to issue the above-described write suppression interrupt request (step F1), and then decrement the table pointer 24d (step F2). If the value of the decremented table pointer 24d indicates "0" (Null) (step F3), the flush process is ended, but the value of the decremented table pointer 24d indicates "5", and the table area No. 24c. Entry No. 5 Since the line information corresponding to “6” indicates “6”, the line number of the cache memory 23 is. The line area 6 is subjected to flash processing (step F4), and then the table area 24c
Entry number. The line information "6" corresponding to 5 is initialized to "0" (Null) (step F5), and the process returns to step F1.

After continuously issuing an interrupt request (step F
1), the table pointer 24d is decremented to "4" (step F2), and the No. of the table area 24c is passed through step F3. No. 4 entry number. The line N of the cache memory 23 by the line information “1” corresponding to
o. 1 line area is flashed (step F4
), Followed by the entry No. of the table area 24c. The line information “1” corresponding to 4 is initialized to “0” (Nul
l) (step F5), and the process returns to step F1 again.

By repeating such an operation until the value of the table pointer 24d becomes "0" (Null),
The dirty entry existing in the cache memory 23 can be flashed at high speed.

In the above embodiment, the table pointer 24
Entry No. of d. The cache memory 23 is flushed when 4 reaches a specific number of limit pointers 24e, but this limit pointer 24e is not provided.
All entry numbers of the table area 24c. When a certain value "m" is reached, an interrupt request is issued to the CPU 21 and the processing of FIG. 13 may be performed.

[0069]

As described above in detail, according to the present invention, it is possible to provide a cache memory control device capable of retrieving a dirty entry at a high speed even in a large capacity cache memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a storage state of a cache memory and a route processing unit of FIG.

FIG. 3 is a flowchart for explaining the operation of the embodiment.

FIG. 4 is a flowchart for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing a circuit configuration according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a storage state of a cache memory and a route processing unit of FIG.

FIG. 7 is a flowchart for explaining the operation of the embodiment.

FIG. 8 is a diagram exemplifying a storage state of a cache memory, a current line pointer, and a backup pointer of FIG.

FIG. 9 is a flowchart for explaining the operation of the embodiment.

FIG. 10 is a block diagram showing a circuit configuration according to a third embodiment of the present invention.

11 is a diagram exemplifying storage states of a cache memory, a table area, and a table pointer of FIG.

FIG. 12 is a flowchart for explaining the operation of the embodiment.

FIG. 13 is a flowchart for explaining the operation of the embodiment.

FIG. 14 is a diagram illustrating a configuration of a conventional cache memory.

[Explanation of symbols]

11, 21 ... CPU, 12, 22 ... Main memory, 13, 23 ... Cache memory, 13a, 23a ... Data area, 13b, 23b ...
Tag area, 13c ... Linear list configuration information storage area, 14, 24
... Cache memory control circuit, 14a, 24a ... Control circuit,
14b ... tag information buffer, 14c ... list information buffer,
14d ... Route processing unit, 14e ... Current line pointer, 14f ...
Backup pointer, 14g ... End line pointer, 14
h ... start line pointer, 24b ... interrupt request generation circuit,
24c ... table area, 24d ... table pointer, 24e ...
Limit pointer.

Claims (5)

[Claims] 1. A cache memory control device for retrieving update information of a cache memory that holds a part of data in a main memory, wherein the line area is provided for each line area of the cache memory, and the line area corresponds to corresponding data in the main memory. When storing different updated data, update storage means for storing line information indicating information of the line area where the data was updated immediately before, and the latest updated line area stored in the update storage means. Route storage means for storing route information indicating the information of the above, and a line list of the cache memory is searched in a linear list based on the route information of the route storage means and the line information of the update storage means, and each corresponding line Cache control means for executing a flash process for writing back the data of the above to the main memory. A characteristic cache memory control device. 2. A start line point storage means for storing a point indicating a start line of a range of cache memory to be flushed, and an end line point storage means for storing a point indicating an end line of a range of cache memory to be flushed. 3. The cache control means further includes only the range of the cache memory indicated by the stored contents of the start line point storage means and the end line point storage means as the target of the flush processing. A cache memory control device as described. 3. The cache control means executes the flush process when the number of line areas holding updated data different from corresponding data in the main memory of the cache memory reaches a specific value. Claim 1
A cache memory control device as described. 4. A cache memory control device for retrieving update information of a cache memory which holds a part of data of a main memory, wherein updated line data of the cache memory is different from corresponding data of the main memory. Table storage means for storing line information indicating the information of the line area as a table when holding, point instruction means for pointing the latest storage position of the table storage means, and the table storage means according to the point instruction means A cache control means for reading the stored line information, searching the line area of the cache memory according to the line information, and executing a flash process for writing back the data to the main memory. Memory controller. 5. The cache memory further comprises limit point designating means for designating a point that can be stored in the table storage means, and the cache control means has a point designating point of the point designating means equal to a designating point of the limit point. The cache memory control device according to claim 4, wherein a flush process is executed at a point of time.