JPH0875829A - Pattern generator for semiconductor test equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] A pattern of a semiconductor test device that enables a user of a pattern generator to easily input the operation data, which is an operation condition, into the memory, and improves the efficiency of use of the memory. Aim to get a generator. [Arrangement] By forming an address table 32 in which the addresses of the operation data table 31 are tabulated in the instruction memory 3 and forming the operation data table 31 in the newly provided operation data memory 14, the operation data memory of the address table 32 is formed. The operation data 15 in the operation data table 31 can be selected by designating the address 11a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator for a semiconductor test apparatus, which enables a user of the pattern generator to easily input calculation data, which is a calculation condition, into a memory.

[0002]

2. Description of the Related Art What is a pattern generator of a semiconductor test device?
It is one functional module incorporated in a semiconductor test device that checks whether the LSI satisfies product specifications (electrical characteristics, timing, characteristics, functions). When performing a functional test of a memory IC, the memory IC is used. On the other hand, it outputs a signal for controlling what kind of information is stored at which address and which address is read out.

FIG. 6 is a block diagram showing a pattern generator of a conventional semiconductor test apparatus. In FIG. 6, 1 designates the address of a test pattern bit to be executed next for each test cycle (writing or reading cycle). The program counter 3 is an instruction memory (high-speed static memory) that stores information for controlling the operation of the address pattern and the operation condition of the data pattern (for example, exclusive OR of two different data patterns). In the RAM or the like), the program counter 1 decodes the control information in the instruction memory 3 and determines the address of the test pattern bit to be executed next, that is, the instruction address 2.

Reference numeral 5 is an address adder circuit for adding the address addition data 4 to the address value of the immediately preceding cycle, 6 is main address data which is pattern data of an address signal applied to the semiconductor memory element, and 7 is test processing. Is a comparison address data indicating the final address value of 8 and 8 is a comparison address register circuit for holding the comparison address data 7.
An address comparison circuit 9 compares the main address data 6 with the comparison address data 7 and transmits an address match signal 10 to the program counter 1 when the two match.
Is a flip-flop circuit used for signal synchronization and delay of the main address data 6 and operation data 15; 15 is operation data representing a combination condition (operation condition) of the input data signal 17; 16 is main address data 6, a data operation circuit for generating an input data signal 17 based on 6 and operation data 15, and 20 is a reference clock signal 21 which is a trigger signal of the flip-flop circuit 13.
Is a reference clock generation unit for generating.

Next, the operation will be described. This pattern generator generates an address signal to be applied to a semiconductor memory element (not shown) in the address data generator 18,
The input data generator 19 generates a data signal to be applied to the semiconductor memory element based on the address signal. First, the instruction memory 3 of the address data generation unit 18 stores the address addition data 4 of the test pattern bit designated by the program counter 1.
Is transmitted to the address adder circuit 5. Next, the address adder circuit 5 adds the address addition data 4 and the address value of the immediately preceding cycle to generate main address data 6 which is the address value for the current cycle. The address addition is performed until the main address data 6 reaches the final address value.

Then, the address comparison circuit 9 compares the main address data 6 with the comparison address data 7 indicating the final address value, and if they match, sends an address match signal 10 to the program counter 1. Then, the program counter 1 determines the address of the test pattern bit to be executed next based on the address match signal 10 and the control information from the instruction memory 3, and the above-described operation is repeated. Further, the input data signal 17 is based on the main address data 6 generated in the address data generator 18 for each cycle and the operation data 15 output from the instruction memory 3 in the data operation circuit 1.
6 is generated.

FIG. 7 is a block diagram showing a method of designating the operation data 15 in the instruction memory 3 of the pattern generator of the conventional semiconductor test apparatus. In the figure, 23 is a test pattern bit address transmitted by the program counter 1 to the instruction memory 3,
Reference numeral 31 is a calculation data table provided in the instruction memory 3. As an example, this calculation data 1
There are about 10 kinds of 5 in actual use, and calculation data 1
It consists of 16 bits regardless of the type of 5,
These calculation data 15 are manually input by the user of the pattern generator. Further, these operation data 15 are arranged in the operation data table 31, and the test pattern bit addresses (0 to n) 23 are attached to each of them. Therefore, the CPU (not shown) retrieves the operation data 15 of the test pattern bit address 23 indicated by the instruction address 2 from the instruction memory 3,
It is transmitted to the data operation circuit 16 and the input data signal 17 is generated. The series of operations is always synchronized with the reference clock signal 21.

In such a conventional pattern generator of the semiconductor test apparatus, since the operation data 15 is 16 bits regardless of the type of operation condition, the user of the pattern generator operates all the operation data 15. There was a problem that it was difficult to input manually by contrasting with the types of conditions.

[0009]

Since the pattern generator of the conventional semiconductor test apparatus is constructed as described above,
There is a problem that it is difficult for the user of the pattern generator to manually input all the calculation data 15 while comparing them with the types of calculation conditions.

The present invention has been made in order to solve the above-mentioned problems, and is a semiconductor capable of facilitating the input of operation data, which is an operation condition, to a memory by a user of the pattern generator. The purpose is to obtain a pattern generator for the test equipment.

[0011]

In a pattern generator of a semiconductor test apparatus according to the present invention, a first storage section having an address table in which addresses of operation data are tabulated is provided in the address data generation section, and the operation data is stored in the first storage section. The second storage unit included therein is provided in the input data generation unit.

[0012]

The pattern generator of the semiconductor test apparatus according to the present invention is provided in the address data generation section, and is provided in the first storage section having an address table in which the addresses of the operation data are tabulated, and the input data generation section, and the operation is performed. By providing the second storage section having the data, it is possible for the user of the pattern generator to easily input the operation data, which is the operation condition, into the memory, and to improve the use efficiency of the memory. Will be able to.

[0013]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a pattern generator of a semiconductor test apparatus of the present invention, and the same reference numerals as those of the conventional one indicate the same or corresponding portions, and therefore the description thereof will be omitted. In the figure, 11a and 11b are calculation memory address data of a calculation data table 31 stored in a calculation data memory 14 described later, and 12a and 12b are calculation data control signals for controlling change of the calculation memory address data 11a and 11b. , 14 are calculation data tables 31
Is a calculation data memory storing therein, for example, a dynamic RAM as a low speed memory is used. Reference numeral 35 is an AND circuit.

Next, the connection state will be described. First, the operational memory address data 11a is input to the D terminal of the flip-flop circuit 13b, and the address match signal 1 is input to the T terminal.
0, operation data control signal 12a, reference clock signal 21
The AND signal of b (the output signal of the AND circuit 35) is input, and the operation memory address data 11b output from the Q terminal is input to the operation data memory 14.
The operation data 15b output from the operation data memory 14 is input to the D terminal of the flip-flop circuit 13b. Since the time delay of the operation data 15b with respect to the main address data 6c, which occurs due to the memory access time of the operation data memory 14, can be removed by the flip-flop circuits 13c and 13d triggered by the reference clock 21c, the operation data memory 14 is It is not necessary to use a high speed memory such as the instruction memory 3.

Next, a method of selecting the operation data 15 in the operation data memory 14 will be described. In the above conventional example, the operation data 1 representing the operation condition of the input data signal 17
Although the operation data table 31 of No. 5 is formed in the instruction memory 3, in the present embodiment, an address table in which the addresses of the operation data table 31 are tabulated is formed in the instruction memory 3 and an operation data table 32 is newly provided. It is formed in the calculation data memory.

FIG. 2 is a block diagram showing a method of selecting the operation data 15 in the operation data memory 14. In the figure, reference numeral 32 is an address table formed in the instruction memory 3 and is a table of addresses of the arithmetic data table 31 formed in the arithmetic data memory 14. The address table 32 stores the operation data memory address 11a of the operation data table 31 displayed in 4 bits for each test pattern bit address 23. Therefore, if the test pattern bit address 23 is specified by the instruction address 2 of the program counter 1, the operation data memory address 11a of the address table 32 can be specified, and as a result, the operation data 15 in the operation data table 31 can be selected. .

Next, the operation of the input data generator 19 will be described with reference to FIG.
This will be described with reference to the timing chart of. FIG. 3 is a timing chart showing the operation of the input data generator 19. First, the instruction address 2 is output from the program counter 1 to the instruction memory 3 in synchronization with the reference clock signal 21a, and after the memory access time Ta, the address addition data 4, the comparison address data 7a, the operation data memory address 11a, and the operation data control signal. 12a outputs. Next, after the address calculation processing time, the main address data 6b continues to be added by a predetermined numerical value until it reaches the comparison address data 7b.
Main address data 6 in synchronization with the trigger signal 21b of
It is input to the flip-flop 13c as c, and is output to the data arithmetic circuit 16 as main address data 6d in synchronization with the trigger signal 21c in the flip-flop 13c.

The arithmetic data memory address 11a is input to the arithmetic data memory 14 as the arithmetic data memory address 11b in synchronization with the trigger signal 21b of the flip-flop 13b. The calculation data 15c is output to the data calculation circuit 16 in synchronization with the trigger signal 21c of 13d.

Therefore, since the main address data 6d and the operation data 15c are output to the data operation circuit 16 in synchronization with the trigger signal 21c of the flip-flop 13d, the data operation circuit 16 outputs the main signal until the match signal 10 is output. The address data 6d is converted into the predetermined calculation data 1
Continue computing at 5c. Then, when the coincidence signal 10 is output, the main address data 6a and the operation data memory address 11a are changed, and the next test pattern is executed.

Next, an example of the test pattern program will be described. FIG. 4 is a test pattern program showing an example for operating the circuit shown in FIG. In the figure, 22 is an initial data set instruction for setting initial data for the data operation conditions of the main address data 6, the comparison address data 7 and the input data signal 17.
Reference numeral 23 is a test pattern bit address, an address transmitted by the program counter 1 to the instruction memory 3, and 24 is an instruction instruction which is a group of control instructions stored in the instruction memory 3.

Reference numeral 25 is an address comparison instruction for instructing to branch to the address indicated by the branch destination bit address 26 until the main address data 6 and the comparison address data 7 match.
Reference numeral 7 is a main address operation instruction which is an instruction for controlling the operation of the address addition circuit 5 for generating the main address data 6, and the addition value described in the above instruction is a value indicating the content of the address addition data 4. Reference numeral 28 is an instruction for controlling the arithmetic processing of the comparison address register circuit 8. 29
Indicates the value of the operation data memory address 11a in the data operation selection instruction for selecting the operation condition of the input data signal 17. Reference numeral 30 is a test pattern stop instruction for stopping the operation of the test pattern.

Next, the operation will be described. A flowchart of the operation of the pattern generator of the semiconductor test apparatus of the present invention will be described with reference to the test pattern program of FIG. FIG. 5 is a flow chart showing the operation of the pattern generator of the semiconductor test apparatus of the present invention. In the figure, the processing between the program counter 1 and the instruction memory 3, the address addition, and the comparison processing between the main address data 6a and the comparison address data 7b are the same as the conventional ones, and thus the description thereof is omitted.

First, before the test pattern is executed, the main address data 6a (M = 0), the comparison address data 7a,
7b (C = 255), the initial data of the operation memory address data 11a, 11B (D = 0), which is the data operation condition, is set based on the instruction address 2 from the program counter 1 (step ST10). When the test pattern bit address 23 is 0, the test pattern processing is executed (step ST11). Next, the address comparison circuit 9 compares the main address data 6a with the comparison address data 7b (step ST12). That is, when the test pattern bit address 23 is 0, it is judged whether the test pattern processing is ended, and the processing is ended. If not (if they do not match), 1 is added to the main address data 6a (step ST13), and when the test pattern bit address 23 is 0, the test pattern processing is completed (main address data 6a becomes 255). Until step ST12 and step ST13 are repeatedly executed. Therefore, in the data operation circuit 16, the operation data (D = 1) until the main address data 6a becomes 255.
And the input data signal 17 is created.

If YES in step ST12, it means that the test pattern processing is completed when the test pattern bit address 23 is 0. Therefore, the main address data 6a
After adding 1 to the comparison address data 7b, C = 5
11, calculation memory address data 11a, 11B D =
It is changed to 1 (step ST14), and when the test pattern bit address 23 is 1, the test pattern processing is executed.
Therefore, the data operation circuit 16 operates based on the operation data (D = 1) until the main address data 6a becomes 511 (steps ST15 and ST16), and creates the input data signal 17.

If YES in step ST15, it means that the test pattern processing is completed when the test pattern bit address 23 is 1, so that the main address data 6a is obtained.
After adding 1 to the comparison address data 7b, C = 1
023, the operation memory address data 11a, 11B is D
= 2 (step ST17), and when the test pattern bit address 23 is 1, the test pattern processing is executed. Therefore, in the data arithmetic circuit 16, the arithmetic data (D =
The calculation is performed based on 2) and the input data signal 17 is created. When the test pattern bit address 23 is 2, the test pattern stop instruction 30 is set in the instruction instruction 24, so the operation of the test pattern is stopped at this point (step ST18).

As described above, according to the present invention, the user of the pattern generator only has to manually input the 4-bit operation data memory address data 11a of the operation data 15 into the instruction memory 3 and therefore the conventional operation. The operation data 15a can be input more easily than inputting 16 bits of the data 15. Further, since the data stored in the instruction memory 3 may be the 4-bit operation data memory address data 11a, it is possible to improve the use efficiency of the instruction memory 3 without causing a wasteful area in the high-speed and expensive instruction memory 3. You can

[0027]

As described above, according to the present invention, the address data generation section is provided with the first storage section having the address table in which the addresses of the operation data are tabulated.
Since the second storage section having the calculation data is provided in the input data generation section, the user of the pattern generator can easily input the calculation data, which is the calculation condition, into the memory. There is.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a pattern generator of a semiconductor test apparatus of the present invention.

[FIG. 2] Operation data 1 in operation data memory 14
It is a block diagram which showed the selection method of 5.

FIG. 3 is a timing chart showing the operation of the input data generation unit 19.

FIG. 4 is an explanatory diagram showing an example of a test pattern program for operating the circuit shown in FIG.

FIG. 5 is a flowchart showing the operation of the pattern generator of the semiconductor test apparatus of the present invention.

FIG. 6 is a configuration diagram showing a pattern generator of a conventional semiconductor test apparatus.

FIG. 7 is a configuration diagram showing a method for designating operation data 15 in an instruction memory 3 of a pattern generator of a conventional semiconductor test apparatus.

[Explanation of symbols]

15, 15b, 15c Operation data, 18 Address data generation unit, 19 Input data generation unit.

Claims (1)

[Claims] 1. An address data generator which outputs and outputs an address value based on a procedure of a test pattern and outputs operation data which is an operation condition of the test pattern, and is sequentially output from the address data generator. In the pattern generator of the semiconductor testing device, which is provided with an input value generation unit for inputting an address value and calculating the data stored in the address value based on the calculation data, the addresses of the calculation data are tabulated. A pattern generator for a semiconductor test apparatus, comprising: a first storage section having an address table in the address data generation section; and a second storage section having the operation data in the input data generation section.