JPH087745A - Electron-emitting device substrate, manufacturing method thereof, and image forming apparatus incorporating the same - Google Patents

Electron-emitting device substrate, manufacturing method thereof, and image forming apparatus incorporating the same

Info

Publication number
JPH087745A
JPH087745A JP13271594A JP13271594A JPH087745A JP H087745 A JPH087745 A JP H087745A JP 13271594 A JP13271594 A JP 13271594A JP 13271594 A JP13271594 A JP 13271594A JP H087745 A JPH087745 A JP H087745A
Authority
JP
Japan
Prior art keywords
electron
wiring
emitting device
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13271594A
Other languages
Japanese (ja)
Other versions
JP3313888B2 (en
Inventor
Hideji Kawasaki
秀司 川崎
Masato Niibe
正人 新部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP13271594A priority Critical patent/JP3313888B2/en
Publication of JPH087745A publication Critical patent/JPH087745A/en
Application granted granted Critical
Publication of JP3313888B2 publication Critical patent/JP3313888B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00Electrodes common to discharge tubes
    • H01J2201/30Cold cathodes
    • H01J2201/316Cold cathodes having an electric field parallel to the surface thereof, e.g. thin film cathodes
    • H01J2201/3165Surface conduction emission type cathodes

Landscapes

  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Electrodes For Cathode-Ray Tubes (AREA)

Abstract

PURPOSE:To provide an electron emitting element substrate having a high step coverage by suppressing the level difference of wiring in the line direction and column direction. CONSTITUTION:Column wirings 502 and filler wirings 502a are provided on a base board 501, and insulative material 503 is applied in the parts where the line wiring 7 and column wiringg are scheduled to make intersection. Then line wiring 504 are provided, and finally a thin film 506 including element electrode 505 and electron emission part is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、表面伝導型電子放出素
子基板、その製造方法、及び同基板を組込んだ平面型画
像形成装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface conduction electron-emitting device substrate, a method for manufacturing the same, and a planar image forming apparatus incorporating the same substrate.

【0002】[0002]

【従来の技術】従来、表示装置等に利用される電子放出
素子として熱電子源と冷陰極電子源の二種類が知られて
いる。冷陰極電子線には電界放出型(以下FEと略
す)、金属/絶縁層/金属型(以下MIMと略す)や表
面伝導型電子放出素子(以下SCEと略す)等がある。
2. Description of the Related Art Conventionally, two types of electron emitters, a thermoelectron source and a cold cathode electron source, are known for use in display devices and the like. The cold cathode electron beam includes field emission type (hereinafter abbreviated as FE), metal / insulating layer / metal type (hereinafter abbreviated as MIM), surface conduction electron emission element (hereinafter abbreviated as SCE), and the like.

【0003】FE型の例としては、W.P.Dyke&
W.W.Dolan、“Fieldemissio
n”、Advance in Electron Ph
ysics、8、89(1956)等が知られている。
As an example of the FE type, W. P. Dyke &
W. W. Dolan, "Fielddemissio
n ”, Advance in Electron Ph
ysics, 8, 89 (1956) and the like are known.

【0004】MIM型の例としては、C.A.Mea
d、“The tunnel−emission am
plifier、J.Appl.Phys.32、64
6(1961)やC.A.Spndt、“Physic
al propertiesof thin−film
field emission cathodesw
ith molybdenum cones”、J.A
ppl.Phys.、47、5248、(1976)等
が知られている。
An example of the MIM type is C.I. A. Mea
d, "The tunnel-emission am
plier, J. et al. Appl. Phys. 32, 64
6 (1961) and C.I. A. Spndt, "Physic
al properties of thin-film
field emission cathode sw
it mollybdenum cones ", JA
ppl. Phys. , 47, 5248, (1976) and the like are known.

【0005】SCE型の例としては、M.I.Elin
son、Radio Eng.Electron Ph
y.、10、(1965)等がある。
As an example of the SCE type, M. I. Elin
son, Radio Eng. Electron Ph
y. 10, (1965) and so on.

【0006】SCEは、基板上に形成された小面積の薄
膜の膜面に平行に電流を流すことにより、電子放出が生
ずる現象を利用するものである。
The SCE utilizes a phenomenon in which electron emission occurs when a current is passed in parallel with the film surface of a thin film having a small area formed on a substrate.

【0007】この表面伝導型電子放出素子としては、前
記エリンソン等によるSnO2 薄膜を用いたもの、Au
薄膜によるもの〔G.Dittmer:“Thin S
olid Films”、9、317(1972)〕、
In2 3 /SnO2 薄膜によるもの〔M.Hartw
ell and C.G.Fonstad:“IEEE
Trans.ED Conf.”、519(197
5)〕、カーボン薄膜によるもの〔荒木久 他:真空、
第26巻、第1号、22(1983)〕等が報告されて
いる。
As the surface conduction electron-emitting device, one using the SnO 2 thin film by Erinson et al.
Thin film [G. Dittmer: "Thin S
old Films ", 9, 317 (1972)],
In 2 O 3 / SnO 2 thin film [M. Hartw
ell and C. G. Fonstad: “IEEE
Trans. ED Conf. "519 (197
5)], by carbon thin film [Hiraki Araki et al .: Vacuum,
Vol. 26, No. 1, 22 (1983)] and the like are reported.

【0008】これらの表面伝導型電子放出素子の典型的
な素子構成として、前述のM.ハートウエルの素子構成
を図7に示す。
As a typical device configuration of these surface conduction electron-emitting devices, the above-mentioned M. The Hartwell device configuration is shown in FIG.

【0009】同図において701は絶縁性基板である。
704は電子放出部を含む薄膜である。スパッタで形成
されたH型形状金属酸化物薄膜等からなる電子放出部形
成用薄膜を、後述のフォーミングと呼ばれる通電処理す
ることにより電子放出部703が形成されている。ま
た、図中の素子の長さL1はおよそ0.5mmから1m
m、素子の幅W2は約0.1mmである。従来、これら
の表面伝導型放出素子においては、電子放出を行う前に
電子放出部形成用薄膜を予めフォーミングと呼ばれる通
電処理によって電子放出部703を形成するのが一般的
であった。
In the figure, reference numeral 701 is an insulating substrate.
704 is a thin film including an electron emitting portion. An electron emitting portion 703 is formed by subjecting a thin film for forming an electron emitting portion formed of an H-shaped metal oxide thin film or the like formed by sputtering to an energization process called forming described later. The length L1 of the element in the figure is about 0.5 mm to 1 m.
m, the width W2 of the element is about 0.1 mm. Conventionally, in these surface conduction electron-emitting devices, it is general that the electron-emitting portion 703 is formed in advance by performing an energization process called forming on the electron-emitting portion forming thin film before the electron emission.

【0010】即ち、フォーミングとは前記電子放出部形
成用薄膜の両端に電圧を印加通電し、電子放出部形成用
薄膜を局所的に破壊、変形もしくは変質せしめ、電気的
に高抵抗な状態にした電子放出部703を形成すること
である。
That is, the forming means that a voltage is applied to both ends of the electron-emitting-portion forming thin film to locally energize the electron-emitting-portion forming thin film so that the electron-emitting-portion forming thin film is brought into a high resistance state. That is, the electron emission portion 703 is formed.

【0011】尚、電子放出部703は電子放出部形成用
薄膜の一部に亀裂が発生しその亀裂付近から電子放出が
行なわれる場合もある。
In some cases, the electron emitting portion 703 has a crack in a part of the thin film for forming the electron emitting portion, and the electron is emitted from the vicinity of the crack.

【0012】以下フォーミングにより発生した電子放出
部703を含む電子放出部形成用薄膜を電子放出部を含
む薄膜704と呼ぶ。前記フォーミング処理をした表面
伝導型電子放出素子は上述電子放出部を含む薄膜704
に電圧を印加し、素子表面に電流を流すことにより、上
述電子放出部703より電子を放出せしめるものであ
る。
Hereinafter, a thin film for forming an electron emitting portion including the electron emitting portion 703 generated by forming will be referred to as a thin film 704 including an electron emitting portion. The surface conduction electron-emitting device that has undergone the forming process is a thin film 704 including the electron-emitting portion.
Electrons are emitted from the electron emitting portion 703 by applying a voltage to the device and passing a current through the device surface.

【0013】図8は本出願人らにより提案された表面伝
導型電子放出素子の構成を示す。(特開平2−5682
2)同図において801は絶縁性基板、805と806
は素子電極、804は電子放出部を含む薄膜、803は
電子放出部である。電子放出部を含む薄膜804のうち
電子放出部803としては粒径が数十オングストローム
の導電性微粒子からなり、これ以外の電子放出部を含む
薄膜804は微粒子膜からなる。なおここで述べる微粒
子膜とは、複数の微粒子が集合した膜であり、その微細
構造として、微粒子が個々に分散配置した状態のみら
ず、微粒子が互いに隣接、あるいは重なり合った状態
(島状も含む)の膜をさす。またこれとは別に電子放出
部を含む薄膜804は、導電性微粒子が分散されたカー
ボン薄膜等の場合がある。
FIG. 8 shows the structure of a surface conduction electron-emitting device proposed by the present applicants. (JP-A-2-5682
2) In the figure, 801 is an insulating substrate, and 805 and 806.
Is an element electrode, 804 is a thin film including an electron emitting portion, and 803 is an electron emitting portion. Of the thin film 804 including the electron emitting portion, the electron emitting portion 803 is made of conductive fine particles having a particle diameter of several tens of angstroms, and the other thin film 804 including the electron emitting portion is made of a fine particle film. The fine particle film described here is a film in which a plurality of fine particles are aggregated, and its fine structure is not limited to a state in which the fine particles are individually dispersed and arranged, but a state in which the fine particles are adjacent to each other or overlap each other (including an island shape). ) Membrane. In addition to this, the thin film 804 including the electron emitting portion may be a carbon thin film in which conductive fine particles are dispersed.

【0014】電子放出部を含む薄膜804の材料の具体
例を挙げるならばPt、Pd、Ru、Ag、Au、T
i、In、Cr、Fe、Zn、Sn、Ta、W、Pb等
の金属、PdO、SnO2 、In2 3 、PbO、Sb
2 3 等の酸化物、HfB2 、ZrB2 、LaB6 、C
eB6 、YB4 、GdB4 等の硼化物、TiC、Zr
C、HfC、TaC、SiC、WC等の炭化物、Ti
N、ZrN、HfN等の窒化物、Si、Ge等の半導
体、カーボン、AgMg、NiCu等がある。
Specific examples of the material of the thin film 804 including the electron emitting portion include Pt, Pd, Ru, Ag, Au and T.
i, In, Cr, Fe, Zn, Sn, Ta, W, Pb and other metals, PdO, SnO 2 , In 2 O 3 , PbO, Sb
2 O 3 and other oxides, HfB 2 , ZrB 2 , LaB 6 , C
Borides of eB 6 , YB 4 , GdB 4, etc., TiC, Zr
Carbides such as C, HfC, TaC, SiC, WC, Ti
There are nitrides such as N, ZrN and HfN, semiconductors such as Si and Ge, carbon, AgMg and NiCu.

【0015】電子放出部を含む薄膜804は真空蒸着
法、スパッタ法、化学的気相堆積法、分散塗布法、デイ
ッピング法、スピナー法等によって形成される。
The thin film 804 including the electron emitting portion is formed by a vacuum vapor deposition method, a sputtering method, a chemical vapor deposition method, a dispersion coating method, a dipping method, a spinner method or the like.

【0016】また、本出願人らは、前記表面伝導型電子
放出素子を用いた電子源や画像形成装置も提案した(U
SP5066883)。図9は前記表面伝導型電子放出
素子を配置した画像形成装置の斜視図を示す。基板90
1上に設けた複数の電子放出素子はそれぞれ2本の配
線、例えばDr 2とDl 2に並列接続されている。
電子放出素子904を作成した基板の上方には電子通過
孔905を有する変調電極906が電子放出素子の配線
903と直交して配置してある。
The present applicants also proposed an electron source and an image forming apparatus using the surface conduction electron-emitting device (U).
SP5068663). FIG. 9 is a perspective view of an image forming apparatus in which the surface conduction electron-emitting device is arranged. Board 90
Each of the plurality of electron-emitting devices provided on 1 is connected in parallel to two wirings, for example, Dr 2 and Dl 2.
A modulation electrode 906 having an electron passage hole 905 is arranged above the substrate on which the electron-emitting device 904 is formed so as to be orthogonal to the wiring 903 of the electron-emitting device.

【0017】また、画像形成装置の断面図を図10に示
す。ここで、901は基板、1002は素子電極、10
13は配線、1005は絶縁膜、906は変調電極、9
05は電子通過孔、1003は電子放出部を含む薄膜を
示す。
FIG. 10 is a sectional view of the image forming apparatus. Here, 901 is a substrate, 1002 is a device electrode, 10
13 is a wiring, 1005 is an insulating film, 906 is a modulation electrode, 9
Reference numeral 05 represents an electron passage hole, and 1003 represents a thin film including an electron emission portion.

【0018】次に表面伝導型電子放出素子基板の製造工
程の概略を図11を用いて以下に記す。
Next, an outline of the manufacturing process of the surface conduction electron-emitting device substrate will be described below with reference to FIG.

【0019】工程−a 基板901上にホトリソグラフ
ィー技術によりレジストパターン1117を形成し、素
子電極1118を形成する。素子電極材料としては、導
電性を有するものであれば使用できる。
Step-a A resist pattern 1117 is formed on the substrate 901 by a photolithography technique, and a device electrode 1118 is formed. As the element electrode material, any material having conductivity can be used.

【0020】工程−b リフトオフによって不要部分の
素子電極材料を除去する。
Step-b The unnecessary portion of the device electrode material is removed by lift-off.

【0021】工程−c 電極1118上にマスクとなる
層1119を積層・パターニングし、その上に電子放出
部形成用薄膜1104を形成する。
Step-c A layer 1119 serving as a mask is laminated and patterned on the electrode 1118, and an electron emission portion forming thin film 1104 is formed thereon.

【0022】工程−d 電子放出部形成用薄膜1104
をリフトオフによって不要の部分を除去することにより
電子放出部を含む薄膜1003を形成する。
Step-d Electron emitting portion forming thin film 1104
A thin film 1003 including an electron emitting portion is formed by removing unnecessary portions by lift-off.

【0023】工程−e 配線903を真空蒸着技術、ホ
トリソグラフィー技術により形成する。配線材には通常
電極材として用いられるものであればよい。
Step-e The wiring 903 is formed by a vacuum evaporation technique and a photolithography technique. Any wiring material may be used as long as it is usually used as an electrode material.

【0024】工程−f 変調電極を支持するための絶縁
膜1105を形成し、変調電極906を真空蒸着技術に
より形成する。
Step-f The insulating film 1105 for supporting the modulation electrode is formed, and the modulation electrode 906 is formed by the vacuum evaporation technique.

【0025】工程−g 絶縁層1105、変調電極90
6をホトリソグラフィー技術、エッチング技術により、
不要部分を取り去り、電子放出部を含む薄膜1003を
露出させる。
Step-g Insulating layer 1105, modulation electrode 90
6 by photolithography technology and etching technology
The unnecessary portion is removed to expose the thin film 1003 including the electron emitting portion.

【0026】[0026]

【発明が解決しようとする課題】しかしながら、本出願
人が、提案した表面伝導型電子放出素子を複数設置した
電子源及び該電子源と対向した位置に蛍光体を配置した
該表示装置等の画像形成装置(図9)においても、多数
素子を並列に配列した素子の配線(行方向配線)と直交
する方向(列方向配線)にグリッドを設ける事が、電子
を放出する素子を選択するためには、必須であり、簡易
な構成でかつ容易に、電子を放出する素子を選択し、そ
の電子放出量を制御し得る電子源ではなかった。また、
該電子源と対向した位置に配置された蛍光体を、選択的
に制御された明るさで発光せしめるには、グリッドが必
須であり、簡易な構成でかつ容易に、電子を放出する素
子を選択し、その電子放出量を制御し、蛍光体の輝度を
制御でき得る表示装置等の画像形成装置ではなかった。
However, an image of an electron source provided with a plurality of surface conduction electron-emitting devices proposed by the present applicant and an image of the display device or the like in which a phosphor is arranged at a position facing the electron source. Also in the forming apparatus (FIG. 9), the grid is provided in the direction (column-direction wiring) orthogonal to the wiring (row-direction wiring) of the elements in which a large number of elements are arranged in parallel in order to select the element that emits electrons. Is an essential electron source, and is not an electron source that can easily select an element that emits electrons and control the electron emission amount with a simple configuration. Also,
A grid is indispensable in order to make the phosphor arranged at a position facing the electron source emit light with selectively controlled brightness, and an element that emits electrons can be easily selected with a simple structure. However, it is not an image forming apparatus such as a display device that can control the electron emission amount and the brightness of the phosphor.

【0027】[0027]

【課題を解決するための手段】上記問題を解決するため
の本発明は、m本の行方向配線およびn本の列方向配線
(但し、m,nは自然数で、同一でも異なっていても良
い)と、素子電極および電子放出部を含む薄膜を有する
と共に該行方向配線及び列方向配線と接続された表面伝
導型電子放出素子とを基板上に形成してなる表面伝導型
電子放出素子基板において、該行方向配線と該列方向配
線とが絶縁膜を介する交差部を有し、かつ該交差部にお
いて少なくともいずれかの配線の膜厚が該交差部以外の
該配線の膜厚より薄いことを特徴とする表面伝導型電子
放出素子基板で、交差部における配線の膜厚と該絶縁膜
の膜厚とを合わせた膜厚が該交差部以外の該配線の膜厚
の0.7〜1.3倍であること、該交差部において行方
向配線の少なくとも一部及び列方向配線の少なくとも一
部が該絶縁膜と基板との間に配置されていることを含
む。
According to the present invention for solving the above problems, m number of row-direction wirings and n number of column-direction wirings (where m and n are natural numbers and may be the same or different). ), And a surface conduction electron-emitting device having a thin film including a device electrode and an electron emitting portion and connected to the row-direction wiring and the column-direction wiring on a substrate. , The row-direction wirings and the column-direction wirings have an intersection with an insulating film interposed, and at least one of the wirings at the intersection has a film thickness smaller than that of the wiring other than the intersection. In the characteristic surface conduction electron-emitting device substrate, the total film thickness of the wiring at the intersection and the insulating film is 0.7 to 1. 3 times, and at least the wiring in the row direction at the intersection Comprising at least a portion of a part and the column direction wirings are disposed between the insulating film and the substrate.

【0028】また本発明は上記の表面伝導型電子放出素
子基板を組込んでなる平面型画像形成装置である。
The present invention is also a plane type image forming apparatus incorporating the above surface conduction electron-emitting device substrate.

【0029】また更に本発明は、m本の行方向配線およ
びn本の列方向配線(但し、m,nは自然数で、同一で
も異なっていても良い)と、素子電極および電子放出部
を含む薄膜を有すると共に該行方向配線及び列方向配線
と接続された表面伝導型電子放出素子とを基板上に形成
してなる表面伝導型電子放出素子基板の製造方法におい
て、該行方向配線および列方向配線の交差部以外の行方
向配線又は列方向配線を形成する部分に予め列方向配線
の一部あるいは行方向配線の一部を形成する工程を含む
ことを特徴とする表面伝導型電子放出素子基板の製造方
法である。
Furthermore, the present invention includes m row-direction wirings and n column-direction wirings (where m and n are natural numbers, which may be the same or different), a device electrode and an electron emitting portion. In a method of manufacturing a surface conduction electron-emitting device substrate, which comprises a thin film and a surface conduction electron-emitting device connected to the row-direction wiring and the column-direction wiring on a substrate, the row-direction wiring and the column direction are provided. A surface conduction electron-emitting device substrate including a step of previously forming a part of the column-direction wiring or a part of the row-direction wiring in a portion where the row-direction wiring or the column-direction wiring other than the intersection of the wiring is formed. Is a manufacturing method.

【0030】本発明の素子基板は上記のように構成する
ことにより、グリッド電極を必要とせず、前述のグリッ
ド電極にともなう問題が解決され、製法が簡略化され、
安価でかつ簡易な構成の電子放出素子が提供できるとと
もに、配線表面位置の高低差が緩和され、製造プロセス
における段差によるパターン欠陥を抑制できる。
By configuring the element substrate of the present invention as described above, a grid electrode is not required, the above problems associated with the grid electrode are solved, and the manufacturing method is simplified.
It is possible to provide an electron-emitting device that is inexpensive and has a simple structure, reduce the height difference between wiring surface positions, and suppress pattern defects due to steps in the manufacturing process.

【0031】また、該交差部において行方向配線の少な
くとも一部及び列方向配線の少なくとも一部は該絶縁膜
と基板との間に配置することにより絶縁膜端部における
配線の断線が抑制でき歩留まりが向上する。あるいは、
交差部における配線の膜厚と該絶縁膜の膜厚とを合わせ
た膜厚が該交差部以外の該配線の膜厚とほぼ等しいこと
により絶縁膜端部における配線の断線が抑制できる。ま
た、前述の表面伝導型電子放出素子を用いて、平面型画
像形成装置を形成することにより安価でかつ簡易な構成
の平面型画像形成装置を提供できる。
By disposing at least a part of the row-direction wiring and at least a part of the column-direction wiring at the intersection between the insulating film and the substrate, disconnection of the wiring at the end of the insulating film can be suppressed and the yield can be improved. Is improved. Alternatively,
Since the total film thickness of the wiring at the intersection and the film thickness of the insulating film is substantially equal to the film thickness of the wiring other than the intersection, disconnection of the wiring at the end of the insulating film can be suppressed. Further, by forming a flat image forming apparatus using the above-mentioned surface conduction electron-emitting device, it is possible to provide a flat image forming apparatus having an inexpensive and simple structure.

【0032】更に、本発明方法によれば、グリッド電極
にともなう歩留まりの低下を抑制できるとともに、配線
の断線欠陥を抑制できる容易な製造方法を提供できる。
Further, according to the method of the present invention, it is possible to provide an easy manufacturing method capable of suppressing the decrease in yield due to the grid electrode and suppressing the disconnection defect of the wiring.

【0033】本発明による画像形成装置の実施態様につ
いて以下に説明する。図1にマトリックス状配線基板の
配線構成図を、図2に画像形成装置の構成図を示す。
An embodiment of the image forming apparatus according to the present invention will be described below. FIG. 1 shows a wiring configuration diagram of a matrix wiring substrate, and FIG. 2 shows a configuration diagram of an image forming apparatus.

【0034】図1において101は石英ガラス、Naな
どの不純物含有量を減少したガラス、青板ガラス、Si
2 を積層した青板などのガラス基板およびアルミナな
どのセラミックス基板などの絶縁性基板、102はN
i,Cr,Au,Mo,W,Pt,Ti,Al,Cu,
Pdなどの金属あるいは合金およびPd,Ag,Au,
RuO2 ,Pd−Agなどの金属あるいは金属酸化物と
ガラスなどから構成される印刷導体、In2 3 −Sn
2 などの透明導体およびポリシリコンなどの半導体材
料などの半導体導体材料などの抵抗が十分低い材料から
なる列方向配線、103は配線102と同様抵抗が十分
に低い材料からなる行方向配線、104は絶縁体材料で
ある。
In FIG. 1, 101 is quartz glass, glass with a reduced content of impurities such as Na, soda lime glass, and Si.
An insulating substrate such as a glass plate such as a blue plate laminated with O 2 and a ceramics substrate such as alumina, 102 is N
i, Cr, Au, Mo, W, Pt, Ti, Al, Cu,
Metals or alloys such as Pd and Pd, Ag, Au,
A printed conductor composed of a metal such as RuO 2 , Pd-Ag or a metal oxide and glass, In 2 O 3 -Sn
A column-directional wiring made of a material having a sufficiently low resistance such as a transparent conductor such as O 2 and a semiconductor conductor material such as a semiconductor material such as polysilicon, 103 is a row-directional wiring made of a material having a sufficiently low resistance like the wiring 102, 104 Is an insulator material.

【0035】図2において201は表面伝導型電子放出
素子が形成されたマトリックス状配線基板200を固定
したリアプレートである。ここで、リアプレートはマト
リックス状配線基板を補強する目的で設けられているた
め、マトリックス状配線基板が十分な強度を持つ場合は
不要である。また、202は支持枠、203は蛍光体、
204はフェースプレートである。
In FIG. 2, reference numeral 201 denotes a rear plate on which a matrix wiring board 200 having surface conduction electron-emitting devices is fixed. Here, since the rear plate is provided for the purpose of reinforcing the matrix wiring board, it is unnecessary when the matrix wiring board has sufficient strength. Further, 202 is a support frame, 203 is a phosphor,
Reference numeral 204 is a face plate.

【0036】ここで、配線構造は図1に示した形状に限
らず、図3b(A−A′断面図)に示す様に絶縁材料3
04と基板301との間に列方向配線302の幅全部
と、行方向配線303と接続される補充配線302aの
一部の配線が配置されていてもかまわない。また、図1
2に示すように基板側に配置された配線(本態様におい
ては配線1202)が交差部において配線1202と一
体になる補充配線1203aと比較して膜厚が薄い構造
を有していてもかまわない。また、両方の配線が交差部
において膜厚が薄い構造でもかまわない。
Here, the wiring structure is not limited to the shape shown in FIG. 1, but the insulating material 3 as shown in FIG.
The entire width of the column-direction wiring 302 and a part of the supplementary wiring 302a connected to the row-direction wiring 303 may be arranged between 04 and the substrate 301. Also, FIG.
As shown in FIG. 2, the wiring arranged on the substrate side (the wiring 1202 in the present embodiment) may have a structure having a smaller film thickness than the supplementary wiring 1203a integrated with the wiring 1202 at the intersection. . Further, the structure may be such that both wirings have a thin film thickness at the intersection.

【0037】しかし、交差部における配線の膜厚と絶縁
膜の膜厚とを合わせた膜厚が、該配線の交差部以外の配
線の膜厚の0.7〜1.3倍であることが好ましい。
However, the total film thickness of the wiring and the insulating film at the intersection is 0.7 to 1.3 times the film thickness of the wiring other than the intersection. preferable.

【0038】[0038]

【実施例】【Example】

〔実施例1〕本発明による表面伝導型電子放出素子およ
びそれを用いた画像形成装置の第1の実施例について説
明する。
[Embodiment 1] A first embodiment of a surface conduction electron-emitting device according to the present invention and an image forming apparatus using the same will be described.

【0039】図4に本実施例による表面伝導型電子放出
素子の工程図を示す。 工程 a 清浄化した青板ガラス上に厚さ0.5μmのシリコン酸
化膜をスパッタ法で形成した基板401上に、真空蒸着
により厚さ50 のCr、厚さ6000 のAu、厚さ
300ÅのCrを順次積層した後、ホトレジスト(AZ
1370ヘキスト社製)をスピンナーにより回転塗布、
ベークした後、ホトマスク像を露光、現像して、列方向
配線402のレジストパターンを形成し、Au/Cr堆
積膜をウエットエッチングして、所望の形状の下配線4
02を形成した。 工程 b その後、所望のパターンをホトレジスト(RD−200
0N−41 日立化成社製)形成し、真空蒸着法によ
り、厚さ50ÅのCr、厚さ10000ÅのAuを順次
堆積した。ホトレジストパターンを有機溶剤で溶解し、
Au/Cr堆積膜をリフトオフし、行方向補充配線40
3を形成した。 工程 c 層間絶縁層としてシリコン酸化膜を10000Å、RF
スパッタにより堆積し、所望の位置にホトレジストパタ
ーンを作り、これをマスクしてエッチングして不要部分
のシリコン酸化膜を取り去り、所望の形状の絶縁膜40
4を形成した。エッチングはCF4 とH2 ガスを用いた
RIE(Reactive Ion Etching)
法によった。 工程 d その後、所望のパターンをホトレジスト(RD−200
0N−41 日立化成社製)形成し、真空蒸着法によ
り、厚さ50ÅのCr、厚さ3000ÅのAuを順次堆
積した。ホトレジストパターンを有機溶剤で溶解し、A
u/Cr堆積膜をリフトオフし、行方向配線405を形
成した。 工程 e その後、素子電極素子電極間ギャップを有するパターン
をホトレジスト(RD−2000N−41 日立化成社
製)形成し、真空蒸着法により、厚さ50ÅのTi、厚
さ1000ÅのNiを順次堆積した。ホトレジストパタ
ーンを有機溶剤で溶解し、Ni/Ti堆積膜をリフトオ
フし、素子電極間隔L1は3μmとし、素子電極幅を3
00μmとする素子電極406を形成した。
FIG. 4 is a process drawing of the surface conduction electron-emitting device according to this embodiment. Step a On a substrate 401 in which a 0.5 μm-thick silicon oxide film was formed on a cleaned soda-lime glass by a sputtering method, Cr with a thickness of 50, Au with a thickness of 6000, and Cr with a thickness of 300 Å were deposited by vacuum deposition. After stacking sequentially, photoresist (AZ
1370 Hoechst) is spin coated by spinner,
After baking, the photomask image is exposed and developed to form a resist pattern of the column-direction wiring 402, and the Au / Cr deposited film is wet-etched to form the lower wiring 4 having a desired shape.
02 was formed. Step b After that, a desired pattern is formed on the photoresist (RD-200
0N-41 (manufactured by Hitachi Chemical Co., Ltd.) was formed, and Cr having a thickness of 50 Å and Au having a thickness of 10000 Å were sequentially deposited by a vacuum vapor deposition method. Dissolve the photoresist pattern with an organic solvent,
The Au / Cr deposited film is lifted off and the supplementary wiring 40 in the row direction is formed.
Formed 3. Step c Silicon oxide film as an interlayer insulating layer is 10000Å, RF
The photoresist film is deposited by sputtering, a photoresist pattern is formed at a desired position, this is masked and etched to remove an unnecessary portion of the silicon oxide film, and an insulating film 40 having a desired shape is formed.
4 was formed. The etching is RIE (Reactive Ion Etching) using CF 4 and H 2 gas.
According to the law. Step d After that, a desired pattern is formed on the photoresist (RD-200).
0N-41 (manufactured by Hitachi Chemical Co., Ltd.) was formed, and Cr having a thickness of 50Å and Au having a thickness of 3000Å were sequentially deposited by a vacuum vapor deposition method. Dissolve the photoresist pattern with an organic solvent, and
The u / Cr deposited film was lifted off to form the row wiring 405. Step e After that, a pattern having a gap between the device electrodes and device electrodes was formed with a photoresist (RD-2000N-41 manufactured by Hitachi Chemical Co., Ltd.), and Ti having a thickness of 50Å and Ni having a thickness of 1000Å were sequentially deposited by a vacuum evaporation method. The photoresist pattern is dissolved in an organic solvent, the Ni / Ti deposition film is lifted off, the device electrode interval L1 is set to 3 μm, and the device electrode width is set to 3
A device electrode 406 having a thickness of 00 μm was formed.

【0040】その後、所望の形状に膜厚1000ÅのC
r膜を真空蒸着により堆積・パターニングし、その上に
有機Pd(ccp4230奥野製薬(株)社製)をスピ
ンナーにより回転塗布、300℃で10分間の加熱焼成
処理をした。また、こうして形成された主元素としてP
dよりなる微粒子からなる電子放出部形成用薄膜の膜厚
は100Å、シート抵抗値は5×104 Ω/□であっ
た。なおここで述べる微粒子膜とは、複数の微粒子が集
合した膜であり、その微細構造として、微粒子が個々に
分散配置した状態のみならず、微粒子が互いに隣接、あ
るいは、重なり合った状態(島状も含む)の膜をさし、
その粒径とは、前記状態で粒子形状が認識可能な微粒子
についての径をいう。つぎに、Cr膜および焼成後の電
子放出部形成用薄膜を酸エッチャントによりエッチング
し、電子放出部形成用薄膜407を形成した。
Then, a C film having a film thickness of 1000Å is formed into a desired shape.
The r film was deposited and patterned by vacuum evaporation, and organic Pd (ccp4230 manufactured by Okuno Chemical Industries Co., Ltd.) was spin-coated with a spinner and heated and baked at 300 ° C. for 10 minutes. Further, P is the main element formed in this way.
The film thickness of the electron-emitting-portion-forming thin film made of fine particles of d was 100Å, and the sheet resistance value was 5 × 10 4 Ω / □. The fine particle film described here is a film in which a plurality of fine particles are aggregated, and its fine structure is not only in a state in which the fine particles are individually dispersed and arranged but also in a state in which the fine particles are adjacent to each other or overlap each other (also in an island shape). (Including)
The particle diameter means the diameter of fine particles whose particle shape can be recognized in the above state. Next, the Cr film and the electron emission part forming thin film after firing were etched with an acid etchant to form an electron emission part forming thin film 407.

【0041】以上述べたようにして、電子放出素子を形
成した。このようにして作成した電子放出素子の配線表
面位置の高低差が補充配線403で緩和される結果、列
方向配線膜厚のみの凹凸に抑えられ、絶縁膜による凹凸
は抑制できた。また、グリッドを用いないため、製法が
簡略化され、大面積電子放出素子を作製しても極端な歩
留まりの低下は起こらなかった。さらに、製造工程の簡
略化により低コスト化出来た。また、絶縁膜段差部によ
る行方向配線の断線が抑えられ、歩留まりが向上した。
An electron-emitting device was formed as described above. As a result of the fact that the height difference of the wiring surface position of the electron-emitting device thus created was alleviated by the supplementary wiring 403, the unevenness due to the film thickness in the column direction alone was suppressed, and the unevenness due to the insulating film was suppressed. Further, since the grid is not used, the manufacturing method is simplified, and even if a large-area electron-emitting device is manufactured, an extremely low yield does not occur. Further, the cost can be reduced by simplifying the manufacturing process. Further, disconnection of the row-direction wiring due to the insulating film step portion was suppressed, and the yield was improved.

【0042】つぎに、以上のようにして作成した電子源
を用いて表示装置を構成した例を、図13と図14を用
いて説明する。
Next, an example in which a display device is configured using the electron source created as described above will be described with reference to FIGS. 13 and 14.

【0043】以上のようにして多数の平面型表面伝導電
子放出素子を作製した基板1311をリアプレート13
01上に固定した後、基板1311の5mm上方に、フ
ェースプレート1306(ガラス基板1303の内面に
蛍光膜1304とメタルバック1305が形成されて構
成される)を支持枠1302を介し配置し、フェースプ
レート1306、支持枠1302、リアプレート130
1の接合部にフリットガラスを塗布し、大気中にあるい
は窒素雰囲気中で400℃ないし500℃で10分以上
焼成することで封着した。またリアプレート1301へ
の基板1311の固定もフリットガラスで行った。
The substrate 1311 on which a large number of plane type surface conduction electron-emitting devices are manufactured as described above is used as the rear plate 13.
After being fixed on 01, the face plate 1306 (which is formed by forming the fluorescent film 1304 and the metal back 1305 on the inner surface of the glass substrate 1303) is arranged 5 mm above the substrate 1311 via the support frame 1302, and the face plate 1306, support frame 1302, rear plate 130
Frit glass was applied to the joint portion 1 and baked at 400 ° C. to 500 ° C. for 10 minutes or more in the air or in a nitrogen atmosphere for sealing. The frit glass was also used to fix the substrate 1311 to the rear plate 1301.

【0044】図13において、1312は電子放出素
子、1313、1314はそれぞれ列方向及び行方向の
配線である。
In FIG. 13, 1312 is an electron-emitting device, and 1313 and 1314 are wirings in the column and row directions, respectively.

【0045】蛍光膜1304は、モノクロームの場合は
蛍光体のみから成る場合もあるが、本実施例では蛍光体
はストライプ形状を採用し、先にブラックストライプを
形成し、その間隙部に各色蛍光体を塗布し、蛍光膜13
04を作製した。ブラックストライプの材料として通常
良く用いられている黒鉛を主成分とする材料を用いた。
In the case of monochrome, the fluorescent film 1304 may consist of only the fluorescent material, but in this embodiment, the fluorescent material has a stripe shape, and a black stripe is formed first, and the fluorescent material of each color is provided in the gap. Is applied, and the fluorescent film 13 is applied.
04 was produced. As a material for the black stripe, a material containing graphite as a main component, which is often used, was used.

【0046】ガラス基板1303に蛍光体を塗布する方
法はスラリー法を用いた。
A slurry method was used as a method for applying the phosphor to the glass substrate 1303.

【0047】また、蛍光膜1304の内面側には通常メ
タルバック1305が設けられる。メタルバックは、蛍
光膜作製後、蛍光膜の内面側表面の平滑化処理(通常フ
ィルミングと呼ばれる)を行い、その後、Alを真空蒸
着することで作製した。
Further, a metal back 1305 is usually provided on the inner surface side of the fluorescent film 1304. The metal back was manufactured by performing a smoothing process (usually called filming) on the inner surface of the fluorescent film after manufacturing the fluorescent film, and then vacuum-depositing Al.

【0048】フェースプレート1306には、更に蛍光
膜1304の導電性を高めるため、蛍光膜1304の外
面側に透明電極(不図示)が設けられる場合もあるが、
本実施例では、メタルバックのみで十分な導電性が得ら
れたので省略した。
The face plate 1306 may be provided with a transparent electrode (not shown) on the outer surface side of the fluorescent film 1304 in order to further enhance the conductivity of the fluorescent film 1304.
In this example, since sufficient conductivity was obtained only with the metal back, it was omitted.

【0049】前述の封着を行う際、カラーの場合は各色
蛍光体と電子放出素子とを対応させなくてはいけないた
め、十分な位置合わせを行った。
In the case of the above-mentioned sealing, in the case of a color, the phosphors of the respective colors and the electron-emitting devices have to correspond to each other, so that sufficient alignment is performed.

【0050】以上のようにして完成したガラス容器内の
雰囲気を排気管(図示せず)を通じ真空ポンプにて排気
し、十分な真空度に達した後、容器外端子Dxolない
しDoxmとDoylないしDoynを通じ電子放出素
子1312の電極1313、1314間に電圧を印加
し、電子放出部を、電子放出部形成用薄膜を通電処理
(フォーミング処理)することにより作成した。フォー
ミング処理の電圧波形を図14に示す。
The atmosphere in the glass container completed as described above is exhausted by a vacuum pump through an exhaust pipe (not shown), and after reaching a sufficient degree of vacuum, the terminals outside the container Dxol or Doxm and Doyl or Doyn. A voltage is applied between the electrodes 1313 and 1314 of the electron-emitting device 1312 through the through-hole, and the electron-emitting portion is formed by energizing (forming) the thin film for forming the electron-emitting portion. FIG. 14 shows the voltage waveform of the forming process.

【0051】図14中、T1及びT2は電圧波形のパル
ス幅とパルス間隔であり、本実施例ではT1を1ミリ
秒、T2を10ミリ秒とし、三角波の波高値(フォーミ
ング時のピーク電圧)は5Vとし、フォーミング処理は
約1×10-6torrの真空雰囲気下で60秒間行っ
た。
In FIG. 14, T1 and T2 are the pulse width and the pulse interval of the voltage waveform. In this embodiment, T1 is 1 ms and T2 is 10 ms, and the peak value of the triangular wave (peak voltage during forming). Was 5 V and the forming treatment was performed for 60 seconds in a vacuum atmosphere of about 1 × 10 −6 torr.

【0052】このように作成された電子放出部は、パラ
ジウム元素を主成分とする微粒子が分散配置された状態
となり、その微粒子の平均流径は30Åであった。
In the electron-emitting portion thus produced, fine particles containing palladium element as a main component were dispersed and arranged, and the average flow diameter of the fine particles was 30Å.

【0053】フォーミングを行い、電子放出部を形成し
電子放出素子を作製した。
Forming was performed to form an electron emitting portion, and an electron emitting device was manufactured.

【0054】次に10-6torr程度の真空度で、不図
示の排気管をガスバーナーで熱することで溶着し外囲器
の封止を行った。最後に封止後の真空度を維持するため
に、ゲッター処理を行った。これは、封止を行う直前
に、高周波加熱等の加熱法により、画像形成装置内の所
定の位置(不図示)に配置されたゲッターを加熱し、蒸
着膜を形成処理した。ゲッターはBa等を主成分とし
た。
Next, at a vacuum degree of about 10 -6 torr, an unillustrated exhaust pipe was heated by a gas burner to weld and seal the envelope. Finally, a getter process was performed in order to maintain the degree of vacuum after sealing. Immediately before sealing, a getter placed at a predetermined position (not shown) in the image forming apparatus was heated by a heating method such as high-frequency heating to form a vapor deposition film. The getter was mainly composed of Ba or the like.

【0055】以上のように完成した本発明の画像表示装
置において、各電子放出素子には、容器外端子Dxlな
いしDxm,DylないしDynを通じ、走査信号及び
変調信号を不図示の信号発生手段よりそれぞれ、印加す
ることにより、電子放出させ、高圧端子Hvを通じ、メ
タルバック1305に数kV以上の高圧を印加し、電子
ビームを加速し、蛍光膜1304に衝突させ、励起・発
光させることで画像を表示した。 〔実施例2〕本発明による表面伝導型電子放出素子の第
2の実施例について説明する。
In the image display device of the present invention completed as described above, the scanning signal and the modulation signal are respectively supplied to the respective electron-emitting devices from the signal generating means (not shown) through the terminals Dxl to Dxm and Dyl to Dyn outside the container. , Is applied to cause electrons to be emitted, and a high voltage of several kV or more is applied to the metal back 1305 through the high voltage terminal Hv to accelerate the electron beam, collide with the fluorescent film 1304, and cause excitation / light emission to display an image. did. [Embodiment 2] A second embodiment of the surface conduction electron-emitting device according to the present invention will be described.

【0056】図5に本実施例による表面伝導型電子放出
素子の工程図を示す。 工程 a 清浄化した青板ガラス上に厚さ0.5μmのシリコン酸
化膜をスパッタ法で形成した基板501上に、真空蒸着
により厚さ50ÅのCr、厚さ10000ÅのAu、厚
さ300ÅのCrを順次積層した後、ホトレジスト(A
Z1370ヘキスト社製)をスピンナーにより回転塗
布、ベークした後、ホトマスク像を露光、現像して、列
方向配線および行方向配線の一部502のレジストパタ
ーンを形成し、Cr/Au/Cr堆積膜をウエットエッ
チングして、所望の形状の下配線である列方向配線50
2及び補充配線502aを形成した。なお、列方向配線
502の幅は補充配線502aよりも幅広に形成した。 工程 b 層間絶縁層としてシリコン酸化膜を10000Å、RF
スパッタにより堆積し、所望の位置にホトレジストパタ
ーンを作り、これをマスクとしてエッチングして不要部
分のシリコン酸化膜を取り去り、所望の形状の層間絶縁
膜503を形成した。エッチングはCF4 とH2 ガスを
用いたRIE(Reactive Ion Etchi
ng)法によった。 工程 c その後、所望のパターンをホトレジスト(RD−200
0N−41 日立化成社製)形成し、真空蒸着法によ
り、厚さ50ÅのCr、厚さ3000ÅのAuを順次堆
積した。ホトレジストパターンを有機溶剤で溶解し、A
u/Cr堆積膜をリフトオフし、行方向配線504を形
成した。 工程 d その後、素子電極素子電極間ギャップを有するパターン
をホトレジスト(RD−2000N−41 日立化成社
製)形成し、真空蒸着法により、厚さ50ÅのTi、厚
さ1000ÅのNiを順次堆積した。ホトレジストパタ
ーンを有機溶剤で溶解し、Ni/Ti堆積膜をリフトオ
フし、素子電極間隔L1は3μmとし、素子電極の幅W
1を300μmとする素子電極505を形成した。
FIG. 5 is a process diagram of the surface conduction electron-emitting device according to this embodiment. Step a On a substrate 501 in which a 0.5 μm-thick silicon oxide film is formed on a cleaned soda-lime glass by a sputtering method, 50 Å of Cr, 10000 Å of Au in thickness, and 300 Å of Cr in thickness are deposited by vacuum evaporation. After sequentially stacking, photoresist (A
(Z1370 Hoechst Co., Ltd.) is spin coated by a spinner and baked, and then a photomask image is exposed and developed to form a resist pattern of a part 502 of the column direction wiring and the row direction wiring, and the Cr / Au / Cr deposited film is formed. The column-direction wiring 50, which is the lower wiring of a desired shape, is wet-etched.
2 and the supplementary wiring 502a are formed. The width of the column wiring 502 was formed wider than that of the supplementary wiring 502a. Step b: Silicon oxide film as an interlayer insulating layer is 10,000 Å, RF
The photoresist pattern was deposited by sputtering, a photoresist pattern was formed at a desired position, and the silicon oxide film was removed by etching using this as a mask to form an interlayer insulating film 503 having a desired shape. The etching is performed by RIE (Reactive Ion Etchi) using CF 4 and H 2 gas.
ng) method. Step c After that, a desired pattern is formed on the photoresist (RD-200
0N-41 (manufactured by Hitachi Chemical Co., Ltd.) was formed, and Cr having a thickness of 50Å and Au having a thickness of 3000Å were sequentially deposited by a vacuum vapor deposition method. Dissolve the photoresist pattern with an organic solvent, and
The u / Cr deposited film was lifted off, and the row wiring 504 was formed. Step d After that, a pattern having a gap between the device electrodes and device electrodes was formed with a photoresist (RD-2000N-41 manufactured by Hitachi Chemical Co., Ltd.), and Ti having a thickness of 50Å and Ni having a thickness of 1000Å were sequentially deposited by a vacuum evaporation method. The photoresist pattern is dissolved in an organic solvent, the Ni / Ti deposition film is lifted off, the device electrode interval L1 is set to 3 μm, and the device electrode width W is set.
A device electrode 505 having a thickness of 1 as 300 μm was formed.

【0057】その後、所望の形状に膜厚1000ÅのC
r膜を真空蒸着により堆積・パターニングし、そのうえ
に有機Pd(ccp4230奥野製薬(株)社製)をス
ピンナーにより回転塗布、300℃で10分間の加熱焼
成処理をした。また、こうして形成された主元素として
Pdよりなる微粒子からなる電子放出部形成用薄膜の膜
厚は100Å、シート抵抗値は5×104 Ω/□であっ
た。なおここで述べる微粒子膜とは、複数の微粒子が集
合した膜であり、その微細構造として、微粒子が個々に
分散配置した状態のみならず、微粒子が互いに隣接、あ
るいは、重なり合った状態(島状も含む)の膜をさし、
その粒径とは、前記状態で粒子形状が認識可能な微粒子
についての径をいう。つぎに、Cr膜および焼成後の電
子放出部形成用薄膜を酸エッチャントによりエッチング
し、電子放出部形成用薄膜を通電処理(フォーミング)
することにより所望のパターンを有する電子放出部を含
む薄膜506を形成した。
After that, a C film having a film thickness of 1000Å was formed into a desired shape.
The r film was deposited and patterned by vacuum evaporation, and organic Pd (ccp4230 manufactured by Okuno Chemical Industries Co., Ltd.) was spin-coated with a spinner and heated and baked at 300 ° C. for 10 minutes. In addition, the film thickness of the electron emission portion forming thin film formed of fine particles of Pd as the main element thus formed was 100Å, and the sheet resistance value was 5 × 10 4 Ω / □. The fine particle film described here is a film in which a plurality of fine particles are aggregated, and its fine structure is not only in a state in which the fine particles are individually dispersed and arranged but also in a state in which the fine particles are adjacent to each other or overlap each other (also in an island shape). (Including)
The particle diameter means the diameter of fine particles whose particle shape can be recognized in the above state. Next, the Cr film and the thin film for forming the electron emitting portion after firing are etched with an acid etchant, and the thin film for forming the electron emitting portion is subjected to an electric current treatment (forming).
By doing so, a thin film 506 including an electron emitting portion having a desired pattern was formed.

【0058】以上述べたようにして、電子放出素子を形
成した。このようにして作製した電子放出素子の配線表
面の位置の高低差が絶縁膜厚のみの凹凸に抑えられ、列
方向配線による凹凸は抑制できた。また、グリッドを用
いないため、大面積電子放出素子を作製しても極端に歩
留まりの低下が起こらなかった。さらに、製造工程の簡
略化により低コスト化できた。また、行方向配線の抵抗
を変えず、工程(d)における配線の堆積膜厚を薄くす
ることができた。補充配線502aにより配線抵抗が低
められたことによるものである。 〔実施例3〕本発明による表面伝導型電子放出素子の第
3の実施例について説明する。
An electron-emitting device was formed as described above. The height difference of the position of the wiring surface of the electron-emitting device thus manufactured was suppressed to the unevenness only in the insulating film thickness, and the unevenness due to the column-direction wiring could be suppressed. Moreover, since the grid is not used, the yield does not extremely decrease even if a large-area electron-emitting device is manufactured. Further, the cost can be reduced by simplifying the manufacturing process. Further, the deposited film thickness of the wiring in the step (d) could be reduced without changing the resistance of the wiring in the row direction. This is because the wiring resistance is reduced by the supplementary wiring 502a. [Embodiment 3] A third embodiment of the surface conduction electron-emitting device according to the present invention will be described.

【0059】図6に本実施例による表面伝導型電子放出
素子の工程図を示す。 工程 a 清浄化した青板ガラス上に厚さ0.5μmのシリコン酸
化膜をスパッタ法で形成した基板601上に、真空蒸着
により厚さ50ÅのCr、厚さ10000ÅのAu、厚
さ300ÅのCrを順次積層した。ホトレジスト(AZ
1370ヘキスト社製)をスピンナーにより回転塗布、
ベークした後、ホトマスク像を露光、現像して、列方向
配線602および行方向配線の一部のレジストパターン
を形成し、Cr/Au/Cr堆積膜をウエットエッチン
グして、所望の形状の列方向配線602及び補充配線6
02aを形成した。 工程 b 層間絶縁層としてシリコン酸化膜を3000Å、RFス
パッタにより堆積し、所望の位置にホトレジストパター
ンを作り、これをマスクとしてエッチングして不要部分
のシリコン酸化膜を取り去り、所望の形状の層間絶縁膜
603を形成した。エッチングはCF4 とH2 ガスを用
いたRIE(Reactive IonEtchin
g)法によった。 工程 c その後、所望のパターンをホトレジスト(RD−200
0N−41 日立化成社製)形成し、真空蒸着法によ
り、厚さ50ÅのCr、厚さ10000ÅのAuを順次
堆積した。ホトレジストパターンを有機溶剤で溶解し、
Au/Cr堆積膜をリフトオフし、行方向配線604、
および列方向配線の一部すなわち補充配線604aを形
成した。 工程 d その後、素子電極素子電極間ギャップを有するパターン
をホトレジスト(RD−2000N−41 日立化成社
製)形成し、真空蒸着法により、厚さ50ÅのTi、厚
さ1000ÅのNiを順次堆積した。ホトレジストパタ
ーンを有機溶剤で溶解し、Ni/Ti堆積膜をリフトオ
フし、素子電極間隔L1は3μmとし、素子電極の幅W
1を300μmとする素子電極605を形成した。
FIG. 6 is a process diagram of the surface conduction electron-emitting device according to this embodiment. Step a On a substrate 601 having a 0.5 μm-thick silicon oxide film formed on a cleaned soda-lime glass by a sputtering method, 50 Å of Cr, 10000 Å of Au, and 300 Å of Cr are deposited by vacuum evaporation. The layers were sequentially laminated. Photoresist (AZ
1370 Hoechst) is spin coated by spinner,
After baking, the photomask image is exposed and developed to form a resist pattern of a part of the column-direction wiring 602 and the row-direction wiring, and the Cr / Au / Cr deposited film is wet-etched to form a desired shape in the column direction. Wiring 602 and supplementary wiring 6
02a was formed. Step b A silicon oxide film of 3000 Å is deposited as an interlayer insulating layer by RF sputtering, a photoresist pattern is formed at a desired position, and the silicon oxide film of an unnecessary portion is removed by etching using this as a mask to form an interlayer insulating film of a desired shape. 603 was formed. The etching is performed by RIE (Reactive Ion Etchin) using CF 4 and H 2 gas.
g) According to the method. Step c After that, a desired pattern is formed on the photoresist (RD-200
0N-41 (manufactured by Hitachi Chemical Co., Ltd.) was formed, and Cr having a thickness of 50 Å and Au having a thickness of 10000 Å were sequentially deposited by a vacuum vapor deposition method. Dissolve the photoresist pattern with an organic solvent,
The Au / Cr deposited film is lifted off, and the row wiring 604,
A part of the column direction wiring, that is, the supplementary wiring 604a is formed. Step d After that, a pattern having a gap between the device electrodes and device electrodes was formed with a photoresist (RD-2000N-41 manufactured by Hitachi Chemical Co., Ltd.), and Ti having a thickness of 50Å and Ni having a thickness of 1000Å were sequentially deposited by a vacuum evaporation method. The photoresist pattern is dissolved in an organic solvent, the Ni / Ti deposition film is lifted off, the device electrode interval L1 is set to 3 μm, and the device electrode width W is set.
A device electrode 605 having a thickness of 1 as 300 μm was formed.

【0060】その後、所望の形状に膜厚1000ÅのC
r膜を真空蒸着により堆積・パターニングし、そのうえ
に有機Pd(ccp4230奥野製薬(株)社製)をス
ピンナーにより回転塗布、300℃で10分間の加熱焼
成処理をした。また、こうして形成された主元素として
Pdよりなる微粒子からなる電子放出部形成用薄膜の膜
厚は100Å、シート抵抗値は5×104 Ω/□であっ
た。なおここで述べる微粒子膜とは、複数の微粒子が集
合した膜であり、その微細構造として、微粒子が個々に
分散配置した状態のみならず、微粒子が互いに隣接、あ
るいは、重なり合った状態(島状も含む)の膜をさし、
その粒径とは、前記状態で粒子形状が認識可能な微粒子
についての径をいう。つぎに、Cr膜および焼成後の電
子放出部形成用薄膜を酸エッチャントによりエッチング
し、電子放出部形成用薄膜を通電処理(フォーミング)
することにより所望のパターンを有する電子放出部を含
む薄膜606を形成した。
After that, a C film having a film thickness of 1000Å is formed into a desired shape.
The r film was deposited and patterned by vacuum evaporation, and organic Pd (ccp4230 manufactured by Okuno Chemical Industries Co., Ltd.) was spin-coated with a spinner and heated and baked at 300 ° C. for 10 minutes. In addition, the film thickness of the electron emission portion forming thin film formed of fine particles of Pd as the main element thus formed was 100Å, and the sheet resistance value was 5 × 10 4 Ω / □. The fine particle film described here is a film in which a plurality of fine particles are aggregated, and its fine structure is not only in a state in which the fine particles are individually dispersed and arranged but also in a state in which the fine particles are adjacent to each other or overlap each other (also in an island shape). (Including)
The particle diameter means the diameter of fine particles whose particle shape can be recognized in the above state. Next, the Cr film and the thin film for forming the electron emitting portion after firing are etched with an acid etchant, and the thin film for forming the electron emitting portion is subjected to an electric current treatment (forming).
By doing so, a thin film 606 including an electron emitting portion having a desired pattern was formed.

【0061】以上述べたようにして、電子放出素子を形
成した。このようにして作製した電子放出素子の配線表
面の位置の高低差が絶縁膜の凹凸に抑えられた。また、
グリッドを用いないため、大面積電子放出素子を作製し
ても極端に歩留まりの低下が起こらなかった。さらに、
製造プロセスの簡略化により低コスト化できた。また、
列方向配線の抵抗を変えず、工程(a)における配線の
堆積膜厚を薄くすることが出来た。
An electron-emitting device was formed as described above. The height difference of the position on the wiring surface of the electron-emitting device thus manufactured was suppressed by the unevenness of the insulating film. Also,
Since the grid is not used, the yield does not extremely decrease even if a large-area electron-emitting device is manufactured. further,
The cost can be reduced by simplifying the manufacturing process. Also,
It was possible to reduce the deposited film thickness of the wiring in the step (a) without changing the resistance of the wiring in the column direction.

【0062】[0062]

【発明の効果】本発明によって、以下のような効果が確
認出来た。
According to the present invention, the following effects can be confirmed.

【0063】1)グリッドを用いないため、電子放出素
子作製プロセスが容易になり、製造コストの低減、歩留
まりの向上が計れる。
1) Since the grid is not used, the electron-emitting device manufacturing process is facilitated, the manufacturing cost can be reduced, and the yield can be improved.

【0064】2)配線表面位置の高低差が抑えられ、素
子電極、電子放出素子の形成が容易になる。
2) The height difference of the wiring surface position is suppressed, and the device electrodes and electron-emitting devices are easily formed.

【0065】3)配線抵抗を増加させることなく、配線
形成回数を変えずに1回で堆積する配線膜厚を削減でき
る。このため、製造コストを低減できる。
3) It is possible to reduce the film thickness of the wiring deposited at one time without increasing the wiring resistance and without changing the number of times of forming the wiring. Therefore, the manufacturing cost can be reduced.

【0066】4)配線の断線による欠陥を低減できる。4) It is possible to reduce defects due to disconnection of wiring.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電子放出素子基板の構成を説明するた
めの概略説明図である。
FIG. 1 is a schematic explanatory diagram for explaining a configuration of an electron-emitting device substrate of the present invention.

【図2】本発明の画像形成装置の構成を説明するための
分解斜視図である。
FIG. 2 is an exploded perspective view for explaining the configuration of the image forming apparatus of the present invention.

【図3】本発明の電子放出素子基板の他の構成を説明す
るための概略説明図である。
FIG. 3 is a schematic explanatory diagram for explaining another configuration of the electron-emitting device substrate of the present invention.

【図4】本発明の電子放出素子基板の第1実施例を示す
製造工程図である。
FIG. 4 is a manufacturing process diagram showing a first embodiment of the electron-emitting device substrate of the present invention.

【図5】本発明の電子放出素子基板の第2実施例を示す
製造工程図である。
FIG. 5 is a manufacturing process diagram showing a second embodiment of the electron-emitting device substrate of the present invention.

【図6】本発明の電子放出素子基板の第3実施例を示す
製造工程図である。
FIG. 6 is a manufacturing process diagram showing a third embodiment of the electron-emitting device substrate of the present invention.

【図7】従来の電子放出素子の構成を示す平面図であ
る。
FIG. 7 is a plan view showing a configuration of a conventional electron-emitting device.

【図8】従来の電子放出素子の構成を示す、aは平面
図、bは側面図である。
FIG. 8 is a plan view and b is a side view showing the structure of a conventional electron-emitting device.

【図9】従来の画像形成装置の一部切欠斜視図である。FIG. 9 is a partially cutaway perspective view of a conventional image forming apparatus.

【図10】図9の画像形成装置の側面断面図である。10 is a side sectional view of the image forming apparatus of FIG.

【図11】図9の画像形成装置の電子放出素子基板の製
造工程図である。
11 is a manufacturing process diagram of an electron-emitting device substrate of the image forming apparatus of FIG.

【図12】本発明の電子放出素子基板の他の構成を説明
するための概略説明図である。
FIG. 12 is a schematic explanatory diagram for explaining another configuration of the electron-emitting device substrate of the present invention.

【図13】本発明の画像形成装置の一例を示す一部切欠
斜視図である。
FIG. 13 is a partially cutaway perspective view showing an example of the image forming apparatus of the present invention.

【図14】フォーミング電圧波形を示すグラフである。FIG. 14 is a graph showing a forming voltage waveform.

【符号の説明】[Explanation of symbols]

101 絶縁性基板 102 列方向配線 103 行方向配線 104 絶縁材料 201 リアプレート 202 支持枠 203 蛍光体 204 フェースプレート 301 基板 302 列方向配線 303 行方向配線 304 絶縁材料 401 基板 402 列方向配線 403 補充配線 404 絶縁膜 405 行方向配線 406 素子電極 407 電子放出部形成用薄膜 501 基板 502 列方向配線 502a 補充配線 503 絶縁膜 504 行方向配線 505 素子電極 506 電子放出部を含む薄膜 601 基板 602 列方向配線 602a 補充配線 603 絶縁膜 604 行方向配線 604a 補充配線 606 電子放出部を含む薄膜 701 絶縁性基板 703 電子放出部 704 電子放出部を含む薄膜 705 電子放出部を含む薄膜 706 電子放出部を含む薄膜 801 絶縁性基板 803 電子放出部 804 電子放出部を含む薄膜 805 素子電極 806 素子電極 901 基板 902 リアプレート 903 配線 904 電子放出素子 905 電子通過孔 906 変調電極 907 透明基板 908 蛍光体 909 メタルバック 910 フェースプレート 911 支持枠 912 画像形成装置 1002 素子電極 1003 電子放出部を含む薄膜 1005 絶縁膜 1010 ガラスフリット 1013 配線 1104 電子放出部形成用薄膜 1105 絶縁層 1117 レジスト 1118 素子電極 1201 絶縁性基板 1202 第1の配線 1203 第2の配線 1204 絶縁材料 1301 平面型表面伝導電子放出素子を作製した基
板 1302 支持枠 1303 ガラス基板 1304 蛍光膜 1305 メタルバック 1306 フェースプレート 1308 画像形成装置 1311 基板 1312 電子放出素子 1313 列方向配線 1314 行方向配線
101 Insulating Substrate 102 Column Direction Wiring 103 Row Direction Wiring 104 Insulation Material 201 Rear Plate 202 Support Frame 203 Phosphor 204 Face Plate 301 Substrate 302 Column Direction Wiring 303 Row Direction Wiring 304 Insulation Material 401 Substrate 402 Column Direction Wiring 403 Supplementary Wiring 404 Insulating film 405 Row direction wiring 406 Element electrode 407 Electron emission part forming thin film 501 Substrate 502 Column direction wiring 502a Replenishment wiring 503 Insulation film 504 Row direction wiring 505 Element electrode 506 Thin film including electron emission section 601 Substrate 602 Column direction wiring 602a Replenishment Wiring 603 Insulating film 604 Row-direction wiring 604a Replenishing wiring 606 Thin film including electron emitting portion 701 Insulating substrate 703 Electron emitting portion 704 Thin film including electron emitting portion 705 Thin film including electron emitting portion 706 Electron emitting portion included Thin film 801 Insulating substrate 803 Electron emitting portion 804 Thin film including electron emitting portion 805 Device electrode 806 Device electrode 901 Substrate 902 Rear plate 903 Wiring 904 Electron emitting device 905 Electron passing hole 906 Modulation electrode 907 Transparent substrate 908 Fluorescent substance 909 Metal back 910 Face plate 911 Support frame 912 Image forming apparatus 1002 Element electrode 1003 Thin film including electron emitting portion 1005 Insulating film 1010 Glass frit 1013 Wiring 1104 Electron emitting portion forming thin film 1105 Insulating layer 1117 Resist 1118 Element electrode 1201 Insulating substrate 1202 First substrate Wiring 1203 Second wiring 1204 Insulating material 1301 Substrate on which a planar surface conduction electron-emitting device is manufactured 1302 Support frame 1303 Glass substrate 1304 Fluorescent film 1305 Metal bar Click 1306 faceplate 1308 image forming apparatus 1311 substrate 1312 electron-emitting devices 1313 column wirings 1314 rows directional wirings

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 m本の行方向配線およびn本の列方向配
線(但し、m,nは自然数で、同一でも異なっていても
良い)と、 素子電極および電子放出部を含む薄膜を有すると共に該
行方向配線及び列方向配線と接続された表面伝導型電子
放出素子とを基板上に形成してなる表面伝導型電子放出
素子基板において、 該行方向配線と該列方向配線とが絶縁膜を介する交差部
を有し、かつ該交差部において少なくともいずれかの配
線の膜厚が該交差部以外の該配線の膜厚より薄いことを
特徴とする表面伝導型電子放出素子基板。
1. A wiring having m row-direction wirings and n column-direction wirings (where m and n are natural numbers and may be the same or different), and a thin film including a device electrode and an electron-emitting portion. In a surface-conduction type electron-emitting device substrate in which a surface-conduction type electron-emitting device connected to the row-direction wiring and the column-direction wiring is formed on a substrate, the row-direction wiring and the column-direction wiring are insulating films. A surface-conduction electron-emitting device substrate having an intersecting portion, and the film thickness of at least one of the wirings at the intersecting portion is thinner than the film thickness of the wiring other than the intersecting portion.
【請求項2】 交差部における配線の膜厚と該絶縁膜の
膜厚とを合わせた膜厚が該交差部以外の該配線の膜厚の
0.7〜1.3倍である請求項1に記載の表面伝導型電
子放出素子基板。
2. The total film thickness of the wiring at the intersection and the insulating film is 0.7 to 1.3 times the film thickness of the wiring other than at the intersection. The surface-conduction type electron-emitting device substrate according to.
【請求項3】 該交差部において行方向配線の少なくと
も一部及び列方向配線の少なくとも一部が該絶縁膜と基
板との間に配置されている請求項1に記載の表面伝導型
電子放出素子基板。
3. The surface conduction electron-emitting device according to claim 1, wherein at least a part of the row-direction wiring and at least a part of the column-direction wiring at the intersection are arranged between the insulating film and the substrate. substrate.
【請求項4】 請求項1に記載の表面伝導型電子放出素
子基板を組込んでなることを特徴とする平面型画像形成
装置。
4. A flat-type image forming apparatus comprising the surface conduction electron-emitting device substrate according to claim 1 incorporated therein.
【請求項5】 m本の行方向配線およびn本の列方向配
線(但し、m,nは自然数で、同一でも異なっていても
良い)と、 素子電極および電子放出部を含む薄膜を有すると共に該
行方向配線及び列方向配線と接続された表面伝導型電子
放出素子とを基板上に形成してなる表面伝導型電子放出
素子基板の製造方法において、該行方向配線および列方
向配線の交差部以外の行方向配線又は列方向配線を形成
する部分に予め列方向配線の一部あるいは行方向配線の
一部を形成する工程を含むことを、特徴とする表面伝導
型電子放出素子基板の製造方法。
5. A wiring having m row-direction wirings and n column-direction wirings (where m and n are natural numbers and may be the same or different), and a thin film including a device electrode and an electron-emitting portion. In a method of manufacturing a surface-conduction electron-emitting device substrate, comprising a surface-conduction electron-emitting device connected to the row-direction wiring and the column-direction wiring on a substrate, the intersection of the row-direction wiring and the column-direction wiring is provided. A method of manufacturing a surface-conduction type electron-emitting device substrate, characterized by including a step of previously forming a part of the column-direction wiring or a part of the row-direction wiring in a portion where row-direction wiring or column-direction wiring other than .
JP13271594A 1994-06-15 1994-06-15 Electron-emitting device substrate, method of manufacturing the same, and image forming apparatus incorporating the same Expired - Fee Related JP3313888B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13271594A JP3313888B2 (en) 1994-06-15 1994-06-15 Electron-emitting device substrate, method of manufacturing the same, and image forming apparatus incorporating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13271594A JP3313888B2 (en) 1994-06-15 1994-06-15 Electron-emitting device substrate, method of manufacturing the same, and image forming apparatus incorporating the same

Publications (2)

Publication Number Publication Date
JPH087745A true JPH087745A (en) 1996-01-12
JP3313888B2 JP3313888B2 (en) 2002-08-12

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ID=15087891

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6986692B1 (en) 1998-10-14 2006-01-17 Canon Kabushiki Kaisha Production method of image-forming apparatus, and image-forming apparatus produced by the production method
JP2006202625A (en) * 2005-01-21 2006-08-03 Seiko Epson Corp Electron emitting device, method for manufacturing electron emitting device, electro-optical device, and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6986692B1 (en) 1998-10-14 2006-01-17 Canon Kabushiki Kaisha Production method of image-forming apparatus, and image-forming apparatus produced by the production method
JP2006202625A (en) * 2005-01-21 2006-08-03 Seiko Epson Corp Electron emitting device, method for manufacturing electron emitting device, electro-optical device, and electronic apparatus

Also Published As

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