JPH087998B2 - Memory-circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static memory circuit, and more particularly to shortening a transition time from a read operation to a write operation.

[Outline of Invention]

According to the present invention, in a memory circuit in which reading and writing are performed using a common data line, a P-channel MO is used when shifting from a writing operation to a reading operation.
A first equalizing circuit composed of S transistors and a second equalizing circuit composed of N-channel MOS transistors.
The equalizing circuit is used to raise the voltage of the data line to shorten the transition time from the read operation to the write operation.

[Conventional technology]

FIG. 3 shows an example of the structure of the main part of a conventional static RAM (random access memory) using MOS transistors.

In FIG. 3, reference numeral 51 denotes a memory cell, and a plurality of memory cells 51 are two-dimensionally arranged in a matrix. The input and output of each memory cell 51 are mutually connected to each other.
It is composed of a MOS transistor flip-flop circuit, and a gate MOS transistor for inputting / outputting data is connected to both ends of the flip-flop circuit.

The memory cells 51 arranged in the row direction are connected to a common word line 52. This word line 52 is connected to an X decoder (not shown), and when a row address is designated and one word line 52 is designated, the gate of the memory cell 51 of the row corresponding to this word line 52 is designated. The MOS transistor for is turned on.

The memory cells 51 arranged in the column direction are connected to a common pair of bit line 53 and bit line 54. One ends of the bit line 53 and the bit line 54 are connected to the sources of the load MOS transistor 55 and the MOS transistor 56, respectively. MOS transistor 55
As N and 56, N channel ones are used. MO
The drains of the S transistor 55 and the MOS transistor 56 are connected to the power supply terminal 57 of the power supply voltage V _DD (for example, 5V). MOS
The gates of the transistor 55 and the MOS transistor 56 are commonly connected, and this connection point is connected to the power supply terminal 57.

The other ends of the bit line 53 and the bit line 54 have switching MO
The drains of the S transistor 58 and the MOS transistor 59 are respectively connected. MOS transistor 58 and MOS transistor
As the 59, an N channel one is used. The gates of the MOS transistor 58 and the MOS transistor 59 are commonly connected, and the column signal input terminal 74 is derived from this connection point.

The sources of the MOS transistor 58 and the MOS transistor 59 are connected to the sources of the load MOS transistor 67 and the MOS transistor 66 via the data line 61 and the data line 60, respectively, and the MOS transistor provided between the power supply terminal 57 and the ground. 62 and a MOS transistor 63 connected in series, and a MOS transistor 64 provided between the power supply terminal 57 and the ground.
And the MOS transistor 65 are connected in series. The sources of the MOS transistor 66 and the MOS transistor 67 are connected to the non-inverting input terminal and the inverting input terminal of the sense amplifier 68, respectively. N-channel transistors are used as the MOS transistors 66 and 67. MOS
The drains of the transistor 66 and the MOS transistor 67 are connected to the power supply terminal 57. The gates of MOS transistor 66 and MOS transistor 67 are connected in common, and the write enable signal is sent from this connection point. The input terminal 75 of is derived.

The gate of the MOS transistor 62 and the gate of the MOS transistor 65 are commonly connected, and this connection point is connected to the output terminal of the NOR gate 70. The gate of the MOS transistor 63 and the gate of the MOS transistor 64 are commonly connected.
Connected to the output terminal of R-gate 69. NOR gate 69 and NO
One input terminal of R gate 70 is a write enable signal Connected to the input terminal 71 of. The other input terminal of the NOR gate 70 and the other input terminal of the NOR gate 69 are connected to the inverter 73.
Connected via The connection point between the other input terminal of the NOR gate 70 and the inverter 73 is connected to the data input terminal 72.

At the time of writing, the write enable signal supplied to the terminals 71 and 75 Is low level. This allows the data input terminal 72
Is supplied to the memory cell 51 via the MOS transistor 58 and the MOS transistor 59, the bit line 53 and the bit line 54, respectively, and the data is written in the memory cell 51.

That is, the write enable signal supplied to the terminal 71 Goes low, the NOR gate 69 and NOR gate 70 open, and the input data supplied to the data input terminal 72 becomes NOR.
It is taken out through the gate 69 and the NOR gate 70. The NOR gate 69 is supplied with the inverted data through the inverter 73, and the NOR gate 70 is supplied with the data from the input terminal 72. Therefore, the NOR gate 69 outputs the normal data and the NOR data is output. The inverted data is output from the gate 70. When the output of NOR gate 69 is high level, MOS transistor 63 and MOS transistor 64 turn on, and NOR gate 69
When the output of 70 is high level, the MOS transistors 62 and 65 are turned on. Therefore, when the input data is at the high level, the connection point between the MOS transistor 64 and the MOS transistor 65 is at the low level, and the connection point between the MOS transistor 62 and the MOS transistor 63 is at the high level. When the input data is low level, the connection point between the MOS transistor 64 and the MOS transistor 65 becomes high level, and the connection point between the MOS transistor 62 and the MOS transistor 63 becomes low level.

A column signal is supplied to the terminal 74 from a Y decoder (not shown). When this column signal goes high,
The MOS transistor 58 and the MOS transistor 59 are turned on, and one memory cell 51 is selected. A memory cell through the bit line 53 and the bit line 54, respectively, whose outputs at the connection point between the MOS transistor 62 and the MOS transistor 63 and the connection point between the MOS transistor 64 and the MOS transistor 65 are selected.
Supplied to 51.

Write enable signal supplied to terminals 75 and 71 when reading Is set to a high level, and the load MOS transistors 66 and 67 are turned on.

A word line 52 is selected by an X decoder (not shown), all memory cells connected to the word line 52 are activated, and a predetermined pair of bit lines 53 from a Y decoder (not shown). Also, a high level column signal for the bit line 54 is supplied to the terminal 74, and the MOS transistors 58 and 59 are turned on. Connected to bit line 53 of flip-flop (not shown) in memory cell 51
If the MOS transistor is in the ON state, the MOS transistor 67 to the data line 61, the selection MOS transistor 58
The data line current _ID flows into the memory cell 51 through the path of the bit line 53. In addition, the load MOS transistor 55 connected to one end of the bit line 53 has its gate connected to the power supply voltage V
_The bit line current I _B flows into the memory cell 51 through the MOS transistor 55 by being supplied with _DD and in the ON state. The sum of this bit line current I _B and the above-mentioned data line current I _D becomes the sink current I _M of the memory cell 51.

On the other hand, the MO connected to the bit line 54 in the memory cell 51
The S transistor (not shown) is in the off state, and no current flows into the memory cell 51 from the bit line 54 and the data line 60.

Therefore, the voltages V ₅₃ and V ₅₄ of the bit line 53 and the bit line 54 are different, and two different potentials are supplied to the pre-sense amplifier 68 through the data line 60 and the data line 61 as information of the desired memory cell 51. . The difference signal between the input signals is amplified and supplied to the inverter 76.

When the power supply voltage V _DD is, for example, 5V, the voltage V ₅₄ of the (higher) bit line ₅₄ is affected by the threshold voltage Vth (about 0.7V) of the MOS transistor 56 and the substrate effect ΔVth (about 1.1V). For example, it is about 3.2V, which is low. Further, the voltage V ₅₃ of the bit line 53 is slightly lower than V _{54 due} to the voltage effect in the MOS transistor 55 when the sink current I _M of the memory cell 51 is, for example, 100 μA.
It becomes 2.9V.

In addition, the voltage V ₆₀ and V of the data line 60 and the data line 61
₆₁ is approximately equal to V ₅₃ and V ₅₄ , respectively, for the same reason as above.

However, if the power supply voltage V _DD drops to, for example, about 3 V due to overload, etc., the data line 60 and the data line 61
The voltage V ₆₀ and V ₆₁ of the device will drop to about 1.5V. Since this value is too low as the input voltage of the pre-sense amplifier 68, there is a problem that the read pre-sense amplifier 68 does not operate.

Further, as described above, for example, the voltages V ₆₀ and V _{61 of} both data lines 60 and 61 and the voltages V ₅₃ and V _{54 of} both bit lines 53 and 54 become substantially equal to each other. The drain-source voltage V _DS of 58 and 59 becomes extremely small, and the drive capability of these MOS transistors 58 and 59 deteriorates. Then, the selection MOS transistors 58 and 59, and the MOS transistors 66 and 67.
Even if each area is increased to, for example, four times the area of the bit line driving MOS transistors 55 and 56, there is a problem in that a large data line current cannot be passed and high-speed reading cannot be performed.

Further, the junction capacitances of the column selecting MOS transistors 58 and 59 become stray capacitances of the data line 60 and the data line 61, respectively. For example, in a memory having a capacity of 64 Kbits, the number of columns is 256, and a considerably large stray capacitance is added to the data lines 60 and 61. Moreover, as described above, in this memory, since the drain-source voltage V _DS of the MOS transistors 58 and 59 is low, the junction capacitance thereof is large, and there is a problem that high-speed driving of the data lines 60 and 61 is hindered. It was

Therefore, as shown in FIG. 4, the load circuits of the data line 60 and the data line 61 are connected to the P-channel MOS transistors 85 and 8 respectively.
The present applicant has proposed a memory circuit configured by 6,87. That is, data line 60 and data line
The drains of P-channel MOS transistors 86 and 87 are connected to 61, and a diode-connected P-channel MOS transistor 85 is inserted between the sources of P-channel MOS transistors 86 and 87 and the power supply terminal 57.

When reading, the write enable signal WE supplied to the terminal 75 is set to low level, and the load MOS transistor 86
And 87 to both gates of both MOS transistors 86.
And 87 are turned on. Since its operating point is selected within the triode region, both MOS transistors 86 and 8
The element 7 operates as a resistor and has an equivalent circuit shown in FIG.

Therefore, by using the P-channel MOS transistors 86 and 87 as the load and eliminating the substrate effect ΔVth, when the power supply voltage V _DD is 5 V, the voltages V ₆₀ and V _{61 of} the data line 60 and the data line 61 are respectively reduced. Increased to 3.9V and about 4.1V.

Therefore, as described above, even when the power supply voltage V _DD drops to, for example, about 3V, the voltage of both data lines 60 and 61 is maintained at about 2V, and the read amplifier operates stably.

Further, since the voltage of both data lines 60 and 61 becomes higher than the voltage of both bit lines 53 and 54 by about 1V, respectively, the drain-source voltage V _{DS of} the selection MOS transistors 58 and 59 becomes large, and its drive capability is increased. Is increased, and a large data line current can be passed, and as a result, high-speed reading is possible. Furthermore, since the V _{DS of} the selection MOS transistors 58 and 59 is increased, the junction capacitance thereof is reduced, and the data lines 51 and
The stray capacitance of 52 is reduced, which contributes to high-speed reading.

[Problems to be solved by the invention]

However, by increasing the voltages V ₆₀ and V ₆₁ of the data line 60 and the data line 61 to about 3.9 V and about 4.1 V, respectively, as described above, it is said that the time required to shift from the write operation to the read operation becomes longer. The problem arises. That is, in the write operation, the voltages V ₆₀ and V ₆₁ of the data line 60 and the data line ₆₁ have a high level of about 3.2V and a low level of about 0.3V. When shifting from the write operation to the read operation, the voltages V ₆₀ and V ₆₁ of the data line 60 and the data line 61 at the time of writing are changed from about 0.3 V and about 3.2 V respectively to the data line 60 and the data line 61 at the time of reading. Voltage of V ₆₀ and V _{61 respectively} about 3.
Must be raised to 9V and about 4.1V. If the voltages V ₆₀ and V ₆₁ of the data line 60 and the data line 61 at the time of reading are increased in this way, the voltage difference between the voltages V ₆₀ and V ₆₁ of the data line 60 and the data line 61 at the time of writing becomes large. Becomes
The read (write recovery) time immediately after the transition from the write operation to the read operation is long.

Therefore, an object of the present invention is to provide a memory circuit in which the transition time from a write operation to a read operation is shortened and write recovery can be speeded up.

[Means for solving problems]

The present invention relates to a memory circuit in which reading and writing are performed by using a common data line, and a first pull-up circuit 36, 37 formed by a P-channel MOS transistor between a pair of data lines 10 and 11 and P
A first equalize circuit 38 formed of channel MOS transistors, a second pull-up circuit 39, 40 formed of N-channel MOS transistors, and a second equalize circuit 41 formed of N-channel MOS transistors are arranged. It is a memory circuit characterized by being installed.

[Action]

When shifting from the write state to the read state, the N-channel MOS transistors 39, 40 and the MOS transistor 41 are turned on and the voltage of the data line 10 and the data line 11 is raised to a predetermined level. When the voltage of the data line 10 and the data line 11 reaches 3.2 V, for example, the MOS transistors 39, 40 and MO
The S transistor 41 is turned off. After the voltage of the data line 11 reaches, for example, 3.2V, the voltage of the data line 11 is raised to a predetermined value by the P-channel MOS transistors 36 and 37.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. First
In the figure, 1 indicates a memory cell, and a plurality of memory cells 1 are two-dimensionally arranged in a matrix. Each memory cell 1 is composed of a flip-flop circuit of MOS transistors whose inputs and outputs are mutually connected, and MOS transistors for gates for inputting and outputting data are connected to both ends of this flip-flop circuit.

The memory cells 1 arranged in the row direction are connected to a common word line 2. This word line 2 is connected to an X decoder (not shown), a row address is designated, and when one word line 2 is designated, the gate of the memory cell 1 of the row corresponding to this word line 2 is designated. The MOS transistor for is turned on.

The memory cells 1 arranged in the column direction are connected to a common pair of bit line 3 and bit line 4. One ends of the bit line 3 and the bit line 4 are connected to the sources of the load MOS transistor 5 and the MOS transistor 6, respectively. MOS transistor 5
As N and 6, N-channel ones are used. MO
The drains of the S transistor 5 and the MOS transistor 6 are connected to a power supply terminal 7 having a power supply voltage V _DD (for example, 5V). MOS
The gates of the transistor 5 and the MOS transistor 6 are commonly connected, and this connection point is connected to the power supply terminal 7.

The other ends of the bit lines 3 and 4 are switching MO
The drains of the S transistor 8 and the MOS transistor 9 are respectively connected. N-channel transistors are used as the MOS transistors 8 and 9. The gates of the MOS transistor 8 and the MOS transistor 9 are commonly connected, and the column signal input terminal 24 is derived from this connection point.

The data lines 11 and 10 are connected to the sources of the MOS transistors 8 and 9, respectively. Data line
Between the 10 and the data line 11, a pull-up circuit and an equalize circuit composed of P-channel MOS transistors 36, 37 and 38, and a pull-up circuit and an equalize circuit composed of N-channel MOS transistors 39, 40 and 41. Are connected.

That is, the source of the P-channel MOS transistor 35 is connected to the power supply terminal 7, the gate and drain of the MOS transistor 35 are commonly connected, and this connection point is the P-channel MO.
Connected to the sources of S transistors 36 and 37. The gates of the MOS transistors 36 and 37 are commonly connected, and the terminal 25 is derived from this connection point, and this connection point is connected to the data line.
MO for equalization provided between 10 and data line 11
Connected to the gate of S transistor 38. The drains of the MOS transistors 36 and 37 are connected to the data line 10 and the data line 11, respectively.

The drains of the N-channel MOS transistors 39 and 40 are connected to the power supply terminal 7. The gates of the MOS transistors 39 and 40 are commonly connected, the terminal 28 is led out from this connection point, and this connection point is provided between the data line 10 and the data line 11 for equalizing N channel MO.
It is connected to the gate of the S transistor 41. The sources of the MOS transistors 39 and 40 are connected to the data line 10 and the data line 11.

In addition, the data line 11 is provided between the power supply terminal 7 and the ground.
It is connected to the connection point of the series connection of the MOS transistors 12 and 13. The data line 10 is connected to the connection point of the series connection of the MOS transistors 14 and 15 provided between the power supply terminal 7 and the ground.

The gate of the MOS transistor 12 and the gate of the MOS transistor 15 are commonly connected, and this connection point is connected to the output terminal of the NOR gate 20. The gate of the MOS transistor 13 and the gate of the MOS transistor 14 are commonly connected, and this connection point is NO.
Connected to the output terminal of R gate 19. NOR gate 19 and NO
One input terminal of the R gate 20 is connected to the terminal 21. NOR
The other input terminal of the gate 20 and the other input terminal of the NOR gate 19 are connected via an inverter 23. NOR gate 2
The connection point between the other input terminal of 0 and the inverter 23 is connected to the data input terminal 22.

When the chip enable signal C is low level, the write enable signal Is set to a high level, a low level is supplied to the terminal 25, a high level is supplied to the terminal 28, a high level is supplied to the terminal 21, and a write state is changed to a read state.

Voltage V of data line 10 and data line 11 in write state
As described above, ₁₀ and V ₁₁ are about 0.3V and about 3.2V, respectively, when the power supply voltage V _DD is 5V, the threshold voltage Vth is 0.7V, and the substrate effect ΔVth is 1.1V. Therefore, the terminal
When the high level is supplied to 28, first, the MOS transistors 39 and 40 and the equalizing MOS transistor 41 are turned on. Since the MOS transistors 39 and 40 are N-channel MOS transistors, the MOS transistors 39 and 40
When 40 is turned on, the voltages V ₁₀ and V ₁₁ of the data line 10 and the data line 11 are raised to 3.2V. Further, since the equalizing MOS transistor 41 is turned on, the voltage difference between the bit line 10 and the bit line 11 is reduced.

Note that the equalizing MOS transistor 41 may affect the bit lines 3 and 4 if one of the high-level data lines 10 or 11 is pulled down too much, which may cause a malfunction. Therefore, the size of the MOS transistor 41 needs to be optimally set.

When the voltages V ₁₀ and V _{11 of the} data line 10 and the data line 11 are raised to 3.2V, the MOS transistors 39 and 40 and the MOS transistor 41 are turned off.

At this time, since the low level is being supplied to the terminal 25,
The MOS transistors 36 and 37 and the MOS transistor 38 are on. Data line 10 and data 11 voltages V ₁₀ and V ₁₁
After the voltage is raised to 3.2V, the data lines 10 and 11 are turned on by the P-channel MOS transistors 37 and 36.
The voltages V ₁₀ and V ₁₁ are increased to 4V and 3.7V, respectively.

The equalizing MOS transistor 38 is connected to the data line 1
It is provided to limit the amplitude of 0 and the data line 11. By providing the equalizing MOS transistor 38, the data inversion time is shortened.

In this way, the data line 10 and the data line 11 have the N-channel MO when the write state changes to the read state.
A pull-up circuit consisting of S transistors 39 and 40, and P
It is pulled up by a pull-up circuit composed of channel MOS transistors 36 and 37. That is, in FIG. 2, when the write state is changed to the read state, the time
During t _{1 to} t ₂ , the data line 10 and the data line 11 are pulled up by the pull-up circuit composed of the MOS transistors 39 and 40 and the pull-up circuit composed of the MOS transistors 36 and 37. In addition, one data line 10 to which high level data is transmitted by the equalizing MOS transistor 41.
Alternatively, the data line 11 is pulled down. At time t ₂ ~t ₃ voltages V ₁₀ and V ₁₁ of the data lines 10 and the data line 11 reaches 3.2 V, N-channel MOS transistors 39, 40 and MOS transistor 41 is turned off. And the MOS transistors 36 and 3
7, the voltage V ₁₀ and V ₁₁ of the data line 10 and the data line ₁₁
Is raised, and the read state can be entered from time t ₃ .

〔The invention's effect〕

According to the present invention, when the write state is changed to the read state, the voltage of the data line is the first pull-up circuit configured by the P-channel MOS transistor and the second pull-up circuit configured by the N-channel MOS transistor. It is pulled up by the circuit. The second pull-up circuit composed of N-channel MOS transistors is
When the voltage of the data line is raised to a predetermined value, it turns off. As a result, when the write state is changed to the read state, the voltage of the data line is instantly raised, and the transition time from the write operation to the read operation is shortened.

[Brief description of drawings]

FIG. 1 is a connection diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram used to explain an embodiment of the present invention, FIG. 3 is a connection diagram of an example of a conventional memory circuit, and FIG. FIG. 5 is a connection diagram of another example of the memory circuit of FIG. 5, and FIG. 5 is an equivalent circuit diagram used for explaining the conventional memory circuit. Description of main symbols in the drawings 1: Memory cell, 3, 4: Bit line, 10, 11: Data line, 36, 37:
P-channel MOS transistor for pull-up, 38: P-channel MOS transistor for equalize, 39, 40: N-channel MOS transistor for pull-up, 41: N-channel MOS transistor for equalize.

 ─────────────────────────────────────────────────── ───Continuation of front page (56) References JP-A-59-151387 (JP, A) JP-A-60-154393 (JP, A) 1985 IEEE International Solid-State Circuits Conference-DIG EST OF TECHNICAL PA PERS , P .; 60 to 61. 1984 IEEE International Solid-State Circuits Conference-DIG EST OF TECHNICAL PA PERS, P.P. 224-225.

Claims (1)

[Claims] 1. A P-channel MOS transistor having a source electrode connected to a power supply terminal and a drain electrode and a gate electrode connected to a first terminal in a memory circuit in which reading and writing are performed using a common data line. A pair of P-channel MOS transistors, one of which is commonly connected to the first terminal and the other of which is connected to a pair of data lines. A first equalizer circuit connected between the data lines; a second pull-up circuit composed of a pair of N-channel MOS transistors, one of which is commonly connected to a power supply terminal and the other of which is connected to a pair of data lines; A second one formed by an N-channel transistor and connected between the pair of data lines
And a logical "H" voltage at the time of writing and a logical "H" voltage at the time of reading are supplied to the gate electrodes of the pair of N-channel MOS transistors. A memory circuit characterized in that the gate electrode of a channel MOS transistor is supplied with a logic "H" voltage during writing and a logic "L" voltage during reading.