JPH088295A - Semiconductor mounting device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Purpose] The back surface of the chip can be grounded, and the wiring area on the mounting board can be secured to mount it by the same means as other electronic components. [Structure] A pattern 2 is formed on a polyimide tape 1 with a copper foil. The inner lead 4 for joining to the input / output terminal of the bare chip IC 3 by the TAB method is the tape 1
The device hole 5 is formed in a state of being extended. In addition, the dummy lead 6 is formed by locating the portion where the solid copper foil is formed in a large area in the device hole 5. The dummy lead 6 may be mounted on another printed circuit board as an outer lead 8a arranged in the same manner as the outer lead 7 connected to the inner lead 4, respectively, or may be mounted on the ground line 8b (or the power supply line) on the TAB tape. ) May be connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting device in which a bare chip IC is mounted on a flexible insulating substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high-density mounting technology has become important with the demand for weight reduction and size reduction of electronic devices. Especially, the mounting technology for connecting the semiconductor element to the wiring board is important, and each company is defeating the development in order to commercialize a portable device aiming at further miniaturization. A TAB (Tape Autom) that mounts an IC (integrated circuit) that is not in a mold package, a so-called bare chip, on a flexible substrate.
The ated Bonding) mounting method is the most general-purpose bare chip mounting technology because it has the advantages of being compact and easy to inspect.

A conventional TAB mounting structure will be described below with reference to FIG.
~ It demonstrates using FIG. The TAB mounting structure can be classified into two types, a face-down TAB and a face-up TAB. First, the face down TAB will be described with reference to FIG.

The bare chip IC 81 is subjected to inner lead bonding to the inner lead portion 83 of the TAB tape 82 via the bumps 84, and then resin sealing 85 is performed. Next, the outer lead portion 88 is punched out by a die and subjected to lead forming, and then connected to the wiring board 86 with solder 87.

In this structure, since the electrode forming surface 81a of the IC chip 81 faces downward, the face down TA
Called B. In this structure, another wiring pattern 90 can be formed on the surface of the TAB-mounted printed circuit board, which is advantageous in that the degree of freedom in pattern design is increased. However, the chip back surface 81b is not grounded, and there is a concern that the characteristics may fluctuate due to the floating potential.

Face-up TAB will be described with reference to FIG. In this case, the surface 8a of the TAB is connected to the wiring board 86 with the surface facing upward. In order to improve heat dissipation and to ground the potential of the chip back surface 8b, an area corresponding to the chip back surface 8b is formed as a solid pattern 91 on the substrate and bonded with a conductive adhesive 92.

Therefore, variations in characteristics due to floating potential on the chip back surface 8b can be prevented, and the heat dissipation of the power IC can be improved. However, the wirings facing the TAB back surface, that is, the chip back surface 8b. The substrate 86 cannot be used as a wiring area.

FIG. 10 is a plan view of the TAB tape. The connection with the bare chip IC is performed on the inner lead portion 83 via a bump. The outer lead portion 84 is partially shown on the outermost periphery of the drawing. In addition to the TAB tape, there is also a bare chip mounting example using a flexible substrate, but the connection method to the wiring substrate can be summarized as TAB by face down or face up described above.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the mounting structure, in the face-down TAB, there are variations in characteristics due to the floating potential on the back surface of the chip, and in the face-up TAB, the area corresponding to the back surface of the TAB cannot be used as board wiring, which is disadvantageous for high-density mounting. is there. Furthermore, in both structures, since it is not possible to mount components on the upper and lower surfaces of the bare chip, it is difficult to meet the demand for higher density mounting.

The present invention provides a semiconductor mounting device capable of grounding the back surface of a chip by effective means, securing a wiring area on a mounting board, and mounting other electronic components by the same means, and a method of manufacturing the same. The purpose is to

[0011]

In the semiconductor mounting device of the present invention, the input / output portion of the integrated internal circuit and the input / output terminal arranged on the first surface are electrically connected to each other. A bare chip IC, a flexible insulating substrate formed by connecting the input / output terminals to desired locations of a wiring pattern fixed in advance, and one end of the bare chip IC inside the bare chip IC on the second surface side of the bare chip IC. It is characterized in that it comprises means for connecting and fixing to a reference potential of the circuit, and bending the other end to electrically connect to the reference potential of the insulating substrate having the same potential as the reference potential.

In the method of manufacturing a semiconductor mounting device, the TA
The first step of raising a dummy lead for connecting to the reference potential point formed on the B tape from the bonding surface of the bare chip IC, and arranging it on the surface of the bare chip IC and electrically connected to the internal circuit A second step of electrically connecting the pad to the TAB tape by bonding, and a third step of connecting the raised dummy lead to the back surface of the bonded bare chip IC via a conductive adhesive. Forming the outer lead portion of the TAB tape and connecting it to a printed wiring board;
And the process of.

Also, a TAB tape and a bare chip IC on which dummy leads for connecting to a reference potential point are formed in advance.
A first step of bonding and electrically connecting to a pad arranged on the surface of and connected to an internal circuit; and a second step of forming the outer lead of the TAB tape and soldering it to a printed wiring board. The method further comprises a third step of electrically connecting the dummy lead and the back surface of the bare chip IC with a conductive adhesive.

[0014]

By connecting the wiring pattern which does not contribute to the bonding of the bare chip to the ground pattern on the flexible substrate by the means described above, electrical connection can be made on the back surface side of the bare chip and the back surface of the bare chip can be easily formed. Can be grounded. Also, by mounting electronic components on the wiring pattern, it is possible to arrange the components three-dimensionally on the bare chip.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a plan view of a TAB tape for explaining an embodiment of the present invention. 75 thickness
A pattern 2 is formed on a polyimide tape 1 having a thickness of 20 μm and a copper foil having a thickness of 20 to 40 μm and a width of 100 to 500 μm. The inner leads 4 for joining with the input / output terminals of the bare chip IC 3 by the TAB method are formed in a state of being extended to the device hole 5 of the tape 1. In addition, the dummy lead 6 is formed by locating the portion where the solid copper foil is formed in a large area in the device hole 5. The dummy leads 6 may be mounted on a printed circuit board (not shown) as outer leads 8a arranged in the same manner as the outer leads 7 connected to the inner leads 4, respectively.
Ground line 8b (or power line) on B tape
You may connect to.

FIG. 2 is a cross-sectional view of the structure mounted on the wiring board, and FIG. 3 is a plan view of FIG. 2 seen from above. The position of the outer lead 7 is different from that of FIG. Bare chip I
The connection pads 3b arranged on the surface 3a of C3 and the inner leads 4 are electrically connected by the conductive adhesive 10. At this time, the dummy leads 6 are raised in advance so as not to get in the way when the bare chip IC 3 is connected. After connecting the bare chip IC3, the dummy lead 6
On the back surface 3c formed of bare chip IC3 silicon,
It is electrically connected through the conductive adhesive 11. Usually, the bare chip IC3 has a back surface 3b formed of silicon, and is electrically connected to a reference potential (described as ground here) of its internal circuit.

The outer lead 7 is cut at the portion of the broken line 7a in FIG. 1 and then formed, and the connection pad 1 formed on the printed wiring board 12 on which electronic parts and the like are mounted.
Solder to 3. At this time, the outer leads 8a of the dummy leads 6 are also connected to the connection pads 13 connected to the ground of the printed wiring board 12. As a result, the bare chip I
The back surface 3b of C3 and the ground of the printed wiring board 12 can be electrically connected.

In this embodiment, it is needless to say that the circuit pattern can be formed at the position of the printed wiring board 12 facing the bare chip IC3, and the back surface 3b of the bare chip IC3 is formed.
It can be electrically connected to the ground of the printed wiring board 12 to prevent the potential from floating and to stabilize the characteristics.

When a part of the dummy lead 6 is a pattern integrated with the ground line 8b on the tape 1, the outer lead 7 connected to the ground line 8b is connected to the connection pad 13 connected to the ground of the printed wiring board 12. Solder to. Even in this case, the back surface 3b of the bare chip IC 3 and the ground of the printed wiring board 12 can be electrically connected. The area of the dummy lead 6 extended to the device hole 5 is widened. Therefore, workability when raising the dummy lead 6 located in the device hole 5 in advance is good.

It is necessary to increase the bending strength of the portion 6a or 6b which is bent when the dummy lead 6 is raised, and it is desirable to make the pattern width as wide as possible and make the thickness thick.

Next, referring to FIGS. 1 to 3 again, another embodiment of the present invention will be described. In this embodiment, one end 61a of the dummy pattern 6 is further extended into the device hole 5 from the inner lead 4, and the other end 61b is arranged in the same manner as the other outer lead 7 to form the tape 1. The position of the other end 61b of the dummy pattern 61 in the cross-sectional view of FIG. 2 and the plan view of FIG. 3 when mounted on a wiring board is shown in FIG.
Different from

In this embodiment as well, it is needless to say that a circuit pattern can be formed at the position of the printed wiring board 12 facing the bare chip IC3, and the back surface 3b of the bare chip IC3 and the ground of the printed wiring board 12 are electrically connected to each other to form a potential. Can be prevented and the characteristics can be stabilized.

The dummy pattern 61 is a bare chip I.
It is necessary to raise one end 61a immediately before the inner lead bonding for connecting the input / output terminal of C3 to the inner lead 4.

FIG. 4 is a plan view for explaining another embodiment of the present invention. This embodiment is an application example of a TAB tape on which a bare chip IC 41 of a memory is mounted. Unlike the multi-pin IC shown in FIG. 1, the memory is characterized by a large chip size and a small number of pins. As shown by the hatched portion, the outer leads 44 in which the dummy leads 43 are integrated are formed on the pattern of the TAB tape 42. Among them, the outer lead 44 is for connecting to the wiring board, and the dummy lead 43 is for grounding the back surface of the chip.

FIG. 5 is a sectional structural view when the tape 42 of FIG. 4 is mounted on the printed wiring board 51. After punching the outer lead 44 with the broken line 45, the dummy lead 4
3 is folded back on the back surface 41a of the bare chip IC 41, and is connected via the conductive adhesive 52. In this embodiment, since the dummy leads 43 are integrated on the tape 42 pattern, it can be said that the mounting is easy.

6 and 7 are sectional views showing the manufacturing process of the above-mentioned embodiment. The embodiment of FIG. 2 is shown in FIG.
In FIG. 6A, the dummy lead 6 of the TAB tape 1 is previously removed from the bonding surface of the IC. Next in FIG.
In (b), the bare chip IC 3 is inner lead bonded and connected to the TAB tape 1. Next, FIG.
In (c), the dummy lead 6 removed from the bonding surface is bent to the bonded chip back surface 3c,
Connection is made with the conductive adhesive 11. After that, Fig. 6
As shown in (d), the outer leads 7 and 8a are formed and soldered to the printed wiring board 12.

Next, the manufacturing process of the embodiment described with reference to FIG. 4 will be described with reference to FIG. FIG. 7A shows the TAB tape 42 on which the dummy leads 43 for grounding are formed on the chip back surface 41a. Next, in FIG. 7 (b),
Inner lead bonding of bare chip IC41,
Connect to tape 42. Next, in FIG. 7C, the outer leads 44 are formed and soldered to the printed wiring board 51. At this time, the dummy leads 43 are also punched out by the mold at the same time, but they are not soldered to the printed wiring board 51. Then, the dummy lead 43 is replaced with the outer lead 4
Bending from the 4 side to the back side of the chip and connecting with the conductive adhesive 52.

In this method, as compared with the process of FIG. 6 in which the dummy lead 43 is folded back before the inner lead bonding, the process of FIG. 7 in which the dummy lead is folded after the TAB mounting is completed is more workable. Get better.

[0029]

As described above, according to the semiconductor mounting device and the method of manufacturing the same of the present invention, when the bare chip IC is connected to the flexible substrate, the back surface of the chip can be easily grounded and the wiring of the mounting substrate can be achieved. Space can be secured, and electronic parts can be mounted on the back surface of the chip.

[Brief description of drawings]

FIG. 1 is a front view of a TAB tape for explaining an embodiment of the present invention.

FIG. 2 is a sectional view for explaining a state in which a bare chip IC connected to the tape of FIG. 1 is mounted on a wiring board.

FIG. 3 is a plan view of FIG. 2;

FIG. 4 is a front view for explaining another embodiment of the present invention.

5 is a sectional view for explaining a state in which a bare chip IC connected to the tape of FIG. 4 is mounted on a wiring board.

FIG. 6 is an explanatory diagram for explaining the manufacturing process of the embodiment described in FIG.

FIG. 7 is an explanatory diagram for explaining the manufacturing process of the embodiment described in FIG.

FIG. 8 is a sectional view for explaining a conventional face-down TAB.

FIG. 9 is a sectional view for explaining a conventional face-up TAB.

FIG. 10 is a front view of a conventional TAB tape.

[Explanation of symbols]

1, 40, 42 ... Tape, 2 ... Pattern, 3, 41 ... Bare chip IC, 4 ... Inner lead, 5 ... Device hole, 6,43 ... Dummy lead, 7, 8a, 42, 44 ...
Outer lead, 8b ... Ground line 10, 11,
52 ... Conductive adhesive, 12, 51 ... Printed wiring board, 6
1 ... Dummy pattern.

Claims (7)

[Claims] 1. An input / output unit of an integrated internal circuit and a first
A bare chip IC electrically connected to the input / output terminals arranged on the surface, and one end connected to a desired portion of the wiring pattern previously fixed to the input / output terminal and the other end connected to another print. A flexible wiring board connected to the wiring board, having one end connected to the second surface of the bare chip IC and the other end connected to the reference potential of the other printed wiring board. Semiconductor mounting device. 2. The bare chip IC at each of the one ends
2. The semiconductor mounting device according to claim 1, wherein the flexible wiring board connected to the first and second surfaces is a pad whose pattern is extended. 3. The semiconductor mounting device according to claim 1, wherein one end of each of the flexible wiring boards is a lead having a pattern formed on a base material of the flexible board. 4. The flexible wiring board according to claim 1, wherein one end connected to the first surface is a pad and one end connected to the second surface is a lead. Semiconductor mounting equipment. 5. The flexible wiring board according to claim 1, wherein one end connected to the first surface is a lead and one end connected to the second surface is a pad. Semiconductor mounting equipment. 6. A first step of raising a dummy lead for connecting to a reference potential point previously formed on a TAB tape from a bonding surface of the bare chip IC, and arranging the dummy lead on the surface of the bare chip IC to form an internal circuit. A second step of electrically connecting the pad electrically connected to the TAB tape and electrically connecting the pad to the TAB tape. A method of manufacturing a semiconductor mounting device, comprising a third step of connecting and a fourth step of forming the outer lead portion of the TAB tape and connecting it to a printed wiring board. 7. A first step of electrically connecting by bonding a TAB tape on which a dummy lead for connecting to a reference potential point is formed in advance and a pad arranged on the surface of a bare chip IC and connected to an internal circuit And forming the outer lead of the TAB tape,
Manufacturing of a semiconductor mounting device comprising a second step of soldering to a printed wiring board and a third step of electrically connecting the dummy lead and the back surface of the bare chip IC with a conductive adhesive. Method.