JPH088362A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] Suppresses ground bounce noise, which tends to increase due to higher integration and higher pin count. [Structure] A metal layer 5 is formed on a first capacitor of a base substrate 1 formed by facing a ground wiring layer 3 and a power supply wiring layer 4 to each other.
By connecting the second capacitors of the cap 6 formed by facing a and 5b in parallel with each other through the solder sealing material 10, the capacitor capacitance between the power supply terminal and the ground terminal is increased, and the high integration semiconductor device Suppresses ground bounce noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a package.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional semiconductor device is formed on the lower surface of a base substrate 1 in which a signal wiring 2, a ground wiring layer 3 made of a sheet metal layer and a power wiring layer 4 are built. It has an external terminal 11 electrically connected to each of the signal wire 2, the ground wiring layer 3, and the power supply wiring layer 4 through the through hole, and the semiconductor chip 7 is die-mounted in the recess of the cap 6 by using the brazing material 8. After that, the base substrate 1 is sealed with the sealing material 12 at the same time as bonding the signal wiring 2, the ground wiring layer 3, and the power wiring layer 4 of the base substrate 1 through the bumps 9 of the semiconductor chip 7. Composed.

Here, the capacitor formed by the ground wiring layer 3 and the electrode wiring layer 4 of the base substrate 1 is used as shown in FIG.
As shown in the transistors Q _1, Q plurality of elements of the ground bounce noise (on the semiconductor chip by connecting a capacitance C _b between the power supply terminal of the semiconductor chip and the ground terminal having a ₂ formed of an electron circuit or the like are simultaneously turned on (/ Noise generated due to fluctuations in the ground wiring or power supply potential that occur when the power is turned off).

[0004]

In this conventional semiconductor device, the number of through-holes penetrating the power supply wiring layer and the ground wiring layer of the base substrate forming the capacitor due to the increase in the number of pins accompanying the high integration of the semiconductor chip is also increased. As a result, the area of the metal layer is reduced and the capacitor capacitance of the base substrate is reduced, while the ground bounce noise tends to increase due to the increase in the number of elements on the semiconductor chip. Had a problem that could not be suppressed.

An object of the present invention is to provide a semiconductor device in which a capacitor having a large capacitance value for suppressing ground bounce noise is built in a package.

[0006]

The semiconductor device of the present invention comprises:
A base substrate having a laminated structure containing a first capacitor formed by facing a ground wiring layer and a power supply wiring layer formed of sheet metal layers, and a second capacitor formed by facing at least two metal layers And a cap for connecting the first capacitor and the second capacitor in parallel via a conductive sealing material and sealing the base substrate with the conductive sealing material, and a cap inside the cap. It is configured to include a semiconductor chip that is die-mounted and electrically connected to at least the ground wiring layer and the power supply wiring layer via bumps.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention.

As shown in FIG. 1, a built-in capacitor formed by opposing a signal wiring 2 and a ground wiring layer 3 made of a sheet-like metal layer and a power supply wiring layer 4 to each other is laminated and made of ceramic or glass epoxy. A base substrate 1 having a structure, and at least two metal layers 5a, 5 having a laminated structure.
Built-in capacitor formed by facing b
The solder cap 8 such as a u-Si alloy is made to face the ceramic cap 6 on which the semiconductor chip 7 is die-mounted, and the bump 9
Signal wiring 2 between the semiconductor chip 7 and the base substrate 1 via
Solder encapsulant 10 for electrically connecting the ground wiring layer 3 and the power supply wiring layer 4 and at the same time annularly provided on the peripheral portion of the cap 6 to seal the cap 6 and the base substrate 1.
Through the metal layer 5a, the ground wiring layer 3, and the metal layer 5b
And the power supply wiring layer 4 are electrically connected to each other, and the signal wiring 2, the ground wiring layer 3, and the power supply wiring 4 are provided on the lower surface of the base substrate 1 via through holes.
It is configured to be electrically connected to.

The capacitor provided in the cap 6 is effective because it does not need to form a through hole for connecting the signal wiring to the external terminal 11 as compared with the capacitor built in the base substrate 1. The area is increased, and a capacitance value about 1.5 times that of the capacitor built in the base substrate 1 is obtained. As shown in FIG. 2, between the power supply terminal and the ground terminal, the capacitance C _b of the base substrate is The capacitor capacitance C _{c of the} cap is connected in parallel, and a sufficiently large capacitor capacitance for suppressing ground bounce noise can be secured.

[0011]

As described above, according to the present invention, by forming a capacitor with a metal film facing a cap of a package and connecting the capacitor in parallel with a capacitor of a base substrate,
There is an effect that it is possible to prevent the ground bounce noise of the highly integrated semiconductor device by compensating for the capacitor capacitance of the base substrate which is reduced by the increase in the number of pins of the package.

[0012]

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an embodiment of the present invention.

FIG. 3 is a sectional view showing an example of a conventional semiconductor device.

FIG. 4 is a circuit diagram for explaining a conventional semiconductor device.

[Explanation of symbols]

 1 Base Board 2 Signal Wiring 3 Ground Wiring 4 Power Wiring 5a, 5b Metal Layer 6 Cap 7 Semiconductor Chip 8 Brazing Material 9 Bump 10 Solder Sealing Material 11 External Terminal 12 Sealing Material

Claims (2)

[Claims] 1. A base substrate having a laminated structure containing a first capacitor formed by facing a ground wiring layer and a power wiring layer, which are sheet-like metal layers, and at least two metal layers facing each other. And a cap that contains the second capacitor and that connects the first capacitor and the second capacitor in parallel via a conductive sealing material and that seals the base substrate with the conductive sealing material, A semiconductor device comprising: a semiconductor chip that is die-mounted inside the cap and that is electrically connected to at least the ground wiring layer and the power wiring layer via a bump. 2. The semiconductor device according to claim 1, wherein the conductive sealing material is solder.