JPH0884340A - Image data coder - Google Patents

Abstract

PURPOSE: To reduce considerably a processing time for entropy coding by providing an exclusive circuit to convert a DCT coefficient into a Huffman code in the coder. CONSTITUTION: The coder that converts a DCT coefficient into a Huffman code is provided with Huffman code table storage devices 105, 106 storing exclusively a Huffman code table, a Huffman coder 101 converting a received numeral into a Huffman code by referencing the Huffman code table, a processing sequence storage device 104 storing in which order 64 sets of DCT coefficients in total are processed, and a DCT coefficient transfer device 102 transferring the 64 sets of DCT coefficients to the Huffman coder 101 according to the sequence represented by the processing sequence storage device 104.

Description

Detailed Description of the Invention

[0001]

The present invention relates to image data, especially DC.
T (Discrete Cosine Transfer)
r) The present invention relates to encoding of numerical data called DCT coefficient after the processing.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, "Interface", December 1991 issue,
P. 183 to 203, “JPEG-compliant image data compression / expansion system realized in C” by Hiroshi Inamura. Figure 7 is a CCITT called JPEG
Of the color still image encoding method by both ISO and ISO groups is shown in a hard image, FIG. 8 is a diagram showing the DC coefficient processing algorithm of the entropy encoding in a hard image, and FIG. 9 is its entropy encoding. FIG. 6 is a diagram showing a hard image of the AC coefficient processing algorithm of FIG.

As described above, conventionally, image data compression processing as shown in FIG. 7 is performed. That is, the input image 1
Is input to the encoder 2, and the header information from the encoder 2
The information 3 including the table and the compressed data is transmitted and transmitted to the transfer unit (transmission path) 4. The information 3 is the combiner 5
Then, the composite image 6 is obtained. Where the encoder 2
, DCT, quantization, and entropy coding processing are performed, and in the decompressor 5, entropy decoding, dequantization, I
DCT processing is performed.

The above entropy coding process is realized by the flow shown in FIGS. 8 and 9. That is, in the processing of the DC coefficient, as shown in FIG. 8, the signal in which the DC coefficient is delayed and the DC coefficient are subtracted, the DC differences are grouped, one-dimensional Huffman coding is performed, and the DC code is obtained and added. Sent with bits. On the other hand, AC
In the coefficient processing, as shown in FIG. 9, zigzag scanning is performed, and when it is 0, run length counting is performed. On the other hand, if it is not 0, grouping is performed and 2
Dimensional Huffman coding is performed to obtain an AC code, which is transmitted together with additional bits.

Such image data compression processing has been realized by using a commercially available processor or the like and by a processing control language that is generally available. For example, if the process of converting a DCT coefficient into a Huffman code is to be realized by using C language, which is generally well known, the method described in the above document is used. This processing flow description is converted into a code (machine language) readable by the processor by the compiler and assembler of each system, and the processing is executed.

[0006]

However, in the above-described conventional processing method, the processor has only general-purpose instructions, so that there is a problem in that the above processing takes time. The present invention, in order to eliminate the above-mentioned problems, is provided with a dedicated circuit for converting DCT coefficients into Huffman codes, and the image data coding apparatus capable of significantly reducing the processing time for entropy coding. The purpose is to provide.

[0007]

In order to achieve the above object, the present invention, in an image data coding apparatus for compressing image data, stores DCT coefficients and processing order of the DCT coefficients. Means, a means for sequentially selecting the DCT coefficients according to the processing order of the DCT coefficients, a means for converting the DCT coefficients selected by the selecting means into a Huffman code, and a means required when converting to the Huffman code. And a means for storing the Huffman code table.

[0008]

According to the present invention, in particular, in the process of converting DCT coefficients into Huffman codes, a Huffman code table storage device (10) for exclusively storing the Huffman code table.
5, 106), referring to the Huffman code table to convert the input numerical values into a Huffman coding device (101) and a total of 64 DCT coefficients in what order. And a DCT coefficient transfer device (10) for sending out 64 DCT coefficients to the Huffman coding device (101) according to the order indicated by the processing order storage device (104).
Since 2) is provided, the processing time for entropy coding can be shortened.

[0009]

Embodiments of the present invention will be sequentially described below with reference to the drawings. FIG. 1 is a block diagram of a Huffman code dedicated apparatus in an image data encoding apparatus showing an embodiment of the present invention, and its operation will be described below. In this figure, the DCT coefficient storage device 103 stores 64 pieces of DCT coefficients after DCT (discrete cosine transform) in advance. This is a one-dimensional array of 8 × 8 matrix-like numerical sequences, and the correspondence is shown in FIG. For example, the data in the 5th row and the 6th column is D above.
It is stored at address 46 of the CT coefficient storage device 103.

The DCT coefficients are processed in the order shown in FIG. The DCT coefficient transfer device 102 counts and gives the addresses 202 of the processing order storage device 104 in order from 0 to 63, and at the same time, sequentially receives the data 204 of the processing order storage device 104 corresponding to the addresses, and outputs the numerical values as they are. DCT coefficient storage device 1
It is output as the address 201 of 03.

The data 203 output from the DCT coefficient storage device 103 is as it is, the Huffman coding device 101.
Is output 205. In addition, the output 205 is output via the coefficient number 212 indicating the order of the processing. Up to this point, the data in the DCT coefficient storage device 103 is sequentially sent to the Huffman coding device 101 in the order indicated by the processing order storage device 104.

FIG. 4 is a diagram showing the details of the Huffman coding apparatus. The processing contents differ depending on the value of the coefficient number 212, which will be described. Of the 64 DCT coefficients, the 0th data is the DC component and the remaining 1st to 63rd data is A
It is called C component. (1) When the value of the coefficient number 212 is 0, that is, when the processing is for the DC component, the DCT coefficient 205 and D
The subtractor 302 subtracts the value 402 of the immediately preceding DC component stored in the C register 301, and the difference data 403 is input to the selector (MUX) 307. The MUX 307 selects the data 403 by the control signal 213 and outputs the data 404. Here, in the control signal 213, all the coefficient numbers 212 are “0”.
The detection circuit 305 is a signal indicating whether it is the 0th or the 1st to 63rd.

On the other hand, the data 404 output from the MUX 307 is subjected to grouping processing as shown in FIG. 5 by the grouping circuit 304, and its group number (4 bits) 406 is output. At this time, the run length counter 303 is reset by the control signal 213 indicating that it is the 0th data, and the output 405 of the run length counter 303 is all "0".
It has become.

The merge circuit 309 is for outputting 8-bit data 206 such that the output 405 of the run-length counter 303 is the upper 4 bits and the output 406 of the grouping circuit 304 is the lower 4 bits. The output 206 becomes the address of the DC Huffman code table storage device 105 as it is, and the DC Huffman code table storage device 105 outputs the code data 207 corresponding to the address indicated by the output 206.

At this time, the output 209 of the AC Huffman code table storage device 106 which is another table and the selector (MUX) 107 selects the output (data) by the control signal 213 indicating that it is the 0th. ) 207
Is selected and the code 210 is output. Data 404
Is also converted by the numerical conversion circuit 308 according to the rules shown in FIG. 6 and output as the additional value 214. In addition, at this time, the input DCT coefficient 205 is stored in the DC register 301 in preparation for subtraction processing with the DC component after one.

(2) When the value of the coefficient number 212 is 1 to 63, that is, when the processing is for the AC component, the coefficient number 212 is not the 0th data by the all "0" detection circuit 305. It is output as the control signal 213. When the DCT coefficient 205 is all "0" and the value of the run length counter 303 is not 15, all "0"
The detection circuit 306 outputs the signal to the signal line 401 to indicate this, and the run length counter 303 is counted up.

When the DCT coefficient 205 is not 0 or the value of the run length counter 303 is 15, the value is passed through the MUX 307, the output (data) 404, and the grouping circuit 304 determines the group number. The output 406 is performed according to the rule shown in FIG. In addition, by the output 405 of the run length counter 303 indicating how many times 0 has continued until then, and the merge circuit 309,
It is merged with bit data and output 208. This output 208 is the address of the AC Huffman code table storage device 106, and the code 209 at that time is output from the AC Huffman code table storage device 106 and the code 2
10 is output. Also, the output (data) 404
Is converted by the numerical conversion circuit 308 and output as the additional value 214, as described above.

By configuring as described above, FIG.
The "entropy coding" part of the image data compression processing as shown in (3) can be specialized in hardware, and the entropy coding can be processed at high speed. Further, the present invention is not limited to the above embodiment,
Various modifications are possible based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0019]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the first aspect of the invention, by providing a dedicated circuit for sequentially Huffman coding the DCT coefficients, the processing time for entropy coding can be greatly shortened.

(2) According to the invention described in claim 1, in addition to the effect of the above (1), the processing for entropy coding can be performed quickly and accurately.

[Brief description of drawings]

FIG. 1 is a block diagram of a Huffman code dedicated device in an image data coding device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an array of DCT coefficients in a DCT coefficient storage device in the image data encoding device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a processing order of a processing order storage device in the image data encoding device according to the embodiment of the present invention.

FIG. 4 is a block diagram of a Huffman encoding device in the image data encoding device showing the embodiment of the present invention.

FIG. 5 is a diagram showing the logic of a grouping circuit in the Huffman coding apparatus in the image data coding apparatus showing the embodiment of the present invention.

FIG. 6 is a diagram showing the logic of a numerical conversion circuit in the Huffman coding apparatus in the image data coding apparatus showing the embodiment of the present invention.

FIG. 7 is a diagram showing a hardware image of an algorithm of a conventional color still image encoding method.

FIG. 8 is a diagram showing a hard image of a DC coefficient processing algorithm of entropy coding of a conventional color still image coding system.

FIG. 9 is a diagram showing a hardware image of an AC coefficient processing algorithm of entropy coding of a conventional color still image coding method.

[Explanation of symbols]

 101 Huffman Coding Device 102 DCT Coefficient Transfer Device 103 DCT Coefficient Storage Device 104 Processing Order Storage Device 105 DC Huffman Code Table Storage Device 106 AC Huffman Code Table Storage Device 107, 307 Selector (MUX) 301 DC Register 302 Subtractor 303 303 Run Length counter 304 Grouping circuit 305, 306 All “0” detection circuit 308 Numerical conversion circuit 309 Merge circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H03M 7/40 9382-5K H04N 1/41 B

Claims (2)

[Claims] 1. An image data encoding apparatus for compressing image data, comprising: (a) means for storing DCT coefficients; (b) means for storing the processing order of the DCT coefficients; and (c) the DCT coefficients. According to the processing order of
Means for sequentially selecting CT coefficients, (d) means for converting the DCT coefficients selected by the selecting means into a Huffman code, and (e) storing a Huffman code table necessary for conversion into the Huffman code An image data encoding device comprising means. 2. The image data encoding device according to claim 1, wherein the Huffman code table includes an individual DC Huffman code table and an AC Huffman code table.