JPH0887955A - Electron-emitting device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] An emitter electrode tilted with respect to the gate electrode is formed with high positional accuracy and good reproducibility, and the gate electrode is formed with an extremely small gap length without being restricted by the design rules of the photolithography method. An electron-emitting device is provided, which is arranged in a self-aligned manner with respect to electrodes and has a dramatically expanded selection range of emitter electrode materials. [Structure] A substrate 1, an insulating layer 2 and a gate electrode 3 are sequentially laminated, and an opening A reaching the substrate is provided in the gate electrode 3 and the insulating layer 2. In a field emission electron-emitting device in which the emitter electrode 4 is laminated so as not to contact the gate electrode 3, the inverted cone-shaped recess 1a is formed in the substrate 1, and the emitter electrode 4 is formed along the slope of the recess 1a. The peripheral edge portion 4a is the concave portion 1a of the substrate.
It is formed so as to protrude from the upper edge of the. Further, when forming the emitter electrode 4, protective layers are provided on both surfaces thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron-emitting device which emits electrons by a strong electric field and a method for manufacturing the same. More specifically, as an electron source or electron gun of an optical printer, an electron microscope, an electron beam exposure apparatus, or the like, or as an ultra-small illumination source of an illumination lamp, in particular, an array-shaped FEA (Field E) that constitutes a flat display.
The present invention relates to an electron-emitting device useful as an electron generation source of a mitter array) and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy in order to emit thermoelectrons from the cathode of an electron gun, and has a large structure. There was a problem such as requiring a volume.

For this reason, there has been a demand for a flat-panel display in which cold electrons, rather than hot electrons, can be used to reduce energy consumption as a whole and the device itself is miniaturized. It is also strongly required to realize high-speed response and high resolution in such a flat panel display.

As a structure of such a flat-type display utilizing cold electrons, it is considered promising to arrange minute electron-emitting devices in an array in a high vacuum flat plate cell. And as an electron-emitting device used for that,
A field emission type electron-emitting device utilizing the field emission phenomenon has been attracting attention. In this field emission type electron-emitting device, when the intensity of the electric field applied to the substance is increased, the width of the energy barrier on the surface of the substance is gradually narrowed according to the intensity, and the electric field intensity becomes a strong electric field of 10 ⁷ V / cm or more. Then, the phenomenon that electrons in the substance can break through the energy barrier due to the tunnel effect and the electron is emitted from the substance is used. In this case, since the electric field follows Poisson's equation, if a portion where the electric field is concentrated is formed in a member (emitter electrode) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.

As a general example of such a field emission type electron-emitting device, a cone-type electron-emitting device having a sharp tip as shown in FIG. 6A can be exemplified. In this element, an insulating layer 62 and a gate electrode 63 are sequentially stacked on a conductive layer 61.
2 and the gate electrode 63, an opening 64 reaching the conductive layer 61 is formed. Then, a conical shape (cone type) having point projections Po on the conductive layer 61 in the opening 64 so as not to contact at least the gate electrode 63.
An emitter electrode 65 is formed. In this case, in order to further improve the electron emission efficiency, the surface of the gate electrode 63 is located at a position higher than the point projections Po of the cone-shaped emitter electrode 65. In such an electron-emitting device, the voltage applied to the emitter electrode 65 is efficiently concentrated on the point-like projections Po, so that cold electrons can be emitted at a relatively low applied voltage.

However, when an electron-emitting device having a cone-type emitter electrode as shown in FIG. 6A is applied to an FEA used for a large-area flat display, the inside of the opening 64 having a diameter of 1 μm or less. In addition, it is desired that a large number of emitter electrodes 65 having point projections Po having a radius of curvature of several hundreds nm or less be uniformly formed without variation while keeping the relative positional relationship with the gate electrode 63 constant. However, in practice, there is a problem that it is very difficult to form such a structure.

Therefore, as shown in FIG. 6 (b), the disk-shaped emitter electrode (disk-shaped emitter electrode) 65 having a good uniform workability is used without forming the cone-shaped emitter electrode.
Is proposed. In the disk-shaped emitter electrode 65, the electric field is concentrated on the ring-shaped peripheral edge Pe of the emitter electrode 65 which is the boundary line between the emitter electrode surface 65a and the emitter electrode peripheral surface 65b, and cold electrons are emitted from the electric field. An emitter electrode base layer 66 is generally formed between the emitter electrode 65 and the conductive layer 61. It is preferable that the emitter electrode base layer 66 has a diameter smaller than the diameter of the emitter electrode 65 so that the electric field is easily concentrated on the peripheral edge Pe of the disk-shaped emitter electrode 65. The base layer 66 is usually formed of a material that is more easily etched than the emitter electrode 65.

However, in the case of an electron-emitting device having a disk-type emitter electrode as shown in FIG. 6B, the ring-shaped peripheral edge Pe on which the electric field is concentrated has the gate electrode 6 formed therein.
Of the emitter electrode surface 65a parallel to the main surface of the substrate 3 and the substrate 61.
6C, the direction x of Pe is parallel to the vertical direction of the substrate 61 and the main surface of the gate electrode 63, as shown in FIG. 6C. On the other hand, they are inclined at 45 °. Therefore, there is a problem described below.

That is, in order to utilize the electrons emitted from the emitter electrode, it is necessary to prevent them from being trapped by the gate electrode. For that purpose, a ring-shaped peripheral edge P
It is desired that the direction x of e be close to the vertical direction of the substrate. However, in the case of the element as shown in FIG. 6B, electrons are emitted from the emitter electrode 65 at a direction of 45 ° with respect to the main surface direction of the gate electrode 63, so that electrons trapped in the gate electrode 63 are generated. Since the ratio becomes large and the ratio (distribution ratio) of the electrons emitted from the inside of the element to the outside becomes relatively low, there is a problem that the function as an electron generation source is insufficient.

In order to solve this problem, the technique disclosed in Japanese Patent Laid-Open No. 4-87135 or Japanese Patent Laid-Open No. 206123 is a technique for making the direction of the ring-shaped peripheral edge Pe of the disk type emitter electrode closer to the vertical direction of the substrate. There is.

According to Japanese Unexamined Patent Publication No. 4-87135, first, as shown in FIG. 7A, a disk-shaped emitter electrode 65 is formed on a conductive layer 61 so that its peripheral portion is in an overhang state. The insulating layer 62 and the gate electrode 63 are formed on the periphery thereof at an ambient temperature of 100 ° C. or higher. Then, the ambient temperature is returned to normal temperature. Then, due to the difference in the coefficient of thermal expansion between the conductive layer 61 and the emitter electrode 65, the peripheral edge portion 65c of the emitter electrode 65 is naturally turned up (FIG. 7).
(B)). By utilizing this phenomenon, FIG.
As shown in, the direction x of the ring-shaped peripheral edge Pe of the emitter electrode 65 can be made closer to the vertical direction of the conductive layer 61.

Further, according to Japanese Patent Laid-Open No. 4-206123, first, as shown in FIG.
A conductive layer 61 is partially formed on the upper surface of the conductive layer 61, and the periphery thereof is tapered to form an insulating layer 62. Further, a metal material thin film layer 68 for a gate electrode and an emitter electrode is laminated on the entire surface. Next, a resist layer 69 is selectively formed on portions of the metal material thin film layer 68 corresponding to the gate electrode and the emitter electrode, and the metal material thin film layer 6 is used as a mask.
8 is etched, and the insulating layer 62 is overetched (FIG. 8B). As a result, the emitter electrode 65 having the peripheral edge portion 65c raised toward the gate electrode 63 is formed. Therefore, as shown in FIG. 8C, the direction x of the ring-shaped peripheral edge Pe of the emitter electrode 65 can be brought close to the vertical direction of the substrate 67.

[0013]

However, in the case of FIG. 7, the curling up of the peripheral edge portion 65c of the emitter electrode 65 depends on the difference in the coefficient of thermal expansion between the conductive layer 61 and the emitter electrode 65. However, there is a problem in that the reproducibility of the degree of curling up is extremely poor, and the geometrical positional accuracy of the electric field concentrated portion cannot be improved. Therefore, it is practically impossible to apply the technique described in Japanese Patent Application Laid-Open No. 4-87135 to a case where a large number of electron-emitting devices having emitter electrodes having constant characteristics are integrated.

Further, as a constituent material of the conductive layer 61 and the emitter electrode 65, it is necessary to select a combination having a large difference in thermal conductivity between the two, which restricts material selection.

On the other hand, the structure of the electron-emitting device shown in FIG. 8 has a problem that the emitter electrode 65 cannot be formed in a positionally definite manner and the gate electrode 63 cannot be formed in a self-aligned manner. That is, for the gate electrode 63 and the emitter electrode 65 of the electron-emitting device of FIG. 8, a resist layer 69 is selectively formed on the metal material thin film layer 68, and the resist layer is used as an etching mask to form the metal material thin film layer 6
Since the gate electrodes 63 and the emitter electrodes 65 are formed at the same time by etching 8, the relative positional accuracy of the gate electrode 63 and the emitter electrode 65 is determined by the resist layer patterning accuracy (mask accuracy, mask accuracy,
There is a problem that cumulative precision errors such as exposure precision, resist layer removal precision, etc.) and etching precision are included.
Therefore, the gap between the gate electrode 63 and the emitter electrode 65 is not constant, and the gap length must depend on the design rule of the photolithography method, and the gap length is made smaller than the design rule. There was a problem that it was difficult to improve the function of.

Therefore, the electron-emitting device shown in FIGS.
It was unsuitable as an ultra-fine electron-emitting device used for EA.

Further, in general, there is a strong demand for finer electron-emitting devices. Therefore, a silicon substrate is used as a substrate of the electron-emitting devices or a conductive layer so that the method of forming a semiconductor chip can be applied. Attempted to use.

As a method for efficiently etching a silicon substrate, RIE using a fluorine-based gas such as SF ₆ is used.
Dry etching is considered. Therefore, when the emitter electrode is formed on the silicon substrate and then the substrate is etched, such an RIE is used as the emitter electrode.
It is necessary to use a material resistant to etching, namely Cr.

However, since a natural oxide film that hinders the emission of electrons is likely to be formed on the surface of Cr, there is a problem that the operating voltage is likely to increase. In addition, since the thermal conductivity of Cr is low, heat conduction in the electric field concentration portion of the emitter electrode is delayed, and the temperature of the emitter electrode excessively rises locally, resulting in destruction of the electron-emitting device. Occurs. Therefore, even when a silicon substrate is used as a substrate and RIE dry etching using a fluorine-based gas is performed on the substrate after the emitter electrode is formed on the substrate, the emitter electrode can be made of a material other than Cr. It is strongly desired to do so.

The present invention is intended to solve the above-mentioned problems of the prior art. The emitter electrode serves as the gate electrode so that the direction of the ring-shaped peripheral edge of the emitter electrode becomes closer to the vertical direction of the substrate. In contrast, it is formed with high positional accuracy and with good reproducibility, and has a very small gap length without being restricted by the design rules of the photolithography method, and the gate electrode is self-aligned with the emitter electrode. An object of the present invention is to provide an electron-emitting device that has a structure that can be arranged and that has a wide range of material selection for the emitter electrode.

[0021]

The present inventor (1) forms an inverted cone-shaped recess such as an inverted cone or an inverted regular quadrangular pyramid on a substrate and forms an emitter electrode along the recess. This makes it possible to form an emitter electrode that is highly reproducibly tilted with respect to the gate electrode and (2) isotropically etches the substrate using the emitter electrode as a mask so that the peripheral edge of the etching is projected from the recess. If an insulating layer and a gate electrode are sequentially stacked on top of it by a vapor deposition method and both layers stacked on the emitter electrode are lifted off, the gate electrode does not come into contact with the emitter electrode and the gap length is extremely small and uniform. (3) In this case, the insulating layer laminated on the emitter electrode whose whole surface is inclined is compared with the insulating layer laminated on the flat substrate. (4) Further, when the emitter electrode is formed, both surfaces thereof are covered with a protective layer, and finally the protective layer on at least both surfaces of the electron emitting portion of the emitter electrode is removed so that the material of the emitter electrode is formed. The inventors have found that the range of choices is widened, and (5) that the above objects can be achieved by combining these, and have completed the present invention.

That is, according to the present invention, a substrate, an insulating layer and a gate electrode are sequentially laminated, an opening portion reaching the substrate is provided in the gate electrode and the insulating layer, and an emitter is formed on the substrate in the opening portion. In a field emission type electron-emitting device in which an electrode is formed so as not to contact the gate electrode, an inverted cone-shaped recess is formed in a substrate, and an emitter electrode is formed along the slope of the recess. Provided is an electron-emitting device characterized in that a peripheral edge portion of an electrode projects from an upper edge portion of a concave portion of a substrate, and a lower protective layer is formed between an emitter electrode and the substrate.

The present invention also provides the above-described method for manufacturing an electron-emitting device, including the step of: (a) forming an insulating layer on a substrate, forming a resist layer thereon, and patterning the resist layer; (B) A step of etching the insulating layer using the patterned resist layer as a mask until the substrate is exposed; (c) A resist layer is removed, and the substrate is further etched using the insulating layer as a mask to form a conical recess. On the substrate; (d) a lower protective layer material thin film layer, an emitter electrode material thin film layer, and an upper layer protective layer on the recess side of the substrate so that the emitter electrode is formed along the slope of the recess of the substrate. A step of sequentially forming a layer material thin film layer; (e) an insulating layer is lifted together with a lower protective layer material thin film layer, an emitter electrode material thin film layer, and an upper protective layer material thin film layer formed thereon. And then patterning the lower protective layer, the emitter electrode and the upper protective layer; (f) etching the substrate so that the peripheral portions of the lower protective layer, the emitter electrode and the upper protective layer protrude from the upper edge of the concave portion of the substrate. (G) a step of etching away the upper protective layer and etching away the peripheral edge of the lower protective layer; (h) newly laminating an insulating layer on the concave side of the substrate, and further laminating a gate electrode material thin film. And; (i) Lifting off the insulating layer newly formed on the emitter electrode together with the gate electrode material thin film layer thereon,
There is provided a manufacturing method comprising a step of forming a gate electrode surrounding the emitter electrode without contacting the emitter electrode.

The present invention will be described in detail below with reference to the drawings.

First, FIG. 1 shows a sectional view of the electron-emitting device of the present invention. As shown in the figure, in the electron-emitting device of the present invention, a substrate 1, an insulating layer 2 and a gate electrode 3 are sequentially laminated, and an opening A reaching the substrate 1 is formed in the gate electrode 3 and the insulating layer 2. Is provided, an inverted cone-shaped recess 1a is formed in the substrate 1 in the opening A, and the emitter electrode 4 is formed so as not to contact the gate electrode 3 along the slope of the recess 1a. Edge 4a of the emitter electrode 4
Are formed so as to protrude from the upper edge portion 1b of the concave portion 1a of the substrate 1. In addition, the emitter electrode 4 and the concave portion 1a of the substrate
The lower protective layer 5 is provided between the and.

In the present invention, the substrate 1 functions as a support for the electron-emitting device. As such a substrate 1, an inverted cone-shaped concave portion 1a such as an inverted cone or an inverted regular square pyramid is used.
Although there is no particular limitation as long as it can form a single crystal silicon substrate, it is particularly preferable to use a single crystal silicon substrate having a (100) plane-oriented main surface. The reason for this is that such a single crystal silicon substrate can be anisotropically etched with an alkali metal hydroxide aqueous solution, and as a result, an inverted regular quadrangular pyramid-shaped concave portion composed of a slope having a (111) plane orientation can be formed. . In this case, if the central angle of the concave portion 1a is 2θ, the angle θ can be about 55 °. On the other hand, since the peripheral side surface 4b of the emitter electrode 4 is in the vertical direction of the substrate 1, the direction x of the peripheral edge Pe of the emitter electrode 4 is inclined by 27.5 ° (= 55 ° / 2) from the vertical direction of the substrate 1. It will be facing. Therefore, the ratio of the electrons emitted from the peripheral edge Pe of the emitter electrode 4 captured by the gate electrode 3 can be reduced.

The insulating layer 2 is a layer for electrically insulating the substrate 1 and the gate electrode 3 from each other, and is also a layer defining the gap width between the gate electrode 3 and the emitter electrode 4. Such an insulating layer 2 can be formed of a known material used as an insulating layer of an electron-emitting device.
In particular, a silicon oxide film is preferable because it can be easily lifted off by buffered hydrofluoric acid. In addition, the thickness of the insulating layer 2 is set to the emitter electrode 4 and the gate electrode 3.
The thickness may be a thickness that realizes a preferable relative positional relationship with, for example, 0.2 to 2 μm, preferably 0.5 to 1 μm.
m.

The gate electrode 3 is an electrode for concentrating a strong electric field on the emitter electrode 4. As the material of the gate electrode 3, a metal, a nitride or a carbide thereof, a semiconductor, a metal compound of a semiconductor, for example, Cr, Zr, Hf, Cu, W,
It can be appropriately selected from simple substances such as Mn, Fe, Ni, Nd, Mo, Ta, Nb, and Ti, their silicon compounds, nitrides, carbides, and the like, but from the viewpoint of current resistance, refractory metal, Particularly, Cr, W, Mo, Ta and Nb can be preferably exemplified. Especially, it is preferable to use Nb.

The thickness of the gate electrode 3 can be appropriately determined according to need, but is preferably about 0.1 to 0.2 μm.

The emitter electrode 4 functions as a member that directly emits electrons from its surface. As a material of such an emitter electrode 4, a material having a small work function, good electron emission characteristics, high voltage resistance, and a high melting point is used. Basically, such a material can be appropriately selected from the group of materials that can be used as the gate electrode 3, but as will be described later, the resistance to the lift-off condition at the time of forming the emitter electrode 4 and the current withstanding point. Therefore, Cr, W, Mo, Ta and Nb can be preferably exemplified. Among them, W, Mo, Ta, Nb other than Cr
Is preferably used.

The thickness of the emitter electrode 4 can be appropriately determined if necessary, but is usually 0.05 to 0.5 μm.
It is preferable that

In the present invention, the peripheral edge portion 4a of the emitter electrode is formed so as to protrude from the upper edge portion 1b of the concave portion 1a of the substrate 1, whereby the electric field is more concentrated in the peripheral edge portion 4a and the voltage is reduced at a lower voltage. It becomes possible to emit electrons. This forming method will be described in detail in the description of the manufacturing method of the present invention described later.

The lower protective layer 5 is formed on the substrate 1 when the substrate 1 is etched so that the peripheral edge 4a of the emitter electrode protrudes from the upper edge 1b of the recess 1a of the substrate 1, as will be described later.
This is for protecting the emitter electrode 4 from the ion species incident on the emitter electrode 4 from the side. Such a lower protective layer 5 can be selected from various materials according to the type of material of the substrate 1 and processing conditions such as dry etching. For example, when a silicon substrate is used as the substrate 1 and RIE etching with a fluorine-based gas such as SF ₆ is performed, Cr can be particularly preferably used as the lower protective layer 5.

The layer thickness of the lower protective layer 5 is not particularly limited as long as it can protect the emitter electrode 4, but is usually 0.01.
To 0.2 μm, preferably 0.05 to 0.1 μm.

The cross-sectional shape of the emitter electrode 4 is shown in FIG.
However, it is preferable that the shape projected onto the plan view is a point-symmetrical shape, for example, a circular shape or a square shape, in order to obtain stable electron emission characteristics.

In particular, when the plane projection shape of the emitter electrode is circular, it is possible to prevent an excessively sharp edge portion from being formed on the peripheral edge Pe of the emitter electrode 4 and to improve the operational stability of the device. preferable. Such an emitter electrode is, for example, an emitter electrode formed in an inverted regular pyramid-shaped recess, and its plan view projected shape is circular as shown in FIG. 2 (a), and its perspective shape is As shown in FIG. 2 (b), one having a shape of four petal aggregates can be mentioned.

On the other hand, in the present invention, if necessary,
A sharp edge portion can be provided on the peripheral portion of the emitter electrode. In this case, since the electric field can be efficiently concentrated on the edge portion, the operating voltage of the electron-emitting device can be reduced. As such an emitter electrode, for example, an emitter electrode formed in a recess of an inverse regular quadrangular pyramid shape, and its plan view projected shape is as shown in FIG.
2 is a square, and its perspective shape is shown in FIG.
As shown in (d), a star-shaped one can be mentioned.

From the viewpoint of emission characteristics, it is preferable that the level of the upper end (peripheral edge Pe) of the peripheral edge portion 4a of the emitter electrode 4 does not exceed the upper surface level of the gate electrode 3.

Next, in the method for manufacturing an electron-emitting device of the present invention, a single crystal silicon substrate having a (100) plane main surface is used as a substrate, and an inverted regular quadrangular pyramid-shaped recess is formed in the substrate, and further, A detailed description will be given with reference to FIGS. 3 and 4, taking as an example the case where the emitter electrode is formed so that the projected shape of the emitter is circular.

Step (a) First, as shown in FIG. 3A, an insulating layer 6 is formed on a substrate 1, a resist is applied on the insulating layer 6, and patterning is performed to form a resist layer 7. In this case, a silicon oxide film formed by a thermal oxidation method can be preferably used as the insulating layer 6.

As the material of the resist layer 7 and its patterning method, known resist materials and patterning methods can be applied. For example, as shown in the plan view of FIG. The resist layer 7 can be formed by an ordinary photolithographic method.

Step (b) Next, the insulating layer 6 is etched using the patterned resist layer 7 as a mask until the substrate 1 is exposed in a circular shape (FIG. 3 (b)). In this case, when a silicon oxide film is used as the insulating layer 6, buffer hydrofluoric acid (BHF) can be preferably used as an etchant.

Step (c) Next, the resist layer 7 is removed, and the substrate 1 is etched using the insulating layer 6 as a mask to form the recess 1a in the substrate 1 (FIG. 3C). In this case, when the substrate 1 is a single crystal silicon substrate having a (100) plane orientation, the insulating layer 6 is formed by using an alkali metal hydroxide aqueous solution such as KOH or NaOH as an etchant.
The etching can be stopped at the (111) plane regardless of the planar shape of the (etching mask), and as a result, as shown in FIG.
As shown in (c), an inverted quadrangular pyramid-shaped recess 1a can be formed. When the alkali metal hydroxide aqueous solution is used as the etchant, the inclination .theta. Of the inner surface of the concave portion 1a is always about 55.degree., So that the concave portion 1a always has a constant shape.
Also, the emitter electrode formed on the slope of is also inclined with good reproducibility.

Step (d) Next, the lower protective layer material thin film 9, the emitter electrode material thin film 10 and the upper protective layer material thin film 11 are formed in this order on the concave portion 1a side of the substrate 1 in this order by vacuum deposition or sputtering. It is laminated by a usual vapor deposition method such as. These thin films form the lower protective layer 5, the emitter electrode 4, and the upper protective layer 8 on the concave portion 1a of the substrate 1 (FIG. 3D).

Here, the upper protective layer 8 is similar to the lower protective layer 5 already described, and the peripheral edge portion 4a of the emitter electrode and the upper edge portion 1b of the concave portion 1a of the substrate 1 are subjected to the step (f) described later.
This is for protecting the emitter electrode 4 from the ion species incident on the emitter electrode 4 from the front surface side of the substrate 1 when the substrate 1 is etched so as to protrude from. Such an upper protective layer 8 can be selected from various materials according to the type of material of the substrate 1 and processing conditions such as dry etching. For example, when a silicon substrate is used as the substrate 1 and RIE etching with a fluorine-based gas such as SF ₆ is performed, Cr can be particularly preferably used as the upper protective layer 8.

The layer thickness of the upper protective layer 8 is usually 0.05 to 1.
μm, preferably 0.1 to 0.5 μm, and the layer thickness of the lower protective layer 5 is usually 0.01 to 0.2 μm, preferably 0.0
5 to 0.1 μm, the thickness of the emitter electrode 4 is usually 0.0
The thickness is 5 to 0.2 μm, preferably 0.1 to 0.3 μm.

As described above, since the emitter electrode 4 is protected by the lower protective layer 5 and the upper protective layer 8, a silicon substrate is used as the substrate 1 and RIE etching using a fluorine-based gas is performed in a later step. Even in this case, the emitter electrode 4 can be made of a material that is originally etched under such etching conditions, for example, Nb, and the range of material selection can be increased.

In this step, the insulating layer 6 around the recess 1a is formed.
The lower protective layer material thin film 9, the emitter electrode material thin film 10 and the upper protective layer material thin film 11 are also formed on the upper surface,
The thickness of each thin film is set so as not to be continuous with the layers corresponding to those layers laminated on the concave portion 1a of the substrate 1 and to be in a step-break state. For example, if the material thin film 9 for the lower protective layer is 0.
The thickness of the emitter electrode material thin film 10 is about 0.05 to 0.5 μm, and the thickness of the upper protective layer material thin film 11 is about 0.05 to 1 μm. The reason why the step is cut off is that the insulating layer 6 is formed in the next step.
This is because it can be easily lifted off.

Step (e) Next, the insulating layer 6 is lifted off together with the lower protective layer material thin film 9, the emitter electrode material thin film layer 10 and the upper protective layer material thin film 11 formed thereon, and the insulating layer 6 is lifted off. Recess 1
The lower protective layer 5, the emitter electrode 4, and the upper protective layer 8 are left along the slope of a (FIG. 3E). When the insulating layer 6 is a silicon oxide film, it can be easily lifted off by buffered hydrofluoric acid.

Step (f) Next, the upper protective layer 8 and the lower protective layer 5 are not etched, but the substrate 1 is anisotropically etched using an etchant capable of etching the exposed substrate 1 (FIG. 4).
(F)). At this time, the substrate 1 located below the peripheral edge 4a of the emitter electrode 4 is side-etched. Then, the peripheral edge portion 8a of the upper protective layer 8, the peripheral edge portion 4a of the emitter electrode 4, and the peripheral edge portion 5a of the lower protective layer 5 project from the upper edge portion 1b of the concave portion 1a of the substrate 1.

As an etching method in this case, when a silicon substrate is used as the substrate 1 and Cr is used as the upper protective layer 8 and the lower protective layer 5, reactive ion etching using SF ₆ gas as an etchant is used. It can be preferably performed. At this time, as the emitter electrode 4,
Even if Nb or the like that would be etched under such etching conditions is used, the peripheral surface can be slightly side-etched.

Step (g) Next, at least peripheral portions of the upper protective layer 8 and the lower protective layer 5 are removed by etching (FIG. 4 (g)). In this case, the upper protective layer 8 may be completely removed, but the lower protective layer 5
For supporting the emitter electrode 4 (recess 1
Etching is performed so as to leave a portion in contact with a).

By the way, if the lower protective layer 5 is a flat film, if the emitter electrode 4 is used as an etching mask to perform isotropic wet etching, a structure in which the lower protective layer 5 remains only on the concave portion 1a of the substrate 1 can be easily obtained. can get. However, in the electron-emitting device of the present invention, the upper protective layer 8, the emitter electrode 4, and the lower protective layer 5 form an inclined surface with respect to the surface of the substrate 1. Therefore, the lower protective layer 5 is significantly side-etched even if it is covered with the emitter electrode 4. In particular, under isotropic wet etching conditions, the lower protective layer 5 is removed by etching in a short time, resulting in lift-off of the emitter electrode 4. Therefore, anisotropic etching is preferred in this step.
For example, when the substrate 1 is a silicon substrate, the upper protective layer 8 and the lower protective layer 5 are Cr, and the emitter electrode 4 is Nb, first, RIE dry etching using a chlorine-based gas is performed. Specifically, chlorine-based gas (flow rate: about 50 to 10
0 sccm / for example, chloroform) and its 0.5-2
A double flow rate of oxygen gas was introduced into the device, and relatively low power (50 to 150 W) and low gas pressure (0.1 to 0.3 T).
The etching can be performed under the condition of (orr).

At the end of such etching, the upper protective layer 8 may be slightly recognized as a residue on the emitter electrode 4, but it is substantially removed. Further, as the emitter electrode 4 is etched, the portion where the lower protective layer 5 is projected from the emitter electrode 4 is also removed.

Furthermore, after this anisotropic etching, light wet etching can be performed. In this case, for example, a normal acidic cerium nitrate-based etching solution can be preferably used as the etching solution. This wet etching may be a light treatment such as rinsing, and a treatment of about 1 to 2 minutes is sufficient in terms of time. By such wet etching, the residue due to the anisotropic etching described above can be completely removed, and further, the removal of the portion of the lower protective layer 5 exposed from the silicon substrate 1 is completed.

Step (h) Next, an insulating layer 12 is newly laminated on the concave portion 1a side of the substrate 1, and a gate electrode material thin film 13 is further laminated by a conventional method. As a result, the insulating layer 2 and the gate electrode 3 can be stacked around the emitter electrode 4 in a self-aligned manner while maintaining a small gap (FIG. 4 (h)). Therefore, the relative position between the emitter electrode 4 and the gate electrode 3 can be controlled with high accuracy without being affected by the accumulated error of the mask pattern forming technique or the photolithographic technique, and especially when a large number of elements are Even when they are integrated and formed, the positional accuracy between the emitter electrode 4 and the gate electrode 3 in each element can be made substantially the same.

Step (i) Finally, the insulating layer 12 on the emitter electrode 4 is lifted off together with the gate electrode material thin film 13 thereon so as to surround the emitter electrode 4 without contacting it.
Are formed (FIG. 4 (i)). As a lift-off method in this case, for example, when a silicon substrate is used as the base material 1 and a silicon oxide film is used as the insulating layer 12, light etching is performed with buffered hydrofluoric acid to remove Cr.
The insulating layer 2 on the buffered hydrofluoric acid-resistant emitter electrode 4 can be lifted off together with the gate electrode material thin film 13 thereon. This utilizes the property that the silicon oxide film deposited on the slope is more easily etched than the silicon oxide film deposited on the flat surface.

Thereafter, if necessary, the gate electrode 3 may be patterned into an effective gate portion surrounding the emitter electrode 4 and a wiring portion for electrically connecting the effective gate portion from an external power source.

3 and 4, the resist layer 7 has a circular opening pattern, the insulating layer 6 is etched, and the insulating layer 6 is used as a vapor deposition mask. This is an example of forming a petal-shaped emitter electrode 4 as shown in the figure. As shown in FIG. 5, the opening pattern A of the resist layer 7 is a square having a side parallel to the (011) plane direction of the silicon substrate. Then, the star-shaped emitter electrode 4 as shown in FIG. 2D can be formed. As described above, it is possible to form a large number of edges, which serve as electric field concentration points, on the peripheral portion of the emitter electrode 4 depending on the opening pattern of the resist layer 7.

[0060]

In the electron-emitting device of the present invention, the emitter electrode is provided along the slope of the inverted pyramidal recess of the substrate,
Moreover, the emitter electrode has a shape protruding obliquely above the base substrate. The emitter electrode having such a shape is surrounded by the gate electrode with a slight gap. Therefore, the emitter electrode is inclined with respect to the gate electrode, and the peripheral edge P of the emitter electrode is
The direction x of e approaches the direction perpendicular to the substrate. Therefore, the probability that electrons emitted from the emitter electrode due to the gate electrode voltage are trapped in the gate electrode can be made extremely small, and the distribution ratio of the electrons emitted to the outside of the device can be significantly improved.

In particular, in the present invention, when a single crystal silicon substrate whose main surface has a (100) plane orientation is used as the substrate, a silicon oxide film can be easily formed as an insulating layer. Anisotropic etching with an aqueous solution of alkali metal hydroxide using the film as an etching mask creates an inverted quadrangular pyramid whose base is a rectangle (rectangle or square) circumscribing the opening pattern shape of the mask regardless of the shape of the etching mask. It is preferable because recesses are obtained.

At this time, since the emitter electrode is formed by using the etching mask made of this silicon oxide film as a vapor deposition mask, the emitter can be formed in various shapes according to the shape of the etching mask.

Further, the emitter electrode is previously covered with a protective layer at the upper and lower sides in the step of processing (mainly RIE) so that the peripheral edge of the emitter electrode protrudes from the concave portion of the substrate. Therefore, it becomes possible to form the emitter electrode from a material having no RIE resistance. Therefore, the selection range of the emitter electrode material is dramatically expanded, and it becomes possible to obtain an electron-emitting device having excellent characteristics.

[0064]

EXAMPLES A production example of the electron-emitting device of the present invention will be specifically described in the following examples.

Example As shown in FIG. 3A, the plane orientation (10
0) a silicon substrate is prepared, and a silicon oxide film (S) having a thickness of about 0.3 μm is formed on the silicon substrate 1 by a thermal oxidation method.
iO ₂ film) was formed. A resist layer (OFPR8600, Tokyo Ohka Kogyo Co., Ltd.) having a circular opening pattern with a diameter of 6 μm was formed thereon by a photolithographic method.

Using this patterned resist layer as a mask, buffer hydrofluoric acid (ammonium fluoride / hydrofluoric acid = 9 /
According to 1), the silicon oxide film was etched until the silicon substrate was exposed as shown in FIG.

After that, the resist layer was removed, and the silicon substrate was anisotropically etched with a 30% potassium hydroxide (KOH) aqueous solution. Thereby, as shown in FIG. 3C, an inverted pyramid-shaped recess was formed.

Next, as shown in FIG. 3D, with the silicon oxide film around the concave portion of the substrate remaining, Cr as the material for the lower protective layer was vapor-deposited to a thickness of 0.05 μm, and then Cr was deposited thereon. Then, Nb as a material for the emitter electrode was vapor-deposited to a thickness of about 0.2 μm, and then Cr as a material for the upper protective layer was vapor-deposited to a thickness of 0.1 μm. At this time, the Nb layer (emitter electrode) formed on the inner surface of the recess of the substrate and the Nb thin film formed on the silicon oxide film around the recess of the substrate were discontinuous, and both were discontinuous. .

After that, as shown in FIG. 3E, the silicon oxide film around the concave portion of the substrate is formed on the Cr film formed thereon.
The film was lifted off together with the thin film / Nb thin film / Cr thin film by buffered hydrofluoric acid.

Further, as shown in FIG. 4F, the substrate was removed by etching by about 0.5 μm by reactive ion etching using SF ₆ gas. At this time, Cr (lower protective layer) / Nb (emitter electrode) on the inner surface of the recess
Among Cr / Cr (upper protective layer), the Cr thin films of the lower protective layer and the upper protective layer were not etched because they had RIE resistance due to the fluorine-based gas. Therefore, these protective layers functioned as an etching protective layer for the emitter electrode. Therefore, the Nb thin film of the emitter electrode was slightly side-etched. On the other hand, the silicon substrate under the emitter electrode was side-etched, and as a result, the emitter electrode was in a state of slightly protruding from the upper edge of the recess of the substrate.

Next, as shown in FIG. 4 (g), the upper protective layer and the lower protective layer were subjected to the RIE method (introduced gas: chloroform (75 sccm) and oxygen (75 sccm) / power 1).
The etching was performed for 15 minutes at 0 W / gas pressure of 0.2 Torr). Then, wet etching was performed by immersing in a cerium nitrate-based etching solution at 25 ° C. for 1 minute. As a result, the upper protective layer was completely removed and the peripheral portion of the lower protective layer was removed.

Thereafter, as shown in FIG. 4H, a silicon oxide film (SiO or SiO ₂ ) having a thickness of about 0.5 μm is vapor-deposited as an insulating layer, and Nb of the gate electrode material is further deposited thereon. It was deposited to a thickness of 0.3 μm. As a result, the insulating layer located around the emitter electrode and the Nb thin film (gate electrode) could be formed with a slight gap from the emitter electrode without contacting the emitter electrode. Therefore, the gate electrode can be formed in a self-aligned manner with respect to the emitter electrode having the side surface facing the gate electrode.

Next, the insulating layer attached on the emitter electrode was lifted off together with the Nb thin film thereon by buffered hydrofluoric acid. As a result, the electron-emitting device shown in FIG. 4 (i) was obtained.

An array in which 200 electron-emitting devices described above were integrated was manufactured as a prototype and tested and evaluated as follows. That is, the distance between the emitter electrode and the gate electrode of each element is about 0.3 μm.
A glass plate member having a transparent electrode (anode) coated with a phosphor is opposed to the device having the structure described above at a distance of 30 mm, and an extraction voltage of 120 V is applied between the emitter electrode and the gate electrode with a positive polarity on the gate electrode side. As a result, an anode current of about 10 μA flowed with respect to the supplied emitter current of 12 μA, and the distribution rate was about 85%. These values were excellent values of 10 times or more for each current value and distribution rate as compared with the typical values of the conventional electron-emitting device shown in FIG. 6B.

[0075]

According to the electron-emitting device of the present invention, the direction of the peripheral edge of the emitter electrode approaches the vertical direction of the substrate,
The emitter electrode is inclined with respect to the gate electrode,
Moreover, its position accuracy and reproducibility are high. Further, the gate electrode is arranged in a self-aligned manner with the emitter electrode with an extremely small gap length without being restricted by the design rule of the photolithography method. Moreover, RIE
The emitter electrode can be made of a material having no resistance, so that the selection range of the emitter electrode material is dramatically expanded, and the electron-emitting device has excellent characteristics.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an electron-emitting device of the present invention.

FIG. 2 is a plan view ((a) and (c) of the same figure) and a perspective view ((b) and (d) of the same figure) of an emitter electrode.

FIG. 3 is a manufacturing process diagram of an electron-emitting device of the present invention.

FIG. 4 is a manufacturing process diagram of the electron-emitting device of the present invention.

FIG. 5 is an explanatory diagram of an opening pattern of a resist layer.

FIG. 6 is a schematic sectional view of a conventional electron-emitting device.

FIG. 7 is a manufacturing explanatory diagram of a conventional electron-emitting device.

FIG. 8 is a manufacturing explanatory diagram of a conventional electron-emitting device.

[Explanation of symbols]

 1 substrate 2 insulating layer 3 gate electrode 4 emitter electrode 5 lower protective layer 6 insulating layer 7 resist layer 8 upper protective layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masago Kanamaru 1-4-1 Umezono, Tsukuba-shi, Ibaraki Electronic Technology Research Institute, Institute of Industrial Technology (72) Inujita Ito 1-4-1, Umezono, Tsukuba-shi, Ibaraki (72) Inventor Mamoru Ishizaki 1-5-1 Taito, Taito-ku, Tokyo Inside Toppan Printing Co., Ltd.

Claims (12)

[Claims] 1. A substrate, an insulating layer and a gate electrode are sequentially laminated, and an opening reaching the substrate is provided in the gate electrode and the insulating layer, and an emitter electrode is formed on the substrate in the opening. In a field emission type electron-emitting device formed so as not to contact the gate electrode, an inverted cone-shaped recess is formed in the substrate, an emitter electrode is formed along the slope of the recess, and a peripheral edge of the emitter electrode is formed. Is protruding from the upper edge of the concave portion of the substrate, and a lower protective layer is formed between the emitter electrode and the substrate. 2. The substrate is a single crystal silicon substrate having a main surface of (100) plane orientation, and the recess formed in the substrate is an inverted regular pyramid-shaped recess having a slope of (111) plane orientation. Item 2. The electron-emitting device according to item 1. 3. The emitter electrode is W, Mo, Ta or Nb.
The electron-emitting device according to claim 1 or 2, wherein the electron-emitting device is formed of Cr and the lower protective layer is formed of Cr. 4. The electron-emitting device according to claim 1, wherein the insulating layer is a silicon oxide film. 5. The gate electrode is an Nb thin film layer.
5. The electron-emitting device according to any one of 4 to 4. 6. The method of manufacturing an electron-emitting device according to claim 1, wherein the step of: (a) forming an insulating layer on the substrate, forming a resist layer thereon, and patterning the resist layer; ) Step of etching the insulating layer using the patterned resist layer as a mask until the substrate is exposed; (c) Removing the resist layer, and further etching the substrate using the insulating layer as a mask to form the inverted pyramidal recess (D) On the recess side of the substrate, the lower protective layer material thin film layer, the emitter electrode material thin film layer and the upper protective layer are formed so that the emitter electrode is formed along the slope of the recess of the substrate. A step of sequentially forming a material thin film layer; (e) lifting off the insulating layer together with the material thin film layer for the lower protective layer, the material thin film layer for the emitter electrode, and the material thin film layer for the upper protective layer formed thereon. Patterning the layer protective layer, the emitter electrode and the upper protective layer; (f) etching the substrate so that the peripheral portions of the lower protective layer, the emitter electrode and the upper protective layer protrude from the upper edge of the recess of the substrate; g) a step of etching away the upper protective layer and an edge of the lower protective layer by etching; (h) a step of newly laminating an insulating layer on the concave side of the substrate and further laminating a gate electrode material thin film; And (i) lifting off the insulating layer newly formed on the emitter electrode together with the gate electrode material thin film layer thereon to form a gate electrode surrounding the emitter electrode without contacting the emitter electrode. And a manufacturing method. 7. The manufacturing method according to claim 6, wherein a single crystal silicon substrate having a (100) -oriented main surface is used as the substrate. 8. The manufacturing method according to claim 7, wherein an alkali metal hydroxide aqueous solution is used as an etchant when the recess is formed in the substrate by etching in the step (c). 9. The emitter electrode is W, Mo, Ta or Nb.
9. The manufacturing method according to claim 6, wherein the lower protective layer and the upper protective layer are formed of Cr. 10. The manufacturing method according to claim 9, wherein in step (g), RIE etching using a chlorine-based gas is performed, and then wet etching is performed using a cerium nitrate-based etching solution. 11. In step (a) and step (h),
A silicon oxide film is formed as an insulating layer.
The manufacturing method according to any one of 1. 12. In step (e) and step (i),
12. Use of buffered hydrofluoric acid for lift-off of the insulating layer.
Manufacturing method.