JPH0895530A - Liquid crystal display - Google Patents

Abstract

(57) [Abstract] [Purpose] A desired gradation display is performed by controlling the gradation level for each gradation number. [Configuration] In the gradation control circuit 17, the binary counter 3
Timing pulses corresponding to the binary code from 1 are output to the decoding circuit in parallel. Further, in the ROM 33, which is a non-volatile memory, decode data for determining the pulse width of the liquid crystal driving pulse for each mode is previously determined according to the characteristics of the liquid crystal, the user's specifications, the screen size of the liquid crystal display panel, the number of display gradations, and the like. Stored in. Then, the mode input terminal 18 is selected, desired decode data is read from the ROM 33, and the binary circuit 31 is read by the decode circuit 32.
Select the count value from, the six timing pulses in the mode are added by the OR circuit 35, the flip-flop circuit 35 synchronizes, and the gradation control clock C
Output KCB. A liquid crystal drive pulse is created based on the gradation control clock CKCB and display gradation data to drive the liquid crystal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device which performs a multi-gradation display using a liquid crystal display panel.

[0002]

2. Description of the Related Art Conventionally, for example, TN (Twisted Nematic)
When gradation display is performed using a liquid crystal display panel using liquid crystal, the voltage applied to the liquid crystal is controlled according to the gradation data to be displayed. The gradation control in this liquid crystal display device is controlled by changing the effective voltage applied to the liquid crystal by changing the voltage application time or the applied voltage value according to the gradation data.

For example, when the effective value of the applied voltage (Vop) is controlled to perform multi-gradation display, when the voltage is gradually applied to the liquid crystal, the alignment vector of the liquid crystal molecules is aligned in the direction of the electric field. Start to stand up.

FIG. 6 is a diagram showing the relationship between the effective voltage applied to the TN liquid crystal and the brightness. As shown in FIG. 6, after the threshold voltage (VOFF) is exceeded, the optical activity is suddenly lost, the transmitted light is blocked, and a black display appears. Then, when the applied voltage is further increased, the brightness gradually increases,
By applying an effective voltage equal to or higher than the saturation voltage (VON), good display with high contrast can be obtained. Conventionally, when performing 8 gradation display by varying the voltage application time, the characteristic line of the TN liquid crystal of FIG. Threshold voltage (VOF
Each gradation is displayed by selecting an application time of a voltage obtained by dividing (T1) into eight equal parts from F) to the saturation voltage (VON). As described above, in the conventional multi-gradation display control, the voltage averaging method is used to control (PWM) the pulse width of the liquid crystal drive voltage pulse according to the number of gradations of the video signal. Specifically, the pulse width of the liquid crystal drive pulse according to the number of gradations is preset by using the gradation control circuit 1 described below.

FIG. 7 is a diagram showing the structure of a conventional gradation control circuit 1. As shown in FIG. 7, the internal basic clock CK1 is input to the CK terminal of the binary counter 2, and the counter reset signal CKN1 that resets the binary counter 2 is input to the RESET terminal.

This binary counter 2 constitutes an 8-bit synchronous falling binary counter, and a decoding circuit 3 is sequentially arranged on the basis of an internal basic clock pulse CK1.
A timing signal composed of a plurality of count values is output to. The decoding circuit 3 takes the NAND (negative logical product) of the eight signals output from the binary counter 2 and further adds the NAND outputs by the OR circuit 4 to equalize 1H (1 horizontal scanning period). The gradation control clock CKCB is divided into seven equal parts.
Then, the gradation control clock CKCB of this uniform liquid crystal drive pulse is output from the inverted Q output terminal by the internal basic clock CK2, and is output via the buffer 6.

FIG. 8 shows clock timings of the above-mentioned internal basic clock pulses CK1 and CK2, a pulse of a counter reset signal CKN1 for resetting the binary counter 2 every 1H interval, and a decoding circuit 3 based on these signals. 6 is a timing chart of a gradation control clock signal CKCB that is generated. As shown in FIG. 8, the phase of CK1 input to the binary counter 2 and the phase of CK2 that outputs the gradation control clock CKCB created based on this are shifted, and the counter reset signal CKN1 output every 1H interval. The timing is set so that the grayscale control clock CKCB receives six predetermined pulses at equal intervals (interval a) between the second and the next CKN1.

The output gradation control clock CKCB
For example, in the case of 8-gradation display, as shown in FIG.
By inputting 6 pulses at equal intervals in one horizontal scanning section (1H section) from N1 to the next CKN1, seven liquid crystal driving pulses are created, and each liquid crystal driving pulse is set to 0.
8 gradations are displayed by selectively applying up to 7 levels.

As described above, the gradation control clock CKCB for controlling the pulse width of the conventional liquid crystal drive pulse is fixedly set by the count value of the decoding circuit 3 described above.

[0010]

However, in such a conventional liquid crystal display device, the gradation control clock CK for determining the pulse width of the liquid crystal driving pulse for gradation control is used.
Since the output timings of the CBs are at equal intervals and the output timings are fixed by the count value of the decoding circuit 3, the liquid crystal drive pulse having the same width is always output according to the number of gradations. Therefore, the gradation control clock C
The timing of KCB is TN (Twisted Nema) shown in FIG.
tic) liquid crystal, STN (Super Twis) shown in Fig. 9
ted Nematic) Like liquid crystal, threshold voltage (VOFF)
It cannot be used for gradation control of a liquid crystal having a narrow (T2) from the saturation voltage (VON) to the saturation voltage (VON), and vice versa.

Further, as shown in the characteristic diagram of the TN liquid crystal of FIG. 6, the threshold voltage (VOFF) and the saturation voltage (VON)
Since the amount of change in luminance is small in the vicinity and the amount of change is large in the middle part, it is possible to properly display gradation by simply applying a liquid crystal drive pulse having the same pulse width according to the number of gradations. There is a problem that you cannot do it.

Further, when there is a difference between the numerical gradation level and the gradation level according to the visual sense of the user, it is necessary to correct the gradation level so as to approach the gradation level of the visual sense. However, in the conventional liquid crystal drive pulse, since the pulse width is fixed, there is a problem that it is not possible to individually adjust the gradation level according to the number of gradations.

Further, when replacing with a liquid crystal display panel having a different screen size, the number of internal basic clock pulses CK1 and CK2 in the 1H section changes depending on the screen size, so the count values of CK1 and CK2 that match the screen size. It is necessary to drive the liquid crystal accordingly. However, the conventional liquid crystal display device has a problem in that the liquid crystal driving method cannot be changed in correspondence with liquid crystal display panels having different screen sizes.

Further, in the case of multi-gradation display, in order to drive the liquid crystal with different gradation numbers, it is necessary to change the pulse number of the liquid crystal driving pulse outputted at every predetermined cycle. But,
Since the conventional liquid crystal display device cannot adjust the number of liquid crystal driving pulses, for example, a driver for 8-gradation display cannot be used as a driver for other multi-gradation display. was there.

The present invention has been made in view of the above problems, and performs a desired gradation display by controlling the gradation level for each gradation number according to the characteristics of the liquid crystal, the user's visual perception, and the like. It is also an object of the present invention to provide a liquid crystal display device capable of coping with the screen size of the liquid crystal display panel and display control with different numbers of gradations.

[0016]

According to another aspect of the present invention, there is provided a liquid crystal display device, wherein a number of liquid crystal driving pulses corresponding to gray scale data are applied to a liquid crystal of a liquid crystal display panel every predetermined period, and an effective voltage applied to the liquid crystal is applied. Is a liquid crystal display device for displaying gray scales while controlling, and which stores counting means for counting a basic clock and outputting a plurality of count values, pulse width data corresponding to each gray scale, and corresponding to each gray scale. Pulse width data storage means comprising a memory in which variation amount of the pulse width data is unevenly stored at least in part, a count value output from the counting means, and the pulse width data storage means. Gradation control signal generating means for generating a gradation control signal by selecting a pulse width according to an arbitrary gradation based on the output pulse width data. It allows to achieve the above object.

Further, in the liquid crystal display device according to a second aspect, the pulse width data storage means further selects a desired mode from a plurality of modes of pulse width data stored in the pulse width data storage means. A mode selection unit may be provided, and a mode may be selected by the mode selection unit, and the gradation control signal may be obtained based on the pulse width data of the mode.

Further, in the mode selection means of the liquid crystal display device according to claim 3, the pulse width of the pulse width data storage means stored corresponding to the frequency of the clock pulse which changes according to the liquid crystal display screen size. A screen size mode selection unit for selecting data may be provided.

[0019]

In the liquid crystal display device according to the first aspect, the counting means counts the basic clock to output a plurality of count values, and the pulse width data storage means stores the pulse width data corresponding to each gradation, and Pulse width data in which the variation amount of the pulse width data corresponding to each gradation is non-uniform in at least a part is stored in advance, and a count value output from the counting means by the gradation control signal creating means, and the pulse width data. Based on the pulse width data output from the storage unit, a pulse width corresponding to an arbitrary gradation is selected to generate a gradation control signal.

Therefore, when a different liquid crystal display panel is exchanged, an appropriate gradation control signal is supplied in accordance with the type of liquid crystal of the liquid crystal display panel, user specifications, etc.
Various gradation data stored in advance in the pulse width data storage means composed of a non-volatile memory is selectively taken out, and desired gradation display is performed by appropriately changing the pulse width for gradation control. You can

According to another aspect of the liquid crystal display device of the present invention, the pulse width data storage means further selects a desired mode from pulse width data of a plurality of modes stored in the pulse width data storage means. Means for selecting the mode by the mode selecting means, and obtaining the gradation control signal based on the pulse width data of the mode.

Therefore, desired gradation control can be easily performed only by switching the mode using the mode selecting means.

In the liquid crystal display device according to the third aspect, the pulse width data of the pulse width data storage means stored in the mode selection means in correspondence with the frequency of the clock pulse which changes according to the size of the liquid crystal display screen is used as the screen size. The mode selection means is used for selection.

Therefore, even if the liquid crystal display panel having a different screen size is replaced, the screen size can be easily accommodated by only selecting the mode corresponding to the screen size.

[0025]

EXAMPLES The present invention will be specifically described below based on examples. 1 to 5 are views for explaining the liquid crystal display device of the present invention. In the present embodiment, in addition to 8 gradation display mainly displaying 8 gradations from black level to white level, 6th floor The gradation display and the 5 gradation display are performed.

FIG. 1 is a block diagram showing the configuration of a liquid crystal television 11 according to this embodiment, in which the pulse width of the liquid crystal drive pulse applied to the liquid crystal is controlled (PWM control) to display the gradation on the liquid crystal display panel. It adjusts the level.

The liquid crystal television 11 includes an antenna 12, a tuner 13, a receiving circuit 14, a synchronizing circuit 15, an A / D converter 16, a gradation control circuit 17, a switch section 18, a controller 19, an interface circuit 20, and a liquid crystal module 21. , A signal side drive circuit 22, a scanning side drive circuit 23, a liquid crystal display panel 24 and the like.

In the liquid crystal display device of the present embodiment, the displayed gray scale levels appear different depending on the characteristics of the liquid crystal and various liquid crystal driving methods. Therefore, by controlling the pulse width of the liquid crystal driving pulse, an appropriate gray scale can be obtained. The display is controlled so that it is displayed at the level. Further, in the liquid crystal display device of the present embodiment, the screen size of the liquid crystal display panel 24 is changed,
Even when the number of display gradations is changed, display control corresponding to this can be performed.

The antenna 12 receives the radio wave received by the tuner 13.
The tuner 13 selects a designated channel according to the tuning control signal VT input from the controller 19, converts the received radio wave supplied from the antenna 12 into an intermediate frequency signal, and outputs the intermediate frequency signal to the reception circuit 14.

The receiving circuit 14 is composed of an intermediate frequency amplifying circuit, a video detecting circuit, a video amplifying circuit, a chroma circuit and the like. The intermediate frequency signal inputted from the tuner 13 is subjected to video detection by the video detecting circuit to obtain a color video signal. Of the color video signal, an audio signal is taken out from the color video signal, and is output to an audio circuit (not shown). The chroma circuit separates the R, G, and B color video signals from the color video signal and outputs them to the A / D converter 16.

The synchronizing circuit 15 extracts the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync from the color video signal and outputs them to the controller 19. A / D converter 1
Although not shown, 6 is composed of a sampling circuit, a comparator circuit, and an encoder circuit. Functionally, R, G, B analog signals are sampled and A / D converted by a comparator (equal division within the range of RHH to RLL).
After that, the encoder circuit converts it into 3-bit digital display data.

The gradation control circuit 17 creates a desired gradation control clock CKCB in which the pulse width of the liquid crystal drive pulse applied to the liquid crystal is adjusted for each gradation, and the signal side drive circuit 22.
The liquid crystal drive pulse having various pulse widths is output to adjust each gradation level to be displayed. As a basic gradation control method, the number of pulses corresponding to the number of gradations of input display data is output to the signal side drive circuit 22 every 1H to control the gradation of the liquid crystal. In the gradation control circuit 17, the pulse width applied for each gradation is varied so that an appropriate gradation display is performed according to the type and temperature of the liquid crystal, or the actual visual recognition condition. Is.

The switch section 18 includes the gradation control circuit 17
It is a data input unit for selecting and inputting the setting data of the pulse width for each gradation which is set in advance. In particular,
The pulse width data for each gradation is stored in advance in the ROM provided in the gradation control circuit 17 for a plurality of modes, and M1 to M6 (see FIG. 2) for selecting desired data among them are stored. The switch corresponds to this. Especially M1-M
For 4-bit switches up to 4, select the mode according to the user and LCD specifications.
With the bit switch, a mode is selected according to the screen size of the liquid crystal display panel.

The controller 19 controls the overall operation of the liquid crystal television 11. For example, the controller 19 causes the liquid crystal display panel 24 to display an image based on the horizontal synchronizing signal (Hsync) and the vertical synchronizing signal (Vsync). Or A /
The sampling clock is generated and supplied to the D converter 16, and the internal basic clocks CK1 and CK2 having two phases are supplied to the gradation control circuit 17.

The interface circuit 20 supplies the horizontal synchronizing signal and the vertical synchronizing signal input from the controller 19 to the signal side driving circuit 22 and the scanning side driving circuit 23, respectively, and an image is displayed on the liquid crystal display panel 24 while driving the scanning. The display is performed.

The vertical synchronizing signal is a CDB signal that determines the scan electrode scan start timing and the scan electrode selection width, a CFB signal that is a scan inversion signal for AC driving the liquid crystal in each frame, and the CDB signal on the scan side. It consists of CNB signals that are sequentially shifted in the drive circuit 23.

The horizontal synchronizing signal includes a CKN signal for latching display data in the signal electrode and outputting the display data stored in the signal side drive circuit 22 to the liquid crystal display panel 24, and an STI signal for starting sampling of the display data. It is composed of a CKF signal for AC driving the liquid crystal for each frame and CK1 and CK2 signals which are basic clock signals of the signal side drive circuit 22.

The liquid crystal module 21 includes the liquid crystal display panel 2
4, a signal side drive circuit 22 and a scanning side drive circuit 23, which are liquid crystal drivers for driving the liquid crystal sealed therein.

The liquid crystal display panel 24 is the STN here.
This is carried out using a liquid crystal cell in which liquid crystal is sealed, and signal electrodes and scanning electrodes made of ITO are arranged in orthogonal directions on the opposing surfaces of two transparent substrates made of glass plates.

The signal side drive circuit 22 includes a gradation control circuit 17
Gradation control clock (CKCB) with pulse width control
Is inputted, and the liquid crystal display panel 24 is driven by the gradation control clock CKCB to perform gradation control.

The scanning side drive circuit 23 generates a scanning signal and sequentially supplies it to a plurality of scanning line electrodes of the liquid crystal display panel 24 to bring it into a selected state, and a predetermined liquid crystal at each pixel position intersecting the signal electrode. The voltage is applied to drive the liquid crystal.

FIG. 2 is a circuit diagram of the gradation control circuit 17 of FIG. 1 for controlling the pulse width of the liquid crystal drive pulse. In FIG. 2, the gradation control circuit 17 includes a binary counter 31, a decoding circuit 32 (321 to 326), a ROM 33, an OR circuit 34, a flip-flop circuit 35, a buffer 36, and the like.

In the binary counter 31, the internal basic clock CK1 is input to the CK terminal, and the binary counter 31
A counter reset signal CKN1 for resetting the counter every 1H (one horizontal scanning period) is input to the RESET terminal of the. This binary counter 31 is an 8-bit synchronous falling binary counter, and after resetting by CKN1, it outputs eight output lines (31a) of the binary counter 31 based on the internal basic clock pulse CK1.
~ 31h) through "1, 2, 4, 8, 16, 32, 6
Timing pulses corresponding to the binary code of “4,128” are output in parallel to the decoding circuit 32.

The decoding circuit 32 includes a binary counter 3
RO which will be described later on various timing pulses output from 1
The selection is made based on the pulse width data for each gradation of various patterns stored in advance in M33, and the clock pulse to be the gradation control clock CKCB is output at the selected timing. That is, each of the decoding circuits 321 to 326 has an AND (or NA) not shown.
ND) gate, the desired timing pulse can be obtained by selecting the output from the binary counter 31 based on the decoded value of a predetermined pattern read from the ROM 33.

A ROM (Read Only Memory) 33 has, for example, several kinds of gradations according to specifications of a plurality of liquid crystal display devices (LCD), user specifications, characteristics of liquid crystal used, screen size of the liquid crystal display panel, and the like. A decode value for creating the control clock CKCB is stored in advance. The ROM 33 is provided with mode input terminals M1 to M6 as a switch unit 18 for selectively reading desired pulse width data from the outside. In this embodiment, M
By turning the mode input terminals 1 to M4 on "1" or off "0", the pulse width data of any mode stored in the ROM 33 can be read. By selecting the count value from the 8-bit binary counter 31 based on the pulse width data of the predetermined mode read in this way, the decode circuit 32 outputs 6 timing pulses from the decode 1 circuits 321 to decode 6 Each can be output from the circuit 326.
In accordance with this timing pulse, the gradation control clock CKCB, which has been subjected to arbitrary pulse width control (PWM control), is obtained.

The OR circuit 34 is for decoding and adding, and adds and outputs the values respectively output from the decoding 1 circuit 321 to the decoding 6 circuit 326 of the decoding circuit 32.

The flip-flop circuit 35 synchronizes the six timing pulses from the decoding circuit 32 added by the OR circuit 34 with the timing of the internal basic clock CK2, and the gradation control clock CK via the buffer 36.
It is output as CB.

FIG. 3 is a diagram for explaining the principle of the liquid crystal gradation control method of this embodiment. In FIG. 3, the vertical axis represents the brightness of the liquid crystal display, and the horizontal axis represents the effective value of the applied voltage (Vop). The characteristic curve of the liquid crystal shown in FIG. 3 shows that the voltage exceeds the threshold voltage (VOFF) and the saturation voltage (VON).
Just before this, the brightness changes gently, and the change in brightness is constant in the middle part.

Conventionally, as described above, liquid crystal driving pulses having the same pulse width, which are equal divisions of the effective voltage from the threshold voltage (VOFF) to the saturation voltage (VON), are applied to the liquid crystal by the number of pulses corresponding to the number of gradations. Pulse width control (PW
M) was performed to display multi-gradation. Therefore, near the threshold voltage (VOFF) and saturation voltage (VON)
Just before this, the amount of change in luminance with respect to the applied voltage was small, and even if a liquid crystal drive pulse having the same pulse width as that of the intermediate portion was applied, proper gradation could not be displayed. Therefore, in the liquid crystal display device of the present embodiment, the effect of the applied voltage at each gradation display is changed according to the characteristics of the liquid crystal, the user's visual recognition condition, the liquid crystal driving method, the change in the number of display gradations, or the change in the display screen size. The value is changed to drive the liquid crystal.

In this embodiment, the gradation control circuit 1 shown in FIG.
7, a predetermined timing pulse is created by selecting the count value output from the binary counter 31 based on the pulse width data for each mode stored in advance in the ROM 33, and 1H shown in FIG. The pulse widths of the liquid crystal drive pulses corresponding to the gradations applied during are set arbitrarily. In this way, by applying an effective voltage with a variable pulse width to the liquid crystal according to each gradation,
Various gradation levels can be arbitrarily adjusted.

Since the liquid crystal display panel used in the liquid crystal television of the present embodiment performs negative inversion display, when an effective voltage for zero gradation driving is applied, it becomes a black (dark) state, and conversely the effective voltage reaches a saturation voltage. White (bright) is produced in the 8-gradation driving state, but the gray level of the black level near the threshold voltage (VOFF) shown in FIG. 3 and the white level slightly before the saturation voltage (VON) The gradation has a small amount of change in brightness with respect to the applied voltage. Therefore, by increasing the pulse width of the liquid crystal drive pulse for other gradations (by increasing the voltage application time and increasing the effective voltage), the brightness Is adjusted so that the amount of change is uniform for each gradation. As described above, in the liquid crystal display device of the present embodiment, it is possible to arbitrarily control the gradation level so as to obtain an appropriate gradation display according to the characteristics of the liquid crystal, the visual recognition situation of the user and the like.

FIG. 4 shows a gradation control circuit 1 according to this embodiment.
7 is a pulse waveform diagram showing an example in which the pulse width of the liquid crystal drive pulse is arbitrarily set by using FIG. CKCB1 shown in FIG.
The pulse waveforms of CKCB2, CKCB14, and CKCB15 show an example in which the counter reset signal CKN1 is input to the binary counter 31 every 1H and the pulse width for each gradation of the liquid crystal drive pulse applied every 1H is varied. Is.

The CKCB1 of FIG. 4 uses the basic clock pulse that counts 270 during 1H, and inputs six pulses in the 1H section at their respective unique timings, thereby making them 20, 76, 26, and 24, respectively. , 26,
Seven liquid crystal drive pulses with a pulse width of 76, 20 counts are set, and 0 is set according to the number of pulses applied to the liquid crystal.
8 gradations up to 7 are displayed.

In the CKCB2 of FIG. 4, the first and last pulses have a large pulse width of 80 counts, and the five pulses in the middle portion are set to the pulse width of 22 counts. This CKCB2 is an example of pulse width setting when driving a liquid crystal having the same characteristics as the TN liquid crystal shown in FIG. 3, in the vicinity of the threshold voltage (VOFF) and the saturation voltage (VON ) .Because the amount of change in brightness is becoming more gradual before (), a large pulse width is set at the beginning and end, and since the amount of change is large and constant in the middle part, a narrow pulse with the same width is set. ing.

Further, in the CKCB 14 of FIG. 4, the first and last pulses have the pulse widths of 20 counts and 19 counts, and the three pulses in the middle portion are 77 pulses, respectively.
It is set to the pulse width for the count. This CKCB
In the case of 14, by inputting four pulses at a specific timing in the 1H section, a maximum of five liquid crystal drive pulses can be set to a predetermined pulse width, and depending on the number of pulses applied to the liquid crystal, 0 to 0 can be set. 6 gradations up to 5 can be displayed. This CKCB14 is an example of pulse width setting when driving a liquid crystal having characteristics opposite to those of the TN liquid crystal shown in FIG. 3, in the vicinity of the threshold voltage (VOFF) and the saturation voltage (VON). Since the amount of change in brightness is steep just before, the pulse width at the beginning and end is small, and the amount of change is moderate and constant in the middle part, so a wide pulse with the same width is set. .

Further, the CKCB 15 of FIG. 4 inputs three pulses at a specific timing in the 1H section, so that pulses of approximately 73, 63, 63 and 71 counts at substantially the same intervals can be used for a maximum of four liquid crystal drive pulses. Can be set up to 5 depending on the number of pulses applied to the liquid crystal.
The gradation can be displayed. In this case, the amount of change in brightness from the threshold voltage (VOFF) to the saturation voltage (VON) is constant, and the number of gradations is as small as five, so a wide pulse with the same width is set. ing.

FIG. 5 shows the above-mentioned CKCB1 and CK of FIG.
It is a figure showing the relation between the decode data in ROM and the selection state of the mode input terminal when performing the pulse width control shown in CB2, CKCB14, and CKCB15.

Next, the operation of this embodiment will be described. First,
In the liquid crystal television 11 shown in FIG. 1, 1H (horizontal scanning period) is set according to the characteristic curve of luminance change with respect to the effective voltage applied to the liquid crystal, the liquid crystal driving method, the visual sense, the screen size of the liquid crystal display panel, or the number of display gradations. By varying the pulse width and the number of pulses of a plurality of liquid crystal driving pulses applied to the (1), the gradation level is corrected and the number of gradations is changed to realize proper gradation display. Here, the liquid crystal display panel is implemented as a liquid crystal television having a replaceable liquid crystal module.

The liquid crystal television 1 shown in FIG. 1 receives television broadcast radio waves through the antenna 12 and displays the received image on the liquid crystal display panel 24. In FIG. 1, the received radio wave received by the antenna 12 is supplied to the tuner 13. The tuner 13 selects a designated channel according to the tuning control signal VT input from the controller 19, converts the reception radio wave supplied from the antenna 12 into an intermediate frequency signal, and outputs the intermediate frequency signal to the reception circuit 14. Receiver circuit 14
Then, the intermediate frequency signal input from the tuner 13 is subjected to video detection by a video detection circuit to extract a color video signal, and an audio signal is extracted from the color video signal and output to an audio circuit (not shown). The color video signal is amplified by and output to the chroma circuit. The chroma circuit separates the R, G, and B color video signals from the color video signal and outputs them to the A / D converter 16.

In the case of the liquid crystal television 11 shown in FIG. 1, the decode value for each mode stored in the ROM of the gradation control circuit 17 in advance is set to the switch unit (mode input terminal) 1.
By using 8 for selection, each liquid crystal drive pulse for controlling the gray scale of the liquid crystal can be set to a desired pulse width according to the display data input from the A / D converter 16. As described above, by selecting the pulse width of a desired pattern using the mode input terminal 18, various gradation control can be easily performed. A / D converter 1 described above
The gradation control clock CKCB, which is pulse-width modulated by the 3-bit parallel display data of R, G, and B created in 6 and the gradation control circuit 17, is output to the signal side drive circuit 22. The signal side drive circuit 22 converts the parallel display data into serial display data, and therefore, the display data serially gradation-controlled by the timing signals P1, P2, P3 signals, the gradation control clock CKCB, and the horizontal synchronizing signal. It is created and supplied to the liquid crystal display panel 24.

Specifically, as shown in FIG. 1, the user uses the mode input terminal of the switch section 18 to select a mode for designating predetermined pulse width data of each liquid crystal drive pulse to be applied to the liquid crystal every 1H. Do. This mode selection is
As shown in FIG. 2, the mode input terminal M of the switch unit 18
By appropriately combining ON / OFF of 1 to M6,
The desired pulse width data stored in advance in the ROM 33 can be designated and read.

Then, the binary counter 31 outputs a binary code "1,2,2" based on the input internal basic clock CK1 (counts 270 in the 1H section).
4, 8, 16, 32, 64, 128 "timing pulses are output to the decoding circuit 32 via the lines 31a to 31h. Then, the decoding circuit 32 selects various input timing pulses based on the pulse width data of the predetermined mode read from the ROM 33, thereby creating various gradation control clocks CKCB at desired timings. be able to.

Therefore, as shown in FIG. 5, assuming that there are 270 basic clock pulses (CK1, CK2) in the 1H section, the CKCB signal output from the gradation control circuit 17 is equally spaced as in the conventional case. When displaying 8 gradations,
Set M1, M2, M3, and M4 of the mode input terminal 18 to "0,
“0, 0, 0” is read from the ROM 33 to each of the decode 1 circuit 321 to decode 6 circuit 326, and the pulse width data of the mode is read out, and the count value of the binary counter 31 is combined and selected.
8, 117, 156, 195, 234 "count timing pulses are generated, and the gradation control clock CKCB having the same pulse width as that of the conventional one as shown in FIG. 8 can be generated.

Specifically, in the decode 1 circuit 321,
D of the first pulse width data input from the ROM 33
By selecting the first, second, third, and sixth binary outputs from the binary counter 31 by the EC1, the total of binary codes becomes 1 + 2 + 4 + 32, and 39 count timings are created and output.

Next, in the decode 2 circuit 322, the ROM
DEC2 of the second pulse width data input from 33
Thus, by selecting the second, third, fourth and seventh binary outputs from the binary counter 31, the total of the binary codes becomes 2 + 4 + 8 + 64, and the timing for 78 counts is created.

Further, in the decode 3 circuit 323, the first, the third, the fifth, the sixth, and the seventh are selected in the same manner as described above, and the total of the binary codes becomes 1 + 4 + 16 + 32 + 64, and the timing for 117 counts is created.

Further, in the decode 4 circuit 324, 3,
By selecting the 4th, 5th and 8th, the sum of the binary codes becomes 4 + 8 + 16 + 128 and the timing for 156 counts is created.

In the decode 5 circuit 325, 1, 2
The second code, the seventh code, and the eighth code are selected, and the sum of the binary codes becomes 1 + 2 + 64 + 128, and the timing for 195 counts is created.

In the decode 6 circuit 326, the second, fourth, sixth, seventh and eighth are selected, and the total of binary codes becomes 2 + 8 + 32 + 64 + 128, and the timing for 234 counts is created.

As shown in FIG. 2, the six pieces of timing data created as described above are added by the OR circuit 34 from the decoding circuit 32 and input to the flip-flop 35, and the timing of the internal basic clock CK2 is obtained. Therefore, the gradation control clock CKCB is output from the inverted Q output terminal via the buffer 36. As a result, it is possible to create a liquid crystal drive pulse for performing 8-gradation display at equal intervals as in the conventional case as shown in FIG.

The gradation control clock CKCB described above includes 6 liquid crystal driving pulses each having a pulse width of 39 counts and 36 counts for 36 counts in a 1H period from when the reset pulse CKN1 shown in FIG. 8 is input until the next CKN1 is input. One liquid crystal drive pulse is formed. The gradation control clock CKCB is used when the luminance change of the liquid crystal between the threshold voltage (VOFF) and the saturation voltage (VON) is constant, and it is necessary to control each pulse width of the liquid crystal drive pulse evenly. This is the case.

Next, the gradation control clock C in FIGS.
When creating the KCB1, if the mode input terminals M1 to M4 are set to "1, 0, 0, 0" and the mode is changed in the same manner as described above, the predetermined pulse width stored in the ROM 33 is set. Read the data, select the count value from the binary counter 31 in the decoding circuit 32,
6 from decode 1 circuit 321 to decode 6 circuit 326
Two timing pulses are created. The six timing pulses are "20, 96, 12" as shown in FIG.
The gradation control clock CKCB2 created by the timing pulse of the count of 2, 148, 174, and 250 "is output, and the desired gradation display is performed by changing the number of pulses according to the display gradation data. You can

Further, the gradation control clock C in FIGS.
In the case of KCB2, when the mode input terminals M1 to M4 are set to "0, 1, 0, 0" and the mode is changed in the same manner as described above, the predetermined decode value stored in the ROM 33 is read. The desired binary count value output from the binary counter 31 is selected by the decode circuit 32, and the decode 1 circuit 321 to the decode 6 circuit 326 generate six timing pulses. The six timing pulses are "80, 10" as shown in FIG.
2, 124, 146, 168, 190 "count control pulse CKC created with timing pulses
B3 is output and a desired gradation display can be performed by changing the number of pulses according to the display gradation data. In particular, in the case of this gradation control clock CKCB2, since the amount of change in luminance is gentle near the threshold voltage (VOFF) and just before the saturation voltage (VON), the first and last The gradation control is performed so that the luminance difference between the displayed gradation levels becomes equal by increasing the effective pulse voltage applied to the liquid crystal by increasing the pulse width of.

Next, the number of display gradations can be changed by changing the number of pulses of the gradation control clock CKCB whose pulse width is controlled. For example, as shown in the gradation control clock CKCB14 in FIG. 5, when it is desired to display 6 gradations, the mode input terminals M1 to M4 are set to “0, 1, 1,
1 "to change the mode, read the predetermined pulse width data stored in the ROM 33, and output a desired binary count value from the binary counter 31 to the decode 1 circuit 321 and the decode 2 circuit of the decode circuit 32. Circuit 322, decode 3 circuit 323, decode 4 circuit 32
4 and decode 5 circuit 325, and decode 6 circuit 326
4 are used to create 4 timing pulses. The four decoded values are, as shown in FIG.
The gradation control clock CKCB14 generated by the timing pulse of the count of "7, 174, 251" is output, and the number of pulses is varied according to the display gradation data to display 6 gradations at a desired gradation level. Can be done. Particularly, in the case of this gradation control clock CKCB14, as shown in FIG. 4, the amount of change in brightness is steep near the threshold voltage (VOFF) and just before the saturation voltage (VON). By reducing the pulse widths of the first and last pulses to reduce the effective voltage applied to the liquid crystal, the luminance difference between the displayed gradation levels is made equal, and appropriate gradation control is performed.

In the case of displaying 5 gradations, the mode input terminals M1 to M4 are set as "1, 1, 1, 1" as shown in the gradation control clock CKCB15 of FIG. The predetermined pulse width data stored in the ROM 33 is changed and the desired binary count value from the binary counter 31 is read by the decode 1 circuit 321, the decode 2 circuit 322, the decode 3 circuit 323, and the decode 4 circuit. Circuit 324, decode 5 circuit 32
Three timing pulses are created using three of 5 and the decode 6 circuit 326. The three decoded values are shown in FIG.
, The gradation control clock CK created by the timing pulses for the count of “73, 136, 199”
The CB 15 is output, and the number of pulses can be varied according to the display gradation data, whereby 5 gradation display can be performed at a desired gradation level. In particular, in the case of this gradation control clock CKCB15, as shown in FIG. 4, since the amount of change in luminance is constant, a number of liquid crystal drive pulses having pulse widths of approximately equal intervals are applied according to the gradation. By doing so, an effective voltage corresponding to each gradation level is applied, and appropriate gradation control can be performed.

Next, when the liquid crystal display panel having a different screen size is exchanged, the number of pulses of the basic clock pulses CK1 and CK2 in the 1H section changes, so that the mode input terminal 18 displays a screen as shown in FIG. M5 and M6 are provided as size mode input terminals. The screen size mode input terminals M5 and M6 are preselected to store decoding data in the ROM 33 according to the number of clock pulses of CK1 and CK2 corresponding to four kinds of screen sizes in combination of ON / OFF. It is possible to output the gradation control clock CKCB according to the desired screen size based on the decoded data of the selected mode.

As described above, the liquid crystal display device of this embodiment is
The decode data for creating the pulse width for each gradation of the liquid crystal drive pulse applied to the liquid crystal is stored in advance in the nonvolatile memory R
Since it is stored in the OM or the like and the decode data in the ROM is selectively designated to change the pulse width for each gradation to perform gradation control, it is possible to adjust the brightness for each gradation. Even if the characteristics of the liquid crystal, the liquid crystal driving method, the visual perception of the user, the screen size of the liquid crystal display panel, or the number of display gradations are changed, appropriate gradation control corresponding to these can be performed.

In the above embodiment, the case where the invention is applied to the liquid crystal television has been described, but the invention is not limited to this, and various liquid crystal panels are actually mounted as a liquid crystal evaluation device to switch modes. However, the present invention may be carried out by finding the optimum liquid crystal driving condition, or may be applied to other liquid crystal display devices.

Further, in the liquid crystal display device of this embodiment, 8
Although description has been made by taking the case of gradation, 6 gradations, and 5 gradations as an example, the present invention is not limited to this, and when performing multi-gradation display of 4 gradations or less, or 9 gradations or more. It goes without saying that the same can be applied to.

[0080]

According to the liquid crystal display device of the first aspect,
The pulse width data storage means composed of a non-volatile memory stores in advance pulse width data of a plurality of modes in which the pulse width of the liquid crystal drive pulse applied to the liquid crystal at a predetermined cycle is adjusted for each gradation. Pulse width data according to the sense of visual perception, the screen size of the liquid crystal display panel, the number of display gray scales, etc., is appropriately selected to create a gray scale control signal having a predetermined pulse width, so that the desired gray scale can be easily Control can be performed.

According to the liquid crystal display device of the second aspect, since the mode selection means for selecting the pulse width data of a plurality of modes stored in the pulse width data storage means is provided, the mode selection means is used. A desired gradation control can be easily performed only by switching the mode.

According to the liquid crystal display device of the third aspect, since the mode selecting means is provided with the screen size mode selecting means for selecting the mode according to the screen size of the liquid crystal display panel, the liquid crystal display panels of different screen sizes are provided. Even if it is replaced with a new one, it can be dealt with quickly and easily, and the liquid crystal can be appropriately driven.

According to the liquid crystal display device of the fourth aspect, since the binary counter is used as the counting means, the count value output from the binary counter is based on the pulse width data stored in the pulse width data storage means. A gradation control signal having a desired pulse width can be obtained simply by selecting the gradation control signal generating means.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal television according to an embodiment.

FIG. 2 is a circuit diagram showing a detailed circuit configuration of a gradation control circuit of FIG.

FIG. 3 is an explanatory diagram of the principle of controlling the gradation of liquid crystal in the present embodiment.

FIG. 4 is a waveform diagram showing a pulse waveform when the pulse width of the liquid crystal drive pulse is set to a desired pattern by using the gradation control circuit of the present embodiment.

5 is a diagram showing a relationship between a combination of mode input terminals for selecting decode data in the ROM of FIG. 2 and corresponding decode data.

FIG. 6 is a diagram showing a relationship between effective voltage applied to a TN liquid crystal and brightness.

FIG. 7 is a diagram showing a configuration of a conventional gradation control circuit.

FIG. 8 is a timing chart of a clock timing of an internal basic clock pulse, a reset pulse, and a gradation control clock CKCB created by a decoding circuit.

FIG. 9 is a diagram showing the relationship between the effective voltage applied to the STN liquid crystal and the luminance.

[Explanation of symbols]

 11 liquid crystal television 12 antenna 13 tuner 14 receiving circuit 15 synchronizing circuit 16 A / D converter 17 gradation control circuit 18 switch section (mode input terminal) 19 controller 20 interface circuit 21 liquid crystal module 22 signal side drive circuit 23 scanning side drive circuit 24 liquid crystal display panel 31 binary counter 32 decode circuit 321 decode 1 circuit 322 decode 2 circuit 323 decode 3 circuit 324 decode 4 circuit 325 decode 5 circuit 326 decode 6 circuit 33 ROM 34 OR circuit 35 flip-flop circuit 36 buffer

[Procedure amendment]

[Submission date] November 24, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2] ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 1, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

Claims (3)

[Claims] 1. A liquid crystal display device which performs gradation display by applying a number of liquid crystal drive pulses corresponding to gradation data to a liquid crystal of a liquid crystal display panel at predetermined intervals to control an effective voltage applied to the liquid crystal. A counting means for counting a basic clock and outputting a plurality of count values; pulse width data corresponding to each gradation; and a change amount of the pulse width data corresponding to each gradation is non-uniform in at least a part Pulse width data storage means including a memory in which various pulse width data is stored in advance, a count value output from the counting means, and pulse width data output from the pulse width data storage means based on an arbitrary gradation. A gradation control signal generating means for generating a gradation control signal by selecting a pulse width according to the liquid crystal display device. 2. The pulse width data storage means further comprises mode selection means for selecting a desired mode from pulse width data of a plurality of modes stored in the pulse width data storage means, and the mode selection means. 2. The liquid crystal display device according to claim 1, wherein the mode is selected by the step, and the gradation control signal is obtained based on the pulse width data of the mode. 3. The mode selection means for selecting a screen size for selecting the pulse width data of the pulse width data storage means stored corresponding to the frequency of the clock pulse which changes according to the liquid crystal display screen size. The liquid crystal display device according to claim 2, further comprising means.