JPH0895862A - Data processing device using snoop cache - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the reliability of data stored in a snoop cache in a shared bus parallel processor system using a snoop cache. [Composition] When the data of the SM normal area 220 is stored in the SCa 21, it is stored only in the CDM 1a25. Invalidation type is used for content matching control. When the data of the SM high reliability area 210 is stored in the SCa21, it is stored in the CDM1a25 and at the same time, a different snoop cache, for example, the CDM2b2 of the SCb211.
Also stored in 17. Update control is used for content matching control. [Effect] Particularly, data that requires high reliability can be stored in two or more different snoop caches, and by using update-type concurrency control, data multiplexing is realized and data is lost when a failure occurs. Can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for making a snoop cache highly reliable and a data processor using the same, and is particularly suitable for a control device such as a disk control device which requires high reliability. The present invention relates to a snoop cache high reliability method and a data processing device.

[0002]

2. Description of the Related Art In a current computer system, most of the data required by a host processor (hereinafter referred to as CPU) is stored in a secondary storage device. The CPU reads / writes data from / to the secondary storage device as needed.
A non-volatile medium is generally used as a recording medium of the secondary storage device. Typical examples include a magnetic disk drive (hereinafter referred to as a drive) and an optical disk drive. These drives are disk controllers (hereinafter D
KC) and is connected to the CPU. DKC is C
Analysis of commands transferred from PU, drive and CP
Transfer data between U.

As an example of the configuration of the DKC, H manufactured by Hitachi
The -6581-C3 machine will be described with reference to FIG. The channel data transfer circuit CDC15 transfers data between the CPU and the data cache (DataCache) 110 in the DKC11, and the drive data transfer circuit DDC113 drives the DataCache110.
And data transfer between the drive 112 and the drive 112. The DataCache control circuit CMC113 stores data in DataCache and CPU
Performs processing such as determining whether the data for which a read / write request exists is present / absent in DataCache. CDC15,
The DDC113 and CMC115 are connected to the common bus DBS17 for data transfer. Timing control such as starting and stopping of each CDC 15 and DDC 113 is performed by the microprocessor MP16. The DKC 11 is composed of a plurality of MPs 16 in order to improve the I / O processing performance. Each MP1
Reference numeral 6 executes the I / O processing while repeatedly reading and writing the configuration information of the DKC 11 and the control information such as the processing status of the I / O request. These pieces of control information are information shared by each MP 16, and in order to prevent inconsistency, a single shared memory SM19 is provided via the shared memory control circuit SMC116.
It is stored in. Each MP16 and SMC116 are connected to a control common bus CBS18 and form a shared bus type parallel processor. In the DKC 11, in order to read and write control information centrally stored in a single SM 19, SM 19 and C
Many access to the BS 18 occurs, which causes a performance bottleneck.

In a shared bus type parallel processor system such as the DKC 11, the following method is known for solving the performance bottleneck caused by the shared memory and shared bus access. This is a method in which a local cache memory is provided for each MP 16 and a copy of the control information in the SM 19 is distributed and stored therein to reduce the number of accesses to the SM 19 and CBS 18. There is a technique called a snoop cache as a technique for performing the content matching control of the copy of the control information in each local cache memory.

As a document describing the details of the snoop cache, Norihisa Suzuki et al .: A shared memory type parallel system,
Corona, 1993, Hennessy et al. (JL Hennessy & D.A.
Patterson), Shinji Tomita et al .: Computer Architecture, Nikkei BP, 1992, etc. According to these documents, there are an invalidation type and an update type in the matching control method of the snoop cache. In invalidation type, there is MP16
When the control information is rewritten by, the same control information in other local cache memory is invalidated. The invalidation type is a method in which the latest data exists in any one of the local caches immediately after the control information is rewritten. On the other hand, in the update type, the same control information in other local cache memories is rewritten together. The update type is a method in which the latest data may exist in a plurality of local caches immediately after rewriting the control information.

Hereinafter, the degree of reduction in the number of accesses to the CBS 18 when the local cache memory is provided in each MP 16 of the DKC 11 and the invalidation type or the update type is applied as the matching control method is regarded as the performance of the matching control method. .
That is, the coincidence control method capable of further reducing the number of accesses to the CBS 18 is the coincidence control method having higher performance. The superiority or inferiority of the invalidation-type / update-type performance depends on the access pattern “which MP16 accesses which control information and in what order”. When a plurality of MPs 16 repeatedly access the same control information, the update type performance in which the same control information remains in each local cache memory is higher. However, when one MP 16 repeatedly accesses the same control information, the invalidation type performance that does not require unnecessary update processing is higher. Japanese Patent Publication No. 6-1463 describes a method of switching to a congruent control method that can obtain higher performance for each MP 16 according to an access pattern.

[0007]

In the DKC 11, since it is necessary to perform highly reliable control, the SM 19 is made highly reliable by duplication / nonvolatization. Special fairness over DKC11
When the conventional snoop cache technology as described in 6-1463 is applied, there is a problem that the reliability of the DKC 11 is lowered. The reason for this is that in both the update type and the invalidation type, a state in which the control information exists independently in one local cache memory may occur. If the local cache memory fails or power is cut off in this state, the control information that exists independently is lost and control cannot be continued. This is not preferable for the DKC 11 that requires highly reliable control. In particular, the invalidation type invalidates the others at the time of rewriting, so the number of cases that exist independently is greater than in the case of the update type, and the reliability is likely to deteriorate.

[0008]

In the present invention, when a copy of control information is placed in the local cache memory, the invalidity-based coincidence control method is used for control information that does not require so much reliability. The update-type congruence control method is used for control information that requires particularly high reliability. Further, in the case of the update type, it is guaranteed that there are copies of the control information in two or more local cache memories. Alternatively, the update-type matching control is used for all copies of the control information placed in the local cache memory, and it is guaranteed that the control information copies always exist in two or more local cache memories.

[0009]

The control information can be multiplexed by using the update-type coincidence control method for control information that requires high reliability and by making the control information always exist in two or more local cache memories. As a result, the loss of control information due to a failure of the local cache memory, power interruption, etc. is prevented,
The control information can be made highly reliable.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A snoop cache high reliability method and a data processing apparatus using the same according to the present invention will be described in detail below with reference to the drawings.

First, the features of this embodiment will be described with reference to FIG. As a first feature of this embodiment, when storing control information that requires high reliability in the snoop cache, update-type matching control is used. Further, when storing control information that does not require so much reliability in the snoop cache, invalidation-type matching control is used.

In the invalidation-type coincidence control, the same control information on another snoop cache is invalidated when the control information is changed. On the other hand, in the update-type matching control, when the control information is changed, the same control information on another snoop cache is also changed. For this reason, when the update-type matching control is used, the possibility that the same control information exists in plural snoop caches is higher than that in the invalidation-type matching control. As a result, the effect of increasing the reliability of the control information is produced.

A method of realizing the first feature will be briefly summarized below. Microprocessor 1617 or 161
When a change request for control information from 8 is generated, the snoop cache 1615 or 1616 checks the address of the change request. The address is shared memory 1
If it belongs to the high-reliability area 1604 of 603, the snoop caches 1615 and 1616 perform update-type coincidence control. On the other hand, if the address belongs to the normal area 1605, invalidation-type matching control is performed.

The second feature of this embodiment is that the same control information is always present in two or more snoop caches in the above update type coincidence control. In the conventional update type, the control information may exist only in one snoop cache due to the writing back to the shared memory or the like, and the reliability of the control information decreases. Therefore, the same control information always exists in two or more snoop caches to guarantee multiplexing. As a result, there is an effect that the reliability of the control information is further enhanced as compared with the conventional update type.

A method of realizing the second feature will be briefly summarized below. Snoop cache 1615 and 161
The memory of 6 is duplicated. Memory a161
2, 1611 and memory b 1613, 1610. Pair 1 of memory a1612 of snoop cache a1615
A memory b1610 of a different snoop cache B1616 is predetermined as 614. When the memory a1612 of the snoop cache A1615 performs processing such as storage of control information in the high-reliability region 1604 and coincidence control, the same processing is always performed in the memory b1610 to realize multiplexing of the same control information. For that purpose, an identification number unique to each snoop cache called a snoop cache ID is used. In the snoop cache A1615 of the memory a1612, the high reliability area 16
When the control information 04 is processed, the snoop cache ID value = 2 of the memory b1610 is sent to the shared bus 1606 (1601). The snoop cache B1616 of the memory b1610 confirms that it is a pair 1614 from its own ID sent to the shared bus 1606 (1602), and performs the same processing as the snoop cache A1615. By this processing, control information can be multiplexed.

The details of the first embodiment of the present invention will be described below.

FIG. 2 shows a block diagram of the first embodiment of the present invention. The DKC 11 is composed of a data transfer system that actually transfers data between the CPU and the drive 112, and a control system that controls this data transfer.

First, the channel data control circuit CDC1
The data transfer between the CPU and the DKC 11 performed by 5 will be described. The channel path 13 connects the CPU and the two channel switch circuits CSC14 in the DKC 11. CS
C14 has a maximum of 4 out of 4 or more channel paths 13.
This is a circuit for selecting a book. A total of eight CDCs 15 are connected to each of the two CSCs 14. The CDC 15 is connected to the data transfer common bus DBS17. DBS1
A DataCache control circuit CMC115 is also connected to 7. CPU
The data transferred from the channel path 13, CSC1
4, DataDC via CDC15, DBS17, CMC115
Stored in che110. When transferring data from DataCache110 to CPU, conversely, CMC115, DBS17, C
It passes through DC15, CSC14, and channel path 13.

Next, the data transfer between the DKC 11 and the drive 112 performed by the drive data control circuit DDC113 will be described. In addition to the CDC 15 and the DataCache 110, four DDCs 113 are connected to the DBS 17. The data transferred from the drive 112 is the drive path 114, DDC113, DB
It is stored in the DataCache 110 via S17 and CMC115.
When data is stored in the drive 112 from the DataCache 110, it goes through the CMC 115, DBS 17, DDC 113, and drive path 114.

Next, a control system for controlling the above data transfer will be described. The DKC 11 has 12 microprocessors MP16. For the MP16, the CDC 15 and the DDC 113 that are in charge of control are determined. Each MP16
Is connected to the control common bus CBS18 via the snoop cache memory SC111. A shared memory control circuit SMC116 is also connected to the CBS18.

Data transfer control between the CPU and the DataCache 110 will be described. MP1 in charge of controlling CDC15
6 accesses the control information stored in SM 19 or SC 111. Based on this result, CPU and DataCache1
Controls data transfer between 10 The details will be described below.

A data transfer request is sent from the CPU to the MP 16 which controls the CDC 15 in the DKC 11. The MP 16 that has received the request reads the control information that records the usage state of the DataCache 110. As a result, if the DataCache 110 is usable, the control information indicating the usage state is rewritten to “in use”. After that, the MP 16 permits the CPU and the CDC 15 to transfer data. Then, the data transfer between the CPU and the DataCache 110 is performed through the route described in the data transfer system. When data transfer is completed, MP16
Rewrites the control information that records the usage status of the DataCache 110 so that it can be used.

Data transfer control between the Data Cache 110 and the drive 112 will be described. DataCache110 and drive 1
When data transfer between 12 is performed, MP16 in charge of control of CDC15 to MP1 in charge of control of DDC113
The control right is transferred to 6. MP1 that controls DDC113
6 accesses the control information stored in SM 19 or SC 111. Based on this result, the data transfer between the DataCache 110 and the drive 112 is controlled.

The details will be described below. The MP 16 that has received the control right reads the control information that records the usage status of the drive 112. As a result, if the drive 112 is usable, the control information indicating the use state is rewritten to “in use”. After that, the MP 16 permits the DDC 113 to transfer data. Then, the data transfer is performed between the DataCache 110 and the drive 112 through the route described in the data transfer system. When the data transfer is completed, the MP 16 rewrites the control information for recording the usage status of the drive 112 to be usable.

FIG. 1 shows the details of the control system of the DKC 11.
SCa21 and SCb211 are the snoop caches SC111 of FIG.
2, and MPa22 and MPb212 correspond to the microprocessor MP16 of FIG. The SM 19 is divided into an SM high reliability area 210 and an SM normal area 220. Among the control information, the control information that requires particularly high reliability is stored in the SM high reliability area 210, and the control information that does not require much reliability is stored in the SM normal area 220.

The detailed structure of the SCa 21 will be described below. Since the SCb211 has the same configuration as the SCa21, its description is omitted. SCa21 is a snoop cache controller SCCa23, two cache tag memories CTM1a24 and C
TM2a26, two cache data memories CDM1a25 and CDM2a27 for storing a copy of control information, address checker A
Ca28, snoop cache ID register SCIDRa29
Composed of. SCCa23 has CBS18, CTM1a2
4, CTM2a26, CDM1a25, CDM2a27, ACa28, SCIDRa2
9, MPa22 is connected. ACa28 and SCIDRa29 are M
Also connected to Pa22.

When a copy of the control information in the SM high reliability area 210 is stored in the SCa21, it is always stored in the CDM2 of a different SC in addition to being stored in the CDM1a25. For example, it is stored in CDM2b217 of SCb211.

Next, the operation of ACa 28 will be described. ACa
When an access request for control information is issued from the MPa 28, 28 acquires the address of the control information for which the access request has been made. The acquired address is the SM high reliability area 21.
Whether the address is 0 or the address of the SM normal area 220 is checked, and the result is notified to SCCa23.

In FIG. 3, CTM1a24, CDM1a25, CTM2a26, CDM2a
Details of 27, CTM1b214, CDM1b215, CTM2b216, and CDM2b217 are shown.

First, the detailed configuration of the CDM 1a25 will be described. C
The DM2a27, CDM1b215, and CDM2b217 have the same configuration as the CDM1a25, and thus the description thereof is omitted. The CDM 1a25 is composed of one or more cache data blocks 35. The cache data block has a length of 1 bit or more, and a copy of the control information is stored therein.

Next, the detailed configuration of the CTM 1a24 will be described. CTM
The 2a26, CTM1b214, and CTM2b216 have the same configurations as the CTM1a24, and therefore their explanations are omitted. CTM1a24 consists of one or more cache tag records. One cache tag record of CTM1a24 corresponds to one cache data block 35 of CDM1a25. 1-bit cache tag record
Valid flag 31, 1-bit shared flag 32, 1bi
An owner flag 33 of t and an address tag 34 having a length of 1 bit or more.

The meaning of each element of the cache tag record will be described below. When the valid flag 31 is On, it means that a correct copy of the control information exists in the corresponding cache data block 35. Valid flag 3
When 1 is Off, the corresponding cache data block 3
5 means unused. Share flag 32 is O
When n, it means that the same copy of the control information in the corresponding cache data block 35 exists in the cache data memory other than the CDM1a25. When the shared flag 32 is Off, the same copy of the control information in the corresponding cache data block 35 is the CD
It does not exist in the cache data memory other than M1a25. When the owner flag 33 is On, it means that the corresponding cache data block 35 stores the latest control information that needs to be written back to the SM 19. When a failure occurs or when the cache data block needs to be replaced, the cache data block must be written back. Owner flag 3
When 3 is Off, it means that the control information stored in the cache data block 35 need not be written back to the SM 19. The address in the SM 19 of the copy of the control information stored in the corresponding cache data block 35 is stored in the address tag 34.

FIG. 4 shows the details of SCIDRa29 and SCIDRb219. The detailed configuration of SCIDRa29 will be described below. SCIDRb21
Since 9 has the same configuration as SCIDRa29, its explanation is omitted. SCIDR
a29 has two snoop cache identification numbers SCID321,
322 and two 1-bit flags 3 indicating the failure occurrence status
23 and 324 are saved. The SCID is an identification number unique to each snoop cache existing in the DKC11. Own SC
ID321 is the SCID of SCa21 itself. Opponent SCID322 is SM
This is the SCID of a pair of snoop caches when a copy of the control information of the high reliability area 210 is stored in the CDM2 of another pair of SCs. When the first failure occurrence flag 323 is On, it means that a failure has occurred in the paired SC when a copy of the control information in the CDM1a25 is stored in the CDM2 of another SC which is a pair. When the second failure occurrence flag 324 is On, it means that a failure has occurred in the paired SC when a copy of the control information in the CDM2a27 is stored in the CDM1 of another paired SC. The fault occurrence flags 323 and 324 can be set / reset by software by the MPa 22 or can be set / reset by hardware by the fault detection circuit, and the specific implementation method is arbitrary.

Details of the operation of the SCCa23 and SCCb213 shown in FIG. 1 will be described below with reference to FIGS. SCCa23, SCCb
The operation of 213 is roughly classified into an operation based on the control information access request from the MPa 22 and MPb 212 and an operation based on the monitoring result of the CBS 18.

First, the operation of the SCCa 23 when receiving the control information access request from the MPa 22 will be described with reference to FIGS. 5 to 18. Next, SC based on the monitoring result of CBS 18
The operation of Cb213 will be described with reference to FIGS. 19 to 24.

FIG. 5 shows the main routine 42 of the operation of the SCCa 23 when receiving the control information access request from the MPa 22. When a control information access request is issued from the MPa 22 to the SCCa 23 41, the ACa 28 determines whether the requested control information address is the address of the SM high reliability area 210 or the SM
It is checked whether it is the address of the normal area 220 (43). Then SC
Ca23 checks the command from MPa22 and checks whether the control information is read or written (44 or 45). Then SC
Ca23 searches the address tag 34 of CTM1a24 and the address tag 39 of CTM2a26 to check whether there is a copy of the control information in CDM1a25 or CDM2a27 (46, 4).
7, 48, 49). Hereinafter, the case where the copy of the desired control information exists in the CDM1a25 or CDM2a27 is called a hit, and the case where it does not exist is called a miss. As described above, eight types of processing are performed depending on the high reliability area / normal area, write / read, hit / miss.

In the case of high reliability area, read, and hit,
Performs processing of subroutine Suba415. No access to CBS 18 is required.

High reliability area, read, C in case of mistake
After the BS 18 is acquired 410 and the subroutine Subb416 is processed, the CBS 18 is released (423).

In the case of high reliability area, writing, and hit,
After the CBS 18 is obtained, the processing of 411 and the sub-routine Subc417 is performed, and then the CBS 18 is released (424).

High reliability area, write, C in case of mistake
After the BS 18 is acquired, the process of 412 and the subroutine Subd418 is performed, and then the CBS 18 is released (425).

In the case of normal area, read, and hit, the processing of the subroutine Suba419 is performed. No access to CBS 18 is required.

Normal area, read, CBS in case of miss
After the acquisition of 18, 413, the subroutine Sube420 is processed, and then the CBS 18 is released (426).

In the case of normal area, write, and hit, the processing of the subroutine Subf421 is performed. Access to CBS 18 may or may not be necessary.

Normal area, write, CBS in case of miss
After the acquisition of 18, the processing of the subroutine Subg422 is performed, and then the CBS 18 is released (427).

FIG. 6 shows details of the subroutine Suba processing. Suba 52 is processing when a read request to the SM normal area 220 or the SM high reliability area 210 is generated from the MPa 22 and hits. This subroutine is a process in response to a read request from the microprocessor when the requested control information exists in the snoop cache connected to the microprocessor. The snoop cache controller reads out the requested control information from the snoop cache and passes it to the microprocessor.

In processing step 51, the CDM1a25 or CDM2a27 is read.

FIG. 7 shows details of the processing of the subroutine Subb. Subb is a process in the case where a read request for the SM high reliability region 210 is generated from the MPa 22 and a mistake occurs. This subroutine is a process in the case where the requested control information does not exist on the snoop cache connected to the microprocessor when the microprocessor requests to read the control information in the high reliability area of the shared memory. When reading into the high reliability area, the same control information is read into both the own snoop cache memory and the paired snoop cache memory.

The snoop cache controller reads the requested control information into its own snoop cache memory. If the control information that needs to be written back to the shared memory exists at the read location, the control information is written back before the reading. The control information that needs to be written back is control information in which both the valid flag and the owner flag in the corresponding cache tag memory are On. Further, the snoop cache controller sends the snoop cache ID of the paired snoop cache to the shared bus,
Prompts the reading of the same control information of the paired snoop cache.

In processing step 55, it is checked whether the valid flag of CTM1a24 is On or Off. If it is On, the process proceeds to step 56. If it is Off, the process proceeds to the subroutine Subh58 of the processing step 58. Subroutine Subh58 is a read process from the SM high reliability area 210. In the reading process from the SM high reliability area 210, the CD of the SCa21
In the CDM2 of one different SC which is a pair of M1a25,
A copy of the same control information is stored.

In process step 56, it is checked whether the owner flag of CTM1a24 is On or Off. In the case of On, the process proceeds to the subroutine Subm57 of the processing step 57. Subroutine Subm57 is a process for writing back to SM19. In the case of Off, the process proceeds to the subroutine Subh588 of process step 58. After the subroutine Subm of processing step 57 ends,
The process proceeds to the subroutine Subh of the processing step 58. In the processing step 59, the cache data block of the CDM1a25 is rewritten with new contents. In process step 510, the valid flag of CTM1a24 is set to On. In process step 511, the shared flag of CTM1a24 is set to On.
In process step 512, the owner flag of CTM1a24 is turned off. CTM1a24 in processing step 513
Replace the address tag of with new contents.

FIG. 8 shows details of the processing of the subroutine Subc. Subc is a process when a write request to the SM high reliability area 210 is generated from the MPa 22 and hits.

This subroutine is a process when the microprocessor requests the writing of the control information in the high-reliability region of the shared memory, and the requested control information exists in the snoop cache connected to the microprocessor. .

When a write occurs in the cache data memory a, the snoop cache controller writes in its own snoop cache memory a. Furthermore, by sending the snoop cache ID to the shared bus, writing to the paired snoop cache memory b is prompted.

When a write occurs in the paired cache data memory b, the snoop cache controller writes in its own snoop cache memory b.
Furthermore, by sending the snoop cache ID to the shared bus, writing to the paired snoop cache memory a is prompted.

The processing differs depending on whether the writing is to the CDM1a25 or the CDM2a27 (517). CDM1
In the case of writing to a25, the process proceeds to the subroutine Subl of the processing step 518. Subroutine Subl518 is C
This is an update process for changing the ownership of TM2. CTM
In the update process for changing the ownership of item 2, the other S
The owner flag of CTM2 of C becomes On. CDM2a27
In the case of writing to, the process proceeds to the subroutine Subk of the processing step 521. Subroutine Subk521 is CTM
This is an update process for changing the ownership of item 1. In the update processing for changing the ownership of the CTM1, the owner flag of the CTM1 of the other SC forming a pair is set to On.

In the processing step 519, the cache data block of the CDM1a25 is rewritten with new contents. In process step 520, the owner flag of CTM1a24 is set to On. In the processing step 522, the cache data block of the CDM2a27 is rewritten with new contents. In process step 523, the owner flag of CTM2a26 is set to On.

FIG. 9 shows the details of the processing of the subroutine Subd. Subd is a process when a write request for the SM high reliability area 210 is generated from the MPa 22 and a mistake occurs.

This subroutine is a process in the case where the requested control information does not exist in the snoop cache connected to the microprocessor when the microprocessor requests the writing of the control information in the high reliability area of the shared memory. Is.

The snoop cache controller carries out a read miss process and a write hit process with respect to its own snoop cache memory 1.

Since the processing steps 62, 63, 64 and 65 are the same as the processing steps 55, 56, 57 and 58, the description thereof will be omitted. Subroutine Su in processing step 66
bl processing is performed. CDM1a25 in process step 67
Rewrite the cache data block of the new contents. In process step 68, the valid flag of CTM1a24 is set to On. In process step 69, the shared flag of CTM1a24 is set to On. CTM1 in processing step 610
Set the owner flag of a24 to On. Processing step 61
In 1, rewrite the address tag of CTM1a24 with new contents.

FIG. 10 shows details of the processing of the subroutine Sube. Subbe is a process in the case where a read request for the SM normal area 220 occurs from the MPa 22 and a mistake occurs.

This subroutine is the processing when the microprocessor requests the reading of the control information in the normal area of the shared memory and the requested control information does not exist in the snoop cache connected to the microprocessor. . When the normal area is read, the control information is read into its own snoop cache memory a, and the contents of the paired snoop cache memory b are invalidated.

The snoop cache controller reads the requested control information into its own snoop cache memory. If the control information that needs to be written back to the shared memory exists at the read location, the control information is written back before the reading. The control information that needs to be written back is control information in which both the valid flag and the owner flag in the corresponding cache tag memory are On. The snoop cache controller sends the snoop cache ID of the paired snoop cache to the shared bus to prompt the invalidation processing of the paired snoop cache.

In process step 615, it is checked whether the valid flag of CTM1a24 is On or Off. If it is On, the process proceeds to step 616. In the case of Off, the process proceeds to a subroutine Sub9 of processing step 618. Subroutine Subi is a read process from the SM normal area 220.

In process step 616, it is checked whether the owner flag of CTM1a24 is On or Off. In the case of On, the process proceeds to the subroutine Subm of processing step 617. In the case of Off, the process proceeds to the subroutine Sub9 of the processing step 618. After the subroutine Subm of the processing step 617 ends, the process proceeds to the subroutine Subi of the processing step 618.

In the processing step 619, the cache data block of the CDM1a25 is rewritten with new contents. In the processing step 620, the valid flag of CTM1a24 is turned on.
To In process step 621, the shared flag of CTM1a24 is set to On. CTM1a2 in process step 622
Set the owner flag of 4 to Off. Processing step 62
In 3, rewrite the address tag of CTM1a24 with new contents.

FIG. 11 shows details of the processing of the subroutine Subf. Subf is a process when a write request to the SM normal area 220 is generated from the MPa 22 and hits.

This subroutine is the processing when the microprocessor requests the writing of the control information in the normal area of the shared memory and the requested control information exists in the snoop cache connected to the microprocessor.

When writing to the normal area, the same control information of the other snoop cache is invalidated by sending an invalidation command to the shared bus. However, if the same control information does not already exist in the other snoop cache, the invalidating instruction is not sent again and the shared bus access becomes unnecessary. Whether the same control information does not exist in the other snoop cache can be known by checking the shared flag in the corresponding cache tag memory.

When writing to the SM normal area 220, there is a case where the shared flag indicating that there is no copy of the same control information in another CDM 1 is Off. In this case, access to the control common bus CBS18 becomes unnecessary.

In processing step 72, it is checked whether the shared flag of CTM1a24 is On or Off. If it is On, the process proceeds to step 73. If it is Off, the process proceeds to step 79. The processing steps 73 to 78 are the control common bus CBS.
This is processing when access to 18 is required. In the processing step 73, the control common bus CBS18 is acquired. In process step 74, the process of the subroutine Subj is performed. Subroutine Subj is a process for invalidating the copy of the same control information in another CDM 1. In processing step 75, the cache data block of CDM1a25 is rewritten with new contents. In process step 76, the shared flag of CTM1a24 is turned off. In process step 77, the owner flag of CTM1a24 is turned on.
In process step 78, the control common bus CBS18 is released. The processing step 79 is the common control bus CBS1.
This is processing when access to 8 is unnecessary. In processing step 79, the cache data block of CDM1a25 is rewritten with new contents.

FIG. 12 shows details of the processing of the subroutine Subg. Subg is a process when a write request for the SM normal area 220 is generated from the MPa 22 and a mistake occurs.

This subroutine is a process when the microprocessor requests the writing of the control information in the normal area of the shared memory and the requested control information does not exist in the snoop cache connected to the microprocessor. .

The snoop cache controller carries out a read miss process and a write hit process with respect to its own snoop cache memory 1.

Process Steps 715, 716, 717, 7
18 is the same as the processing steps 615, 616, 617, 618, and the description thereof will be omitted. In process step 719, the process of the subroutine Subj is performed. Processing step 7
At 20, the cache data block of CDM1a25 is rewritten with new contents. CT in process step 721
Set the valid flag of M1a24 to On. Processing step 722
At, the sharing flag of CTM1a24 is turned off. In process step 723, the owner flag of CTM1a24 is turned on.
To In processing step 724, the address tag of CTM1a24 is rewritten with new contents.

FIG. 13 shows the subroutine Subh, FIG. 14 shows the subroutine Subi, and FIG. 15 shows the subroutine Sub.
j, FIG. 16 shows the subroutine Subk, FIG. 17 shows the subroutine Subl, and FIG. 18 shows the details of the subroutine Subm.

Subh, Subi, Subj, Sub
k, Subl, and Subm indicate 6 types of access to the CBS 18. For each of the six types of access, a high reliability area read instruction, a normal area read instruction, an invalidation instruction, an update instruction for changing the ownership of CTM1, an update instruction for changing the ownership of CTM2, SM
There are 6 instructions of write back instruction.

FIG. 13 will be described below. Subroutine Subh is a read process from the SM high reliability area 210. In this subroutine, the requested control information is read into the snoop cache memory 1 in which a mistake has occurred, and at the same time, the same control information is read into the paired snoop cache memory 2.

SM to be accessed in processing step 82
The address of 19 is sent to the CBS 18. Processing step 8
In 3, the high reliability area read command is sent to the CBS 18. In process step 84, the partner SCID of SCIDRa29
322 is sent to the CBS 18. In process step 85, read data is received from CBS 18. Opponent SCID
In the other SC having the SCID equal to 322, the read data is stored in the CDM2.

FIG. 14 will be described below. Subroutine Subi is a read process from the SM normal area 220. In this subroutine, the requested control information is read into the snoop cache memory a in which a mistake has occurred, and at the same time, the contents of the paired snoop cache memory b are invalidated.

Access S in processing step 89
The address of M19 is sent to CBS18. In process step 810, a normal area read command is sent to the CBS 18. Opponent of SCIDRa29 in processing step 811
Send SCID322 to CBS18. Processing step 812
At, the read data is received from the CBS 18. In other SCs with SCID equal to the partner SCID322, CT
The valid flag of M2 is turned off and invalidated.

FIG. 15 will be described below. Subroutine Subj is a process for invalidating all copies of the same control information in another CDM 1. The address of the SM 19 to be accessed is sent to the CBS 18 in processing step 816. CB is issued in the processing step 817
Send to S18.

FIG. 16 will be described below. Subroutine Subk is an update process for changing the ownership of CTM1. This subroutine is an update process when writing to the cache data memory 2 occurs. In the cache control of the present embodiment, the snoop cache pair in which writing has occurred is the owner. The snoop cache pair that became the owner is responsible for writing back the latest control information to the shared memory and for sending the latest value to the shared bus in response to the control information read request sent to the shared bus. This subroutine updates the contents of the paired cache data memory 1 and further sets the owner flag to On.
Is the process of

In processing step 821, the address of SM19 to be accessed is sent to CBS18. In processing step 822, an update command for changing the ownership of CTM1 is sent to CBS18. In processing step 823, the own SCID 321 of SCIDRa 29 is sent to the CBS 18.
The update data is sent to the CBS 18 in process step 824.

As the partner SCID, the own SCID32 of SCIDRa29
The other SC having the SCID equal to 1 updates the cache data block of CDM1 and sets the owner flag of CTM1 to On.

FIG. 17 will be described below. Subroutine Subl is an update process for changing the ownership of CTM2. This subroutine is an update process when writing to the cache data memory 1 occurs. This subroutine is a process of updating the contents of the cache data memory 2 forming a pair and setting the owner flag thereof to On.

In processing step 828, the address of SM19 to be accessed is sent to CBS18. In processing step 829, an update command for changing the ownership of CTM2 is sent to CBS18. In process step 830, the partner SCID322 of SCIDRa29 is sent to the CBS 18. In the processing step 831, update data is updated to CBS1
8 is sent. SCI equal to SCID322 of SCIDRa29
In the other SC having D, the cache data block of CDM2 is updated and the owner flag of CTM2 is set to On.
To

FIG. 18 will be described below. Subroutine Subm is a process for writing back to SM19. In processing step 835, the address of SM19 to be accessed is sent to CBS18. In process step 836, an SM write back command is sent to CBS 18. In the processing step 837, the write-back data is sent to the CBS 18. Shared memory control circuit SM in process step 838
A write-back completion notification is received from C116 via the CBS 18.

FIG. 19 shows an SC based on the monitoring result of the CBS 18.
The main routine Main914 of the operation of Cb213 is shown. 6
Of the types of shared bus access, it is the five types of access other than shared memory write-back that the snoop cache controller needs to perform processing based on the monitoring result. The processing is different for each access.

In process step 92, the address of SM19 is obtained from CBS18. In process step 93, the command is obtained from CBS 18. In processing step 94, it is checked whether the instruction is a high reliability area read instruction. If it is a high reliability area read command, the processing of the subroutine Subn of processing step 95 is performed. Otherwise, it proceeds to processing step 96.

In processing step 96, it is checked whether the instruction is a normal area read instruction. If it is a normal area read command, the processing of the subroutine Subo of the processing step 97 is performed. Otherwise, it proceeds to processing step 98.

In processing step 98, it is checked whether the instruction is an invalidation instruction. If it is an invalidation command, processing step 99
Processing of the subroutine Subp. Otherwise, proceed to process step 910.

In processing step 910, the instruction is CT
It is checked whether it is an update command for changing the ownership of M1. C
If it is an update instruction for changing the ownership of TM1, the processing of the subroutine Subq of processing step 911 is performed. Otherwise, it proceeds to processing step 912.

In processing step 912, the instruction is CT
It is checked whether it is an update command for changing the ownership of M2. C
If it is an update instruction for changing the ownership of TM2, the processing of the subroutine Subr of processing step 913 is performed. Otherwise, the process ends. FIG. 20 shows the subroutine Su
Details of the bn processing are shown. Subroutine Subn is CB
This is a process when a high reliability area read command is obtained as a result of the monitoring in S18. When reading into the high reliability area, the same control information is read into both the own snoop cache memory 1 and the paired snoop cache memory 2.

As a result of acquiring the snoop cache ID from the shared bus and comparing it with the own snoop cache ID, if they are equal, it means that the control information of the high reliability area is read into the paired snoop cache memory 1. Therefore, the same control information is also read into its own snoop cache memory 2.

If the own snoop cache holds the latest value of the read-requested data, the contents are sent to the shared bus. Whether or not it is the latest value can be known by checking the owner flag in the corresponding cache tag memory.

In processing step 102, the SCID is acquired from the CBS 18. It is checked whether the SCID acquired in processing step 103 is equal to the own SCID 325 of SCIDRb 219. If they are equal, the process proceeds to step 104. If they are not equal, the process proceeds to step 105. When the SCID acquired as a result of the monitoring of the CBS 18 is equal to the own SCID 325 of the SCID Rb 219, it is necessary to store a copy of the control information of the SM high reliability area 210 in the paired CDM 2b 217.

In processing step 104, it is checked whether the owner flag of CTM1b 214 is On or Off. If On, go to process step 1012; if Off, process step 1012.
Go to 6.

In processing step 105, it is checked whether the owner flag of CTM1b 214 is On or Off. If On, go to processing step 1018; if Off, end processing.

When the owner flag of CTM1b214 is On,
This means that the latest control information is stored in the cache data block of CDM1b215 corresponding to CTM1b214.
Therefore, it is necessary to send the read data to the CBS 18. If there is no CTM1 whose owner flag is On, the read data is not sent from any SC. In this case, after a certain period of time, the SMC116 determines that the owner is absent, and the read data is sent from the SM19 to the CB via the SMC116.
It is sent to S18.

Processing steps 1012 to 1017
This is a case where both the processing of storing data in the CDM2b217 and the data transmission from the CDM1b215 to the CBS18 are required. In processing step 1012, the latest control information in CDM1b215 is stored in the cache data block of CDM2b217. In processing step 1013, the CTM2b216 valid flag is set to O.
set to n. In process step 1014, the shared flag of CTM2b216 is set to On. In process step 1015
Set the owner flag of CTM2b216 to Off. In processing step 1016, the address tag of CTM2b216 is rewritten with new contents. The read data is sent to the CBS 18 in process step 1017.

The processing steps 106 to 1011 are CDs.
This is the case when only the data storage process to M2b217 is required. In processing step 106, read data is acquired from the CBS 18. Read data from other SC or SMC116
This is the data sent from the CBS 18 to the CBS 18. In processing step 107, the cache data block of CDM2b217 is rewritten. In processing step 108, the valid flag of CTM2b216 is set to On. In process step 109
The shared flag of CTM2b216 is set to On. Processing step 10
In 10, the owner flag of CTM2b216 is turned off. In processing step 1011, the address tag of CTM2b216 is rewritten with new contents.

Process step 1018 is where it is only necessary to send the read data to the CBS 18. The above-mentioned processing is processing when no failure has occurred in the snoop cache memory. Under the condition that no failure has occurred, the snoop cache memory 1 as the owner sends the read data of the high reliability area.

The processing when the snoop cache memory 1 which is the owner fails and the read data in the high reliability area cannot be transmitted will be described below. In this case, the read data is sent from the snoop cache memory b paired with the failed snoop cache memory a.

When reading the control information of the high reliability area, SC
It is assumed that the failure occurrence flag 2328 of the IDRb 219 is On and a failure occurs in the paired snoop cache memory a when the data is duplicated and stored in the CDM 2b217. In such a situation, it is impossible to send the read data in the high-reliability area, which was owned by the snoop cache memory a. Therefore, the pair of snoop cache memories 1, CDM2b217, sends out read data instead. When the address tag of CTM2b216 is equal to the address sent to CBS18 and both the owner flag and the valid flag are On, the contents of the corresponding cache data block of CDM2b217 is sent to CBS18.

FIG. 21 shows details of the processing of the subroutine Subo. Subroutine Subo is a process when a normal area read command is obtained as a result of monitoring of CBS 18. When the normal area is read, the control information is read into its own snoop cache memory a, and the contents of the paired snoop cache memory b are invalidated.

As a result of acquiring the snoop cache ID from the shared bus and comparing it with its own snoop cache ID, if they are equal, it means that the control information of the normal area is read into the paired snoop cache memory a. Therefore, the contents of its own snoop cache memory b are invalidated. If the own snoop cache holds the latest value of the data requested to be read, the contents are sent to the shared bus. Whether or not it is the latest value can be known by checking the owner flag in the corresponding cache tag memory.

CBS 18 in process step 1102
To get the SCID. It is checked whether the SCID acquired in processing step 1103 is equal to the own SCID 325 of SCID Rb219. If they are equal, the process proceeds to step 1104.
If they are not equal, the process proceeds to processing step 1105.

The control information of the normal area is stored only in the CDM1, and the cache data block of the paired CDM2 is invalidated. SCI acquired as a result of CBS18 monitoring
If D is equal to the own SCID 325 of SCID Rb219, the cache data block of CDM2b217 needs to be invalidated.

In processing step 1104, it is checked whether the owner flag of CTM1b 214 is On or Off. If On, go to processing step 1106; if Off, processing step 11
Proceed to 07.

In process step 1105, it is checked whether the owner flag of CTM1b214 is On or Off. If On, go to processing step 1110, and if Off, end processing.

When the owner flag of CTM1b214 is On,
This means that the latest control information is stored in the cache data block of CDM1b215 corresponding to CTM1b214.
Therefore, it is necessary to send the read data to the CBS 18.

Process Steps 1106, 1108, 110
In No. 9, it is a case where both the processing of invalidating the CDM2b217 and the data transmission from the CDM1b215 to the CBS18 are necessary. In processing step 1106, the valid flag of CTM2b216 is turned off. In processing step 1108, the sharing flag of CTM1b 214 is set to On. The read data is sent to the CBS 18 in process step 1109. Processing step 11
In 07, it is a case where only the invalidation of CDM2b217 is necessary. In processing step 1107, the valid flag of CTM2b216 is set to 0.
ff

In processing steps 1110 and 1111, it is only necessary to send the read data to the CBS 18. In processing step 1110, the sharing flag of CTM1b 214 is set to On. The read data is sent to the CBS 18 in process step 1111.

FIG. 22 shows the details of the processing of the subroutine Subp. Subroutine Subp is a process when an invalidation command is obtained as a result of monitoring of CBS 18. If the control information to be invalidated exists in the snoop cache memory 1, it is invalidated by turning off the corresponding valid flag. The presence or absence of the corresponding control information is checked by comparing the corresponding address tag with the address sent to the shared bus.

At processing step 1115, CTM1b214
Address tag and processing step 9 of Main914 in FIG.
In step 2, the address of SM19 acquired as a result of monitoring of CBS18 is compared. In processing step 1116,
If there is an equal address as a result of the comparison, the process proceeds to processing step 1117, and if not, the process ends. In processing step 1117, the validity flag of CTM1b214 is set to Of.
f to invalidate.

FIG. 23 shows details of the processing of the subroutine Subq. Subroutine Subq is a process when an update command for changing the ownership of CTM1 is obtained as a result of monitoring of CBS 18. If the control information to be updated exists in the own snoop cache memory 1 or 2, the memory contents are rewritten to the latest value sent to the shared bus. The presence or absence of the corresponding control information is checked by comparing the corresponding address tag with the address sent to the shared bus. Also, the snoop cache I sent to the shared bus
D is checked, and as a result, the owner flag of the cache tag memory 1 is set to On or Off.

In processing step 122, CTM1b214,
The address tag of CTM2b216 and the result of monitoring the CBS 18 were acquired in the processing step 92 of Main914 of FIG.
Compare with SM19 address. In processing step 123, if there is an equal address as a result of comparison, the process proceeds to processing step 124, and if not, the process ends.

In processing step 124, the CBS 18
Get more SCID. In processing step 125, C
Update data is acquired from BS18. Processing step 12
In 6, the cache data blocks of CDM1b215 and CDM2b217 are rewritten with new contents.

SC obtained in processing step 127
It is checked whether the ID is equal to the partner SCID326 of SCIDRb219.
If they are equal, the process proceeds to processing step 128, and if they are not equal, the processing proceeds to processing step 129.

In the processing step 128, it means that the CDM2 of the other SC paired with the CDM1b215 has become the owner. Therefore, only when there is a valid copy of the control information in CDM1b215, the owner flag of CTM1b214 is set to O.
n, in all other cases, set to Off, and the process ends.

The processing step 129 means that the CDM2 of another SC unrelated to the CDM1b215 has become the owner. Therefore, set the owner flag of CTM1b214, CTM2b216
Set to Off, and the process ends.

FIG. 24 shows details of the processing of the subroutine Subr. Subroutine Subr is a process when an update command for changing the ownership of CTM 2 is obtained as a result of monitoring CBS 18. If the control information to be updated exists in the own snoop cache memory a or b, the content of the memory is rewritten to the latest value sent to the shared bus. The presence or absence of the corresponding control information is checked by comparing the corresponding address tag with the address sent to the shared bus. Also, the snoop cache I sent to the shared bus
D is checked, and as a result, the owner flag of the cache tag memory b is set to On or Off.

Since the processing steps 132 to 136 are the same as the processing steps 122 to 126, the description thereof will be omitted.

SC acquired in process step 137
It is checked whether the ID is equal to the own SCID325 of SCIDRb219. If they are equal, the process proceeds to step 138, and if they are not equal, the process proceeds to step 139.

In the processing step 138, it means that the CDM1 of the other SC paired with the CDM2b217 has become the owner. Therefore, only when there is a valid copy of the control information in CDM2b217, the owner flag of CTM2b216 is set to O.
n, in all other cases, set to Off, and the process ends.

The processing step 139 means that the CDM1 of another SC unrelated to the CDM2b217 has become the owner. Therefore, set the owner flag of CTM1b214, CTM2b216
Set to Off, and the process ends.

FIG. 25 and FIG. 26 show the details of the writing process to the SM high reliability area 210 when a failure occurs. SC
It is assumed that the failure occurrence flag 1323 or the failure occurrence flag 2324 of IDRa29 is On, and a failure occurs in the paired snoop cache when the data is duplicated and stored in the CDM 1a25 or the CDM2a 27. In such a situation, it is impossible to duplicate the copy of the control information in the CDM1a25 or CDM2a27. Therefore, reliability is maintained by always writing back to the SM 19 when writing occurs.

In the case of high reliability area, write, and hit,
After obtaining the CBS 18, the subroutine Subc'1412 of FIG. 25 is processed, and then the CBS 18 is released. The process differs depending on whether the writing is to CDM1a25 or CDM2a27. In the case of writing to the CDM1a25, the process proceeds to the subroutine Subl of the processing step 143. In processing step 144, the subroutine Sub
m processing is performed. CDM1a25 in process step 145
Rewrite the cache data block of the new contents. In process step 146, the owner flag of CTM1a24 is turned off, and the process ends.

When writing to the CDM2a27, the process proceeds to the subroutine Subk of the processing step 147. In process step 148, the process of the subroutine Subm is performed.
In processing step 149, the cache data block of the CDM 2a27 is rewritten with new contents. In process step 1410, the owner flag of CTM2a26 is set to Of.
f, and the process ends.

High reliability area, writing, C in case of mistake
After the BS 18 is acquired, the process of the subroutine Subd 'of FIG. 26 is performed, and then the CBS 18 is released.

Process Steps 1414, 1415, 141
6, 1417 is the same as the processing steps 55, 56, 57, 58, and therefore its explanation is omitted. In process step 1418, the process of the subroutine Subl is performed. In process step 1419, the process of the subroutine Subm is performed.
In processing step 1421, the cache data block of the CDM1a25 is rewritten with new contents. In process step 1422, the valid flag of CTM1a24 is set to On.
In process step 1423, the sharing flag of CTM1a24 is set to On. In process step 1424, the owner flag of CTM1a24 is turned off. Processing step 1425
At, the address tag of CTM1a24 is rewritten with new contents, and the process ends.

27 and 28, SM19 at the time of failure occurrence
The details of the write-back processing to are shown below.

Main 1519 in FIG. 27 shows details of the control information write-back process in the CDM 1a25. It is assumed that the failure occurrence flag 1323 of SCIDRa29 is On and a failure occurs in a pair of snoop caches when the data is duplicated and stored in the CDM1a25. In this situation, CDM1a2
Duplication of control information in 5 is impossible. Therefore, the latest owner flag 33 of the CTM 1a24 existing only in the CDM 1a25 writes the On control information back to the SM 19 to maintain reliability.

In processing step 152, it is checked whether all owner flags of CTM1a24 are On or Off. All O
If it is ff, the processing is ended, and if there is On, processing step 1
Proceed to 53. In process step 153, the control common bus CBS 18 is waited for until it becomes empty. In process step 154, the CBS 18 is obtained. In process step 155, the process of the subroutine Subm is performed. Processing step 1
At 56, the owner flag of CTM1a24 is turned off. In the processing step 157, the CBS 18 is released and the process proceeds to the processing step 152 again.

Main 1530 in FIG. 28 shows details of the control information write-back processing in the CDM 2a27. It is assumed that the failure occurrence flag 324 of SCIDRa29 is On and a failure occurs in the paired snoop caches when the data is duplicated and stored in the CDM2a27. In this situation, the CDM2a27
It is not possible to duplicate the copy of the control information inside. Therefore, the latest owner flag 38 of the CTM 2a 26 existing only in the CDM 2a 27 writes the control information of On back to the SM 192 to maintain reliability.

In processing step 1512, CTM2a26
Check whether all owner flags of are on or off. If all are Off, the process ends, and if On is present, the process proceeds to process step 1513. In process step 1513, the control common bus CBS 18 is waited for until it becomes empty. In process step 1514, the CBS 18 is obtained. In process step 1515, the process of the subroutine Sub13 is performed. In process step 1516, the owner flag of CTM2a26 is turned off. In processing step 1517, C
The BS 18 is released, and the process again proceeds to the processing step 1512.

In the present embodiment, the invalidation type and update type coincidence control methods are switched depending on the degree of reliability required for data. Then, in update-type matching control, the same data is always placed in two or more local cache memories.

On the other hand, even when the update-type matching control is used for all the control information existing in the local cache memory, the same method as in the present embodiment is used, and the update information is always stored in two or more local cache memories. It is possible to put the same data.

[0140]

As described above, according to the present invention, in the shared bus type parallel processor system using the snoop cache, the reliability of the data stored in the snoop cache is improved, and the failure / power failure of the snoop cache occurs. The probability of data loss over time can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a control system of a data processing device using a snoop cache according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a data processing device using a snoop cache according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a cache tag memory and a cache data memory according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a snoop cache ID register according to an embodiment of the present invention.

FIG. 5 is a flowchart showing a main routine of one embodiment of the present invention.

FIG. 6 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 7 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 8 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 9 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 10 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 11 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 12 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 13 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 14 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 15 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 16 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 17 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 18 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 19 is a flowchart showing a main routine of one embodiment of the present invention.

FIG. 20 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 21 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 22 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 23 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 24 is a flowchart showing a subroutine of an embodiment of the present invention.

FIG. 25 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 26 is a flowchart showing a subroutine of one embodiment of the present invention.

FIG. 27 is a flowchart showing a main routine of one embodiment of the present invention.

FIG. 28 is a flowchart showing the main routine of one embodiment of the present invention.

FIG. 29 is a block diagram showing the configuration of a conventional data processing device.

FIG. 30 is an explanatory diagram showing characteristics of the operation of the data processing device according to the embodiment of the present invention.

[Explanation of symbols]

18 ... Common bus for control, 19 ... Shared memory, 21 ... Snoop cache a, 22 ... Microprocessor a, 23
... Snoop cache control circuit a, 24 ... Cache tag memory 1a, 25 ... Cache data memory 1a, 2
6 ... Cache tag memory 2a, 27 ... Cache data memory 2a, 28 ... Address checker a, 29 ... Snoop cache ID register a, 116 ... Shared memory control circuit, 210 ... Shared memory high reliability area, 211 ...
Snoop cache b, 212 ... Microprocessor b, 213 ... Snoop cache control circuit b, 214 ...
Cache tag memories 1b, 215 ... Cache data memories 1b, 216 ... Cache tag memories 2b, 21
7 ... Cache data memory 2b, 218 ... Address checker b, 219 ... Snoop cache ID register b, 220 ... Shared memory normal area.

Claims (7)

[Claims] 1. A plurality of processors are connected to a shared bus and a shared memory via each local cache memory and a cache control device provided for each local cache memory, and each local cache memory has a shared memory. Part of or all of the data stored in the cache controller is stored, and the cache controller constantly monitors the signals sent to the shared bus. Based on the monitoring result and the request from the processor connected to the cache controller, a plurality of local caches are cached. In a data processing device including a shared bus and a shared memory for performing coincidence control of the content of the shared data when the content of the data shared between the memories is changed, the shared memory area is a highly reliable area by an address. And divided into a normal area and the area provided for each local cache memory In the cache controller, the data for which the read and write requests from the processor, whether belonging to the said normal region belongs to a trusted region, means for determining from said address, by the determination means,
When it is determined to write to the data belonging to the high-reliability area of the shared memory, all the same shared data are also changed in the same manner, and the determining means determines the normal area of the shared memory. A data processing device, which is provided with a means for coincidence control that invalidates all the same shared data when it is determined to write to the data belonging to. 2. The data processing device according to claim 1, wherein
A unique identification number is set for each local cache memory, and the address of the shared memory is changed by the cache control device A of the local cache memory A, and the shared memory changed by the processor A connected to the local cache memory A. Data, an instruction to the shared memory, an instruction to a cache control device other than the cache control device A, an identification number n of a local cache memory B different from the local cache memory A,
Means for transmitting a part or all of the identification number m of the local cache memory A to the shared bus, and the cache control device B of the local cache memory B.
Is the address of the shared memory sent from the cache control device A to the shared bus, the data of the shared memory modified by the processor A connected to the local cache memory A, the instruction to the shared memory, An instruction to a cache control device other than the cache control device A, the local cache memory A
Means for confirming a part or all of the identification number n of the local cache memory B different from the identification number m of the local cache memory A, and as a result of the confirmation, the cache control device B causes the local cache memory B On the other hand, the data processing device is provided with means for storing data having the same content as that of the local cache memory A or for making the same change as the change of the content of the local cache memory A or invalidating the data. 3. A plurality of processors are connected to a shared bus and a shared memory via each local cache memory and a cache controller provided for each local cache memory, and each local cache memory has a shared memory. Part of or all of the data stored in the cache controller is stored, and the cache controller constantly monitors the signals sent to the shared bus. Based on the monitoring result and the request from the processor connected to the cache controller, a plurality of local caches are cached. When the content of the data shared between the memories is changed, in the data processing device provided with the shared bus and the shared memory for performing coincidence control of the content of the shared data, writing to the data of the local cache memory occurs. If all of the same shared data changes as well And a unique identification number for each local cache memory, and the cache controller A of the local cache memory A changes the address of the shared memory by the processor A connected to the local cache memory A. Data of the shared memory, an instruction for the shared memory, an instruction for a cache control device other than the cache control device A, an identification number n of a local cache memory B different from the local cache memory A, and an identification number m of the local cache memory A. Means for sending a part or all of the local cache memory to the shared bus; and the cache controller B of the local cache memory B, the address of the shared memory sent from the cache controller A to the shared bus, the local Cash memo Data of the shared memory changed by the processor A connected to A, an instruction for the shared memory, an instruction for a cache controller other than the cache controller A, identification of a local cache memory B different from the local cache memory A Number n, a means for confirming a part or all of the identification number m of the local cache memory A, and as a result of the confirmation, the cache control device B
A data processing apparatus, comprising: means for storing data having the same content as that of the local cache memory A or making the same change to the content of the local cache memory A in the local cache memory B. 4. The data processing apparatus according to claim 2, wherein the local cache memory is divided into a memory 1 and a memory 2, and the local cache memory A is a pair of the memories 1 belonging to the local cache memory A. A memory 2 belonging to the local cache memory B different from that of the local cache memory B is defined, and both of the memory 1 of the local cache memory A and the memory 2 of the paired local cache memory B are written at the time of writing data in the shared memory A data processing device comprising means for storing. 5. The data processing device according to claim 2, 3 or 4, wherein the local cache memory A is provided.
One of the pair of the local cache memories B has a failure, which makes it impossible to store the data, and the remaining one of the local cache memories stores the other data in the shared memory. A data processing device comprising means for sending the data to the shared bus from the cache control device of the remaining one local cache memory when a read request is issued from the microprocessor. 6. The data processing apparatus according to claim 2, 3 or 4, wherein the local cache memory A is provided.
One of the pairs of the local cache memory B has failed, data cannot be stored, and the data in the shared memory stored in the remaining one of the local cache memories has been changed. In this case, from the cache control device of the local cache memory,
A data processing device, characterized in that the change contents are written back to the shared memory by providing a means for sending a write back command to the shared memory and the changed contents to the shared bus. 7. The data processing device according to claim 2, 3 or 4, wherein an owner flag indicating whether or not the data is newer than the contents of the shared memory is provided for each data in the local cache memory. When a failure occurs in one of the pair of the memory 1 of the local cache memory A and the memory 2 of the local cache memory B, and the data cannot be stored, the remaining one of the local caches is stored. The cache controller of the cache memory checks the owner flag,
The means for finding data having a newer content than the content of the shared memory among the data of the shared memory stored in the local cache memory, and the cache control device of the one remaining local cache memory, A command for writing back to the shared memory, from the cache control device of the local cache memory, all the data stored in the local cache memory and having a newer content than the content of the shared memory. , And a means for sending the changed contents to the shared bus, thereby providing means for writing back to the shared memory by utilizing the idle time of the shared bus.