JPH0897529A - Surface mounting circuit board and manufacturing method thereof - Google Patents
Surface mounting circuit board and manufacturing method thereofInfo
- Publication number
- JPH0897529A JPH0897529A JP26781894A JP26781894A JPH0897529A JP H0897529 A JPH0897529 A JP H0897529A JP 26781894 A JP26781894 A JP 26781894A JP 26781894 A JP26781894 A JP 26781894A JP H0897529 A JPH0897529 A JP H0897529A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- conductor film
- lead
- circuit board
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】
【目的】 マザーボートとの接続状態が簡単に確認で
き、しかも製造工程が非常に簡単な表面実装用回路基板
及びその製造方法を提供する。
【構成】裏面Bと端面Eとの成す稜線部分に傾斜面Cを
形成したセラミック基板(積層体)1に所定回路を形成
するとともに、前記所定回路1の導出用導体膜6がセラ
ミック基板1の裏面Bから傾斜面Cに形成している。
(57) [Abstract] [Purpose] To provide a surface mounting circuit board and a manufacturing method thereof, in which a connection state with a mother boat can be easily confirmed and a manufacturing process is very simple. [Structure] A predetermined circuit is formed on a ceramic substrate (laminate) 1 in which a sloping surface C is formed at a ridgeline portion formed by a back surface B and an end surface E, and a lead-out conductor film 6 of the predetermined circuit 1 is formed on the ceramic substrate 1. The back surface B is formed to the inclined surface C.
Description
【0001】[0001]
【産業上の利用分野】本発明は、セラミック単板基板、
セラミック積層基板などの回路基板をマザーボードに表
面実装可能にするための接続端子を有する回路基板及び
その製造方法に関するものである。BACKGROUND OF THE INVENTION The present invention relates to a ceramic single plate substrate,
The present invention relates to a circuit board having connection terminals for enabling surface mounting of a circuit board such as a ceramic laminated board on a mother board and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来、例えば積層セラミック基板は、積
層体の内部に内部配線パターンが形成されており、積層
体の表面には表面配線パターン、厚膜抵抗体膜など形成
されており、さらに表面配線パターンの一部にICチッ
プ、チップ状電子部品などを接合しており、各種電子部
品を含む所定回路網が、積層体の内部、表面に渡って高
密度に配置されていた。2. Description of the Related Art Conventionally, for example, in a laminated ceramic substrate, an internal wiring pattern is formed inside the laminated body, and a surface wiring pattern, a thick film resistor film, etc. are formed on the surface of the laminated body. An IC chip, a chip-shaped electronic component, etc. are joined to a part of the wiring pattern, and a predetermined circuit network including various electronic components is arranged in high density inside and on the surface of the laminate.
【0003】このような積層セラミック基板をマザーボ
ードに接続するための構造として、積層体の裏面に所定
回路の一部と接続する導出用導体膜を形成して、この積
層セラミック回路基板の導出用導体膜とマザーボードの
所定配線パターンとを半田を介在させて平面的に当接す
ることによって表面実装していた。As a structure for connecting such a laminated ceramic substrate to a mother board, a lead-out conductor film for connecting with a part of a predetermined circuit is formed on the back surface of the laminate, and the lead-out conductor of this laminated ceramic circuit board is formed. Surface mounting is performed by abutting the film and a predetermined wiring pattern of the motherboard in a plane with solder interposed.
【0004】また、別の構造として、積層セラミック基
板の端面に、所定回路の一部と接続する導出用導体膜を
形成して、この積層セラミック回路基板の端面導出用導
体膜とマザーボードの所定配線パターンとを半田を介在
させて、端面導出用導体膜にはいあがる半田メニスカス
によって表面実装していた。As another structure, a lead-out conductor film for connecting to a part of a predetermined circuit is formed on the end face of the laminated ceramic substrate, and the end-face lead-out conductor film of the laminated ceramic circuit substrate and a predetermined wiring of the mother board. The pattern and the solder are interposed, and the surface mounting is performed by the solder meniscus rising on the end face lead-out conductor film.
【0005】尚、積層セラミック基板の端面導出用導体
膜として、大型積層体基板を分割した後に、分割端面に
端面導出用導体膜を形成する構造と、予め分割される部
分に貫通穴を形成しておき、この貫通穴の内壁に導電膜
を形成しておき、最終の分割工程で貫通穴の内面の導体
膜を2つ分割して端面導出用導体膜とする構造とがあっ
た。As a conductor film for leading out an end surface of a laminated ceramic substrate, a structure in which a conductor film for leading out an end face is formed on a divided end face after dividing a large-sized laminated substrate, and a through hole is formed in a portion to be divided in advance. There is a structure in which a conductive film is formed on the inner wall of the through hole, and the conductor film on the inner surface of the through hole is divided into two to form an end face lead-out conductor film in the final dividing step.
【0006】[0006]
【発明が解決しようとする課題】しかし、上述の基板の
裏面に導出用導体膜を形成した構造では、マザーボード
の配線パターンと導出用導体膜との半田接合が、実質的
に積層セラミック回路基板によって隠蔽されるため、半
田の接合状況を確認できず、接合信頼性に乏しかった。However, in the structure in which the lead-out conductor film is formed on the back surface of the above-mentioned substrate, the solder connection between the wiring pattern of the mother board and the lead-out conductor film is substantially made by the laminated ceramic circuit board. Since it was hidden, the soldering condition could not be confirmed and the bonding reliability was poor.
【0007】また、積層体の端面に導出用導体膜を形成
する場合においては、半田の接合状態、しかも半田メニ
スカスまでもが確認でき、接合信頼性が向上するもの
の、その端面導出用導体膜の形成するための製造工程が
非常に煩雑となったり、導出用導体膜が安定に形成でき
ないなどの問題があった。Further, in the case where the lead-out conductor film is formed on the end face of the laminated body, the soldering state and even the solder meniscus can be confirmed, and the joining reliability is improved, but the end face lead-out conductor film There are problems that the manufacturing process for forming is very complicated, and that the lead-out conductor film cannot be formed stably.
【0008】即ち、大型積層基板を分割した後に、端面
導出用導体膜を形成する構造においては、大型積層基板
を分割し、個々の積層セラミック基板を整列させて、そ
の端面に導体膜を形成する必要があり、非常に製造工程
が煩雑となる。That is, in the structure in which the conductor film for leading out the end face is formed after the large laminated substrate is divided, the large laminated substrate is divided, the individual laminated ceramic substrates are aligned, and the conductor film is formed on the end face. Therefore, the manufacturing process becomes very complicated.
【0009】また、大型積層基板に予め貫通穴を形成し
ておき、この貫通穴に導体膜を形成する場合、例えば、
導電性ペーストを貫通穴の一方側から吸引しながら印刷
しなければならず、導電性ペーストの粘度、吸引の条件
によって安定した導体膜が形成できない。また、貫通穴
の内面に導体膜は、その導体膜を引き裂き分断する方向
に分割されるため、剥離や一方側の積層体側にもってい
かれるなるの問題があった。When a through hole is previously formed in a large-sized laminated substrate and a conductor film is formed in this through hole, for example,
Printing must be performed while sucking the conductive paste from one side of the through hole, and a stable conductor film cannot be formed depending on the viscosity of the conductive paste and the suction conditions. Further, the conductor film on the inner surface of the through hole is divided in the direction in which the conductor film is torn and divided, so that there is a problem that the conductor film may be peeled off or brought to the side of the laminated body on one side.
【0010】本発明は上述の問題点に鑑みて案出された
ものであり、その目的は、マザーボートとの接続状態が
簡単に確認でき、しかも製造工程が非常に簡単な表面実
装用回路基板及びその製造方法を提供することにある。The present invention has been devised in view of the above-mentioned problems, and an object thereof is to easily confirm the connection state with a mother boat and to have a very simple manufacturing process. And to provide a manufacturing method thereof.
【0011】さらに別の目的は、上述の目的に加え、分
割処理において、導出用導体膜が安定的に達成すること
ができる表面実装用回路基板の製造方法を提供すること
にある。Still another object is to provide a method for manufacturing a surface mounting circuit board which can stably achieve a lead-out conductor film in a dividing process in addition to the above-mentioned object.
【0012】[0012]
【課題を解決するための手段】本発明の第1の発明は、
裏面と端面との成す稜線部分に傾斜面を形成したセラミ
ック基板に所望回路を形成するとともに、前記所望回路
の導出用導体膜をセラミック基板の裏面から前記傾斜面
に形成した表面実装用回路基板である。The first invention of the present invention is as follows:
A surface mounting circuit board in which a desired circuit is formed on a ceramic substrate in which a sloping surface is formed on a ridgeline portion formed by a back surface and an end surface, and a conductor film for deriving the desired circuit is formed on the sloping surface from the back surface of the ceramic substrate. is there.
【0013】第2の発明は、裏面と端面との成す稜線部
分に傾斜面を形成したセラミック基板に所望回路を形成
するとともに、前記所望回路の導出用導体膜をセラミッ
ク基板の裏面から傾斜面に形成した表面実装用回路基板
の製造方法であって、大型基板の表面側に分割溝、裏面
側にV溝を形成し、セラミック基板となる複数の領域に
区画する工程と、前記各領域に設けた所望回路の一部に
接続するようにして、各領域の裏面側からV溝に跨がっ
て導出用導体膜を形成する工程と、前記導出用導体膜が
形成された大型基板を、分割溝とV溝に沿って個々のセ
ラミック基板に分割処理する工程とを含む表面実装型回
路基板の製造方法である。According to a second aspect of the present invention, a desired circuit is formed on a ceramic substrate having an inclined surface formed on a ridge line formed by a back surface and an end surface, and a conductor film for deriving the desired circuit is formed on the inclined surface from the back surface of the ceramic substrate. A method of manufacturing a formed surface mounting circuit board, the method comprising: forming a dividing groove on a front surface side of a large-sized board and forming a V groove on a rear surface side of the large board to divide the area into a plurality of areas to be a ceramic board; The step of forming the lead-out conductor film across the V-groove from the back side of each region so as to connect to a part of the desired circuit and the large-sized substrate on which the lead-out conductor film is formed are divided. A method of manufacturing a surface-mounting type circuit board, which includes a step of dividing each ceramic board along a groove and a V groove.
【0014】第3の発明は、さらに、前記大型基板の裏
面に形成するV溝の先端に該V溝の開口角度に比較して
小さい開口角度を有する第2のV溝を形成する表面実装
型回路基板の製造方法である。A third aspect of the present invention is further a surface mount type in which a second V groove having an opening angle smaller than the opening angle of the V groove is formed at the tip of the V groove formed on the back surface of the large-sized substrate. It is a method of manufacturing a circuit board.
【0015】[0015]
【作用】第1の発明によれば、表面実装型回路基板の裏
面と端面との成す稜線部分が傾斜面となっており、裏面
から傾斜面にかけて導出用導体膜が形成されている。こ
のため、マザーボードの所定配線パターンに半田を接合
した場合、傾斜面の導出用導体膜に簡単に半田メニスカ
スが形成でき、強固に接合できるとともに、この半田の
接合状況が簡単に確認できるため、接合信頼性が向上す
る。According to the first aspect of the present invention, the ridge portion formed by the back surface and the end surface of the surface-mounted circuit board is an inclined surface, and the lead-out conductor film is formed from the back surface to the inclined surface. Therefore, when solder is joined to the predetermined wiring pattern of the mother board, a solder meniscus can be easily formed on the lead-out conductor film on the inclined surface to firmly join, and the joining situation of this solder can be easily confirmed. Improves reliability.
【0016】第2の発明によれば、各回路基板となる領
域を区画するV溝の形成と、このV溝を跨がって裏面に
導体膜を形成し、さらにV溝での分割処理によって、簡
単に形成することができ、従来のように製造工程が煩雑
となることがなく簡単に導出用導体膜を形成することが
できる。このため、回路基板の全体のコストが大きく低
下させることができる。According to the second aspect of the present invention, by forming the V-grooves for partitioning the regions to be the respective circuit boards, forming the conductor film on the back surface across the V-grooves, and further dividing by the V-grooves. Further, the lead-out conductor film can be easily formed, and the lead-out conductor film can be easily formed without complicating the manufacturing process as in the conventional case. Therefore, the overall cost of the circuit board can be significantly reduced.
【0017】また、分割処理時、導体膜が分割されるこ
とになるが、導体膜が平面的に折り曲げられるように切
断されるため、導体膜の剥離や一方側回路基板側に取ら
れることが有効に抑えられ、基板に対して安定的に被覆
した導出用導体膜となる。Further, the conductor film is divided during the dividing process, but since the conductor film is cut so as to be bent in a plane, the conductor film may be peeled off or may be peeled off on one side of the circuit board. The lead-out conductor film is effectively suppressed and stably covers the substrate.
【0018】さらに、第3の発明によれば、V溝(第1
のV溝)の先端部分に第2のV溝を形成したため、第1
のV溝の全面にわたり、導出用導体膜を導電性ペースト
に印刷形成した場合、第1のV溝と第2のV溝の稜線部
分で、導電性ペーストの流れ混みがペーストの表面張力
によって停止し、実質的に隣接する回路基板となる領域
の導出用導体膜と分離した状態で導体膜を形成すること
ができ、分割処理における導出用導体膜の剥離が皆無と
なる。Further, according to the third invention, the V groove (first
Since the second V groove is formed at the tip of the V groove),
When the lead-out conductor film is formed on the entire surface of the V groove by printing on the conductive paste, the flow tension of the conductive paste is stopped by the surface tension of the paste at the ridges of the first V groove and the second V groove. However, it is possible to form the conductor film in a state of being separated from the lead-out conductor film in the region which is substantially the adjacent circuit board, and there is no peeling of the lead-out conductor film in the dividing process.
【0019】[0019]
【実施例】以下、本発明を図面に基づいて詳説する。
尚、実施例には、積層セラミック回路基板を用いた回路
基板でもって説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.
It should be noted that the embodiments will be described using a circuit board using a laminated ceramic circuit board.
【0020】図1は第1の発明を説明するための積層セ
ラミック基板の断面図であり、図2はその裏面側斜視図
であり、図3はマザー基板の接合状況を示す側面図であ
る。FIG. 1 is a sectional view of a monolithic ceramic substrate for explaining the first invention, FIG. 2 is a rear perspective view thereof, and FIG. 3 is a side view showing a bonding state of a mother substrate.
【0021】積層セラミック基板10は、積層体1と、
該積層体1の表面側主面に形成された表面配線パターン
4・・・と、該表面配線パターン4・・・に搭載された
電子部品5と、積層体1の裏面側主面Bに形成された導
出用導体膜6・・・とから構成されている。The laminated ceramic substrate 10 includes the laminated body 1 and
Formed on the front surface side main surface B of the laminated body 1 and the surface wiring patterns 4 ... Formed on the front surface side main surface of the laminated body 1 and the electronic components 5 mounted on the front surface wiring pattern 4. And the derived conductor film 6 ...
【0022】積層体1は、例えば6層のセラミック層1
a〜1fからなり、各セラミック層間、1aと1b、1
bと1c・・・・1eと1fとの間には所定回路を構成
する内部配線パターン2b〜2f(総称して「2」と記
す。)が配置されている。また、セラミック層1a〜1
fには、その厚み方向を貫くビアホール導体3a〜3f
(総称して「3」と記す)が形成されている。The laminate 1 comprises, for example, 6 ceramic layers 1
a to 1f, each ceramic layer, 1a and 1b, 1
Internal wiring patterns 2b to 2f (collectively referred to as "2") forming a predetermined circuit are arranged between b and 1c ... 1e and 1f. Also, the ceramic layers 1a to 1
f is the via-hole conductors 3a to 3f that penetrate the thickness direction.
(Collectively referred to as “3”) is formed.
【0023】セラミック層1a〜1fは、例えば、アル
ミナ、窒化アルミニウム、ムライトなどのセラミック単
体、ガラス−セラミック、Mn−Zn、Ni−Zn(広
義でセラミックという)などの磁性体セラミック、Ba
TiO3 などの誘電体セラミック材料などから成り、内
部配線パターン2、ビアホール導体3は、Ag系(Ag
単体またはAgの合金)導体、Cu系(Cu単体または
Cuの合金)導体、Au系導体などからなる。The ceramic layers 1a to 1f are, for example, simple ceramics such as alumina, aluminum nitride and mullite, magnetic ceramics such as glass-ceramic, Mn-Zn and Ni-Zn (ceramics in a broad sense), Ba.
It is made of a dielectric ceramic material such as TiO 3, and the internal wiring pattern 2 and the via-hole conductor 3 are Ag-based (Ag.
A single or Ag alloy conductor, a Cu-based (Cu alone or Cu alloy) conductor, an Au-based conductor, and the like.
【0024】具体的には、ビアホール導体3となる導体
が貫通穴に充填され、且つ表面に内部配線パターン2と
なる導体膜が形成されたセラミックグリーンシートを積
層順序を考慮して積層し、一体的に焼成することによっ
て達成されるものである。Specifically, the ceramic green sheets having the conductors serving as the via-hole conductors 3 filled in the through holes and having the conductor film serving as the internal wiring pattern 2 formed on the surface are stacked in consideration of the stacking order, and integrated. It is achieved by calcination.
【0025】表面配線パターン4・・は、積層体1の表
面側主面に、ビアホール導体3aなどを介して内部配線
2と接続した配線パターンであり、例えば、Ag系(A
g単体またはAgの合金)導体、Cu系(Cu単体また
はCuの合金)導体、Au系導体などから成る。The surface wiring pattern 4 ... Is a wiring pattern which is connected to the internal wiring 2 through the via-hole conductor 3a on the main surface of the laminated body 1 on the front surface side.
g conductor or Ag alloy) conductor, Cu (Cu alone or Cu alloy) conductor, Au conductor, and the like.
【0026】また、電子部品5は、表面配線パターン4
の一部を接合用パッドとして、半田、導電性接着材など
を介して接合されており、電子部品として、ICベアチ
ッフ、トランジスタ、チップ抵抗器、チップコンデンサ
などが例示できる。The electronic component 5 has a surface wiring pattern 4
Some of them are bonded as a bonding pad via solder, a conductive adhesive, or the like, and examples of the electronic component include an IC bare chip, a transistor, a chip resistor, a chip capacitor, and the like.
【0027】本発明の特徴的なことは、積層体1は、そ
の裏面側主面Bと端面Eとの成す稜線部分に傾斜面Cが
形成されており、また、内部配線パターン2、ビアホー
ル導体3、表面配線パターン4、電子部品5などから成
る所定回路の入出力端子部分となる導出用導体膜6・・
が積層体1の裏面側主面Bから前記傾斜面Cにかけて形
成されている。A feature of the present invention is that the laminated body 1 has an inclined surface C formed on the ridge line portion formed by the back surface side main surface B and the end surface E, the internal wiring pattern 2, the via hole conductor. 3, the lead-out conductor film 6 serving as an input / output terminal portion of a predetermined circuit including the surface wiring pattern 4, the electronic component 5, etc.
Is formed from the back surface side main surface B of the laminated body 1 to the inclined surface C.
【0028】例えば、図1では導出用導体膜6は、ビア
ホール導体3fを介して内部配線パターン2b〜2fな
どの構成する所定回路に接続されている。For example, in FIG. 1, the lead-out conductor film 6 is connected to a predetermined circuit such as the internal wiring patterns 2b to 2f via the via-hole conductor 3f.
【0029】この導出用導体膜6は、Ag系、Cu系、
Au系導体からなり、積層体1の裏面側主面Bから前記
傾斜面Cを含む端面方向にかけて導電性ペーストを選択
的にスクリーン印刷して、導体塗膜を形成し、焼きつけ
処理をして形成される。The lead-out conductor film 6 is made of Ag-based, Cu-based,
A conductive paste made of an Au-based conductor is selectively screen-printed from the back-side main surface B of the laminate 1 toward the end surface including the inclined surface C to form a conductor coating film and baking treatment. To be done.
【0030】このように、積層体1の裏面側主面Bと端
面Eとが成す稜線部分の傾斜面Cに導出用導体膜6が形
成された積層セラミック回路基板10をマーザーボード
基板に接合した状態を図3に示す。尚、図3において、
30はマザーボードであり、31は所定配線パターンで
あり、32は半田である。In this way, the laminated ceramic circuit board 10 in which the lead-out conductor film 6 is formed on the inclined surface C of the ridge portion formed by the back surface side main surface B and the end surface E of the laminated body 1 is joined to the mother board. Is shown in FIG. In addition, in FIG.
Reference numeral 30 is a mother board, 31 is a predetermined wiring pattern, and 32 is solder.
【0031】図に示すように、マザーボード30の所定
配線パターン31上に、クリーム状半田を塗布して、こ
のクリーム状半田を塗布した所定配線パターン31に、
積層セラミック回路基板10の導出用導体膜6が当接す
るように配置して、リフロー炉などに投入して、クリー
ム状半田を溶融させ、徐冷することにより、所定配線パ
ターン31と導出用導体膜6・・・との間が半田32に
よって強固に接合されることになる。As shown in the figure, a cream-like solder is applied onto the predetermined wiring pattern 31 of the mother board 30, and the predetermined wiring pattern 31 onto which the cream-like solder is applied,
Arranged so that the lead-out conductor film 6 of the laminated ceramic circuit board 10 is in contact, and put into a reflow furnace or the like to melt the cream-like solder and gradually cool it so that the predetermined wiring pattern 31 and the lead-out conductor film are formed. 6 will be firmly joined by the solder 32.
【0032】特に、積層体1の裏面側主面Bと端面Eと
のなす稜線部分の傾斜面Cに形成された導出用導体膜6
・・・は、実質的にマザーボード30の所定配線パター
ン31に対して傾斜した状態となり、この間に楔状の隙
間が形成されることになる。In particular, the lead-out conductor film 6 formed on the inclined surface C of the ridgeline formed by the back surface side main surface B and the end surface E of the laminate 1.
Are substantially inclined with respect to the predetermined wiring pattern 31 of the mother board 30, and a wedge-shaped gap is formed therebetween.
【0033】しかし、実際には、溶融した半田32の表
面張力により、半田のメニスカスが安定的に形成される
ことになり、マザーボード30と積層セラミック回路基
板10との電気的接続及び一層強固な機械的接合が達成
されることになる。However, in reality, the meniscus of the solder is stably formed due to the surface tension of the molten solder 32, and the electrical connection between the mother board 30 and the monolithic ceramic circuit board 10 and the stronger mechanical strength. A physical bond will be achieved.
【0034】しかも、この半田メニスカスの形成状態を
積層セラミック回路基板10の外部から簡単に目視確認
できるため、接合信頼性が大きく向上する。Moreover, since the state of formation of the solder meniscus can be easily visually checked from the outside of the laminated ceramic circuit board 10, the joining reliability is greatly improved.
【0035】このような積層セラミック回路基板10の
製造方法を図4に基づいて説明する。尚、本製造方法は
大型セラミック基板から複数の積層セラミック回路基板
を抽出する多数個取りの製造方法を図4の工程図、及び
図5の主要工程における裏面側斜視図に基づいて説明す
る。A method of manufacturing such a laminated ceramic circuit board 10 will be described with reference to FIG. In this manufacturing method, a multi-cavity manufacturing method for extracting a plurality of laminated ceramic circuit boards from a large-sized ceramic board will be described with reference to the process diagram of FIG. 4 and the rear perspective view of the main process of FIG.
【0036】まず、図4の(a)工程〜(f)工程を行
い、積層セラミック回路基板の積層体となる複数の領域
を区画するように表面側に分割溝、裏面側に裏面と分割
端面との稜線部分を傾斜面となるようなV溝が夫々形成
され、且つ各領域の裏面側に各々の所定回路の一部が導
出された大型基板を形成する。First, steps (a) to (f) of FIG. 4 are performed to divide a plurality of regions to be a laminated body of a laminated ceramic circuit board into division grooves on the front surface side and back surfaces and division end surfaces on the back surface side. V-grooves are formed so that their ridges are inclined surfaces, and a part of each predetermined circuit is led out on the back side of each region to form a large substrate.
【0037】まず(a)の工程として、各セラミック層
1a〜1fとなるグリーンシートを用意する。First, in the step (a), green sheets to be the ceramic layers 1a to 1f are prepared.
【0038】次に、(b)の工程として、各グリーンシ
ートの最終的に積層体となる各領域内に、各セラミック
層1a〜1fの厚みを貫くビアホール導体3a〜3fと
なる貫通孔をパンチ加工などにより形成する。Next, in the step (b), punching through holes to be the via-hole conductors 3a to 3f penetrating the thickness of the ceramic layers 1a to 1f are punched in the respective regions of the green sheets to be finally laminated. It is formed by processing.
【0039】次に、(c)の工程として、この貫通孔に
ビアホール導体3a〜3fとなる導体を導電性ペースト
の充填により形成するとともに、各グリーンシート上
に、内部配線パターン2b〜2fとなる導体膜を導電性
ペーストの印刷により形成する。Next, in the step (c), conductors to be the via-hole conductors 3a to 3f are formed in the through holes by filling a conductive paste, and internal wiring patterns 2b to 2f are formed on each green sheet. The conductor film is formed by printing a conductive paste.
【0040】次に、(d)の工程として、このようなグ
リーンシートを積層順序に応じて積層する。これによ
り、図5に示す未焼成状態の大型積層基板50が達成さ
れる。Next, in the step (d), such green sheets are laminated in the order of lamination. As a result, the large-sized laminated substrate 50 in the unfired state shown in FIG. 5 is achieved.
【0041】図において、50は未焼成状態の大型積層
基板であり、30f・・・はビアホール導体3fとなる
導体の露出部であり、点線X・・・、Y・・・は、各領
域を区画する仮想線である。In the figure, 50 is a large-sized laminated substrate in an unfired state, 30f ... Is an exposed portion of the conductor to be the via-hole conductor 3f, and dotted lines X ..., Y ... It is a virtual line that divides.
【0042】次に、(e)の工程として、上述の大型積
層基板の表面に各領域を区画する分割溝を、裏面には最
終的に分割処理した時に傾斜面Cとなるように各領域を
区画するV溝及び分割溝を形成する。この状態を図6に
示す。図6で、大型積層基板50の裏面側主面Bの各領
域を区画する点線Y方向には、傾斜面CとなるV溝7を
形成し、裏面側主面の各領域を区画する点線X方向に
は、分割溝8を形成する。これは、各領域を区画する点
線X方向に、導出用導体膜を形成しないため、V溝が存
在しない。このため、後述の分割処理で分割性を高める
形成するものである。従って、例えば、点線X方向にも
導出用導体膜を形成する場合には、このX方向にもV溝
を形成することとなる。Next, in the step (e), a dividing groove for partitioning each region is formed on the front surface of the large-sized laminated substrate described above, and each region is formed on the back surface so as to become an inclined surface C when the final division processing is performed. A V-shaped groove and a dividing groove for partitioning are formed. This state is shown in FIG. In FIG. 6, a V groove 7 serving as an inclined surface C is formed in a dotted line Y direction that partitions each region of the back surface-side main surface B of the large-sized laminated substrate 50, and a dotted line X that partitions each region of the back surface-side main surface. The dividing groove 8 is formed in the direction. This is because the lead-out conductor film is not formed in the direction of the dotted line X that divides each region, so that there is no V groove. Therefore, the dividing process described later is performed to enhance the dividing property. Therefore, for example, when the lead-out conductor film is formed also in the dotted line X direction, the V groove is also formed in this X direction.
【0043】また、大型積層基板50の表面側主面の各
領域を区画するように縦横に分割溝9を形成する。Further, dividing grooves 9 are formed vertically and horizontally so as to partition each region of the main surface on the front surface side of the large-sized laminated substrate 50.
【0044】分割溝8、9は、刃先の断面形状が概略V
字状となったスナップ刃をプレス成型などによって、V
溝7は、刃先の断面形状が概略V字状となったダイシン
グソーを用いて形成する。尚、分割溝8、9も実質的的
にV字状の溝であるが、特に傾斜面Cを形成するための
溝7と区別するために、溝8、9を「分割溝」、溝7を
「V溝」と記す。The dividing grooves 8 and 9 have a V-shaped cross-sectional shape of the cutting edge.
V-shaped snap blade with press-molding
The groove 7 is formed by using a dicing saw whose cutting edge has a substantially V-shaped cross section. The dividing grooves 8 and 9 are also substantially V-shaped grooves, but in order to distinguish them from the groove 7 for forming the inclined surface C, the grooves 8 and 9 are referred to as “dividing groove” and groove 7. Is referred to as "V groove".
【0045】次に、(f)の工程として、分割溝8、
9、V溝7が形成された未焼成状態の大型積層基板50
を焼成処理を行う。これにより、グリーンシートは焼結
反応により各グリーンシートは強固に一体化し、導体膜
は内部配線パターン2b〜2fとなり、導体30fなど
はビアホール導体3a〜3fとなる。Next, in the step (f), the dividing grooves 8,
9, large-sized laminated substrate 50 in which the V groove 7 is formed in an unfired state
Is fired. As a result, the green sheets are firmly integrated by the sintering reaction, the conductor film becomes the internal wiring patterns 2b to 2f, and the conductor 30f becomes the via hole conductors 3a to 3f.
【0046】次に、図4の(g)工程〜(h)工程を行
い、少なくとも各領域の裏面側主面BからV溝7に跨が
り、且つ所定回路一部と接続する導出用導体膜6となる
導体膜60を形成する。この状態を図7に示す。Next, the steps (g) to (h) of FIG. 4 are performed, and the lead-out conductor film which extends from at least the back-side main surface B of each region to the V groove 7 and is connected to a predetermined circuit part. A conductor film 60 to be 6 is formed. This state is shown in FIG.
【0047】具体的には、(g)の工程として、まず、
焼成された大型積層基板50の表面側主面に、導電性ペ
ーストの印刷焼きつけにより表面配線パターン4を形成
する。なお、この時、同時に必要に応じて、その他の厚
膜回路素子、例えば厚膜抵抗体膜を形成してもよい。Specifically, as the step (g), first,
The surface wiring pattern 4 is formed on the main surface on the front surface side of the baked large-sized laminated substrate 50 by printing and baking a conductive paste. At this time, other thick film circuit elements, for example, thick film resistor films may be formed at the same time, if necessary.
【0048】次に、焼成された大型積層基板50の裏面
側主面Bに、導電性ペーストの印刷焼きつけにより導出
用導体膜6・・となる導体膜60を形成する。構造的に
は、各領域の裏面側主面Bに露出しているビアホール導
体3fと電気的に接続するように被覆するとともに、導
体膜60の一部がV溝7内に到るように形成する。尚、
図7では、V溝7を介して隣接する各領域に渡って共通
的に導体膜60を形成するために、導体膜60の中央部
付近がV溝7内に形成され、且つその両端部が夫々異な
る領域のビアホール導体3eを覆うように形成されてい
る。Next, a conductor film 60 to be the lead-out conductor film 6 is formed on the main surface B on the back surface side of the fired large-sized laminated substrate 50 by printing and baking a conductive paste. Structurally, the conductive film 60 is formed so as to be electrically connected to the via-hole conductor 3f exposed on the back-side main surface B of each region and a part of the conductor film 60 reaches the V-groove 7. To do. still,
In FIG. 7, in order to commonly form the conductor film 60 across the adjacent regions via the V groove 7, the vicinity of the central portion of the conductor film 60 is formed in the V groove 7, and both ends thereof are formed. It is formed so as to cover the via-hole conductors 3e in different regions.
【0049】次に、必要に応じて、表面処理工程である
(h)の工程をおこなう。即ち、各種電子部品5を表面
配線パターン4の所定位置に搭載して、各領域毎に所定
回路が構成されることになる。Next, the surface treatment step (h) is carried out, if necessary. That is, various electronic components 5 are mounted at predetermined positions on the surface wiring pattern 4, and a predetermined circuit is formed for each area.
【0050】最後に、図4の(i)の工程として、導出
用導体膜となる導体膜60が形成された大型積層基板5
0を、分割溝8、9とV溝7に沿って個々の積層セラミ
ック回路基板10に分割する。この状態を図8に示す。
これにより、隣接する両領域を区画するV溝7が分割さ
れて、傾斜面Cとなり、また、隣接する両領域を区画す
るV溝7を介して跨がって形成した導体膜60が2つに
分割されて、夫々導出用導体膜6となる。Finally, in the step (i) of FIG. 4, the large-sized laminated substrate 5 on which the conductor film 60 serving as the lead-out conductor film is formed.
0 is divided into individual monolithic ceramic circuit boards 10 along the dividing grooves 8 and 9 and the V groove 7. This state is shown in FIG.
As a result, the V-groove 7 partitioning the two adjacent regions is divided into the inclined surface C, and two conductor films 60 are formed across the V-groove 7 partitioning the two adjacent regions. To be the lead-out conductor film 6 respectively.
【0051】以上の各工程により形成される積層セラミ
ック回路基板10では、裏面側主面Bと端面Eとの成す
稜線部分の傾斜面Cは、大型積層基板50にV溝7が形
成され、且つこのV溝7を分割処理に2分することによ
って達成されるため、非常に簡単に形成することができ
る。また、裏面Bから傾斜面Cに渡って形成される導出
用導体膜6・・は、大型積層基板50の裏面側主面Bに
V溝7を覆うように導電性ペーストの印刷・焼きつけ
に、さらに、上述のように分割処理に2分することによ
って達成されるため、これもまた、非常に簡単に形成す
ることができる。In the laminated ceramic circuit board 10 formed by the above steps, the inclined surface C of the ridgeline portion formed by the back-side main surface B and the end surface E has the V groove 7 formed in the large-sized laminated board 50, and This is achieved by dividing the V-groove 7 into two parts for the dividing process, so that the V-groove 7 can be formed very easily. Further, the lead-out conductor film 6 formed on the back surface B to the inclined surface C is printed or printed with a conductive paste so as to cover the V groove 7 on the back surface side main surface B of the large-sized laminated substrate 50. Moreover, this is also very simple to form, as it is achieved by dividing the splitting process in two as described above.
【0052】これは、従来のように、分割処理した後に
その分割端面に印刷・焼きつけをおこなったり、また、
端面電極となる貫通孔を形成して、貫通孔の内壁に導体
膜を形成したりすることに比較して製造工程が非常に簡
略化される。As in the prior art, after the division processing, printing / baking is performed on the division end surface, or
The manufacturing process is greatly simplified as compared with forming a through hole to be an end face electrode and forming a conductor film on the inner wall of the through hole.
【0053】また、大型積層基板50を分割溝8とV溝
7とに沿って分割した時、従来のように導体膜の例えば
表面側から割くように切断されず、V溝7内に形成され
た導体膜60は平面的に折曲されるようにして切断され
るため、導体膜60の剥離がなく、また、一方側の積層
セラミック回路基板側に取られることがなく安定的に分
割される。When the large laminated substrate 50 is divided along the dividing groove 8 and the V groove 7, the large laminated substrate 50 is formed in the V groove 7 without being cut so as to be split from, for example, the front surface side of the conductor film as in the conventional case. Since the conductor film 60 is cut so as to be bent in a plane, the conductor film 60 is not peeled off and is stably separated without being taken by the laminated ceramic circuit board on one side. .
【0054】しかも、この工程が多数個取りの製造方法
であり、表面処理、即ち、各種電子部品5の搭載などを
大型積層基板上で処理できるので、電子部品5の実装効
率が向上させることができ、 非常に量産性に優れ、積
層セラミック回路基板のコストを低減することができ
る。Moreover, this process is a multi-piece manufacturing method, and the surface treatment, that is, the mounting of various electronic components 5 and the like can be performed on the large laminated substrate, so that the mounting efficiency of the electronic components 5 can be improved. Therefore, the mass productivity is excellent, and the cost of the laminated ceramic circuit board can be reduced.
【0055】ここで、V溝7の形状について検討する
と、V溝7内に安定的に導体膜60を形成されるための
形状として、裏面BとV溝7の傾斜面Cとの成す角θ1
は、120°〜150°(V溝7の先端部分の開口角度
60〜120°)が望ましい。Considering the shape of the V groove 7, the angle θ formed between the back surface B and the inclined surface C of the V groove 7 is a shape for stably forming the conductor film 60 in the V groove 7. 1
Is preferably 120 ° to 150 ° (opening angle 60 to 120 ° at the tip of the V groove 7).
【0056】尚、角θ1 が120°未満であると、傾斜
面Cの角度が急峻となり、裏面に導電性ペーストを印刷
して形成する導電膜した場合、単位あたりの投射影面積
が小さくなり、安定した膜厚の導体膜が形成されない。When the angle θ 1 is less than 120 °, the angle of the inclined surface C becomes steep, and when a conductive film is formed by printing a conductive paste on the back surface, the projected shadow area per unit becomes small. , A conductor film having a stable film thickness is not formed.
【0057】また、角θ1 が150°を越えると、マザ
ーボード30の所定配線パターン31上に載置した場
合、この配線パターン31と導出用導体膜6との間の楔
状の間隙が少なくなり、半田メニスカスの形成が減少し
てしまい、接合強度が充分得られなかったり、また半田
32の接合状態の確認が困難となってしまう。Further, when the angle θ 1 exceeds 150 °, when placed on the predetermined wiring pattern 31 of the mother board 30, the wedge-shaped gap between the wiring pattern 31 and the lead-out conductor film 6 becomes small, The formation of the solder meniscus is reduced, the bonding strength cannot be sufficiently obtained, and it becomes difficult to confirm the bonding state of the solder 32.
【0058】また、V溝7と分割溝の深さについて検討
すると、一般に積層セラミック回路基板の厚みは、0.
8〜1.0mmであり、V溝7の深さは0.2〜0.5
mmの範囲が望ましい。例えば、深さが0.2mm未満
となると、上述の<字状の間隙が小さくなり、また、
0.5mmを越えると、これに伴いV溝7の開口幅が大
きくなり、製造上に実用的ではない。When the depths of the V-groove 7 and the dividing groove are examined, generally, the thickness of the laminated ceramic circuit board is 0.
8 to 1.0 mm, and the depth of the V groove 7 is 0.2 to 0.5.
A range of mm is desirable. For example, when the depth is less than 0.2 mm, the above-mentioned <shaped gap becomes small, and
If it exceeds 0.5 mm, the opening width of the V-groove 7 increases accordingly, which is not practical in manufacturing.
【0059】さらに、表面側の分割溝9の深さは、V溝
7の深さ、積層体1の厚みによって変動するものであ
り、分割溝9とV溝7の深さの合計が、積層体1の厚み
全体の約30〜60%程度となるようにする。例えば、
厚み0.8mmの積層体1に対しては、V溝7の深さを
0.3mm、分割溝9の深さを基板全体の10%程度の
0.08mmとすれば、積層体1の厚み全体の約48%
程度となる。Further, the depth of the dividing groove 9 on the front surface side varies depending on the depth of the V groove 7 and the thickness of the laminated body 1, and the total depth of the dividing groove 9 and the V groove 7 is the lamination. It is about 30 to 60% of the total thickness of the body 1. For example,
If the depth of the V-groove 7 is 0.3 mm and the depth of the dividing groove 9 is 0.08 mm, which is about 10% of the entire substrate, for the laminate 1 having a thickness of 0.8 mm, the thickness of the laminate 1 About 48% of the whole
It will be about.
【0060】分割溝9とV溝7の深さの合計が、積層体
1の厚み全体の約30%未満であると、分割性が低下し
てしまい、例えば分割端面に凹凸などが発生してしま
う。If the total depth of the dividing grooves 9 and the V-grooves 7 is less than about 30% of the total thickness of the laminated body 1, the dividing property will be deteriorated and, for example, unevenness will occur on the dividing end faces. I will end up.
【0061】また、60%を越えると、例えば、表面配
線パターン4の形成時や導出用導体膜6・・・となる導
体膜60の形成時に、分割溝9とV溝7との間で分割さ
れてしまい、多数個取りの製造方法に製造の煩雑さを起
こすことになる。Further, when it exceeds 60%, for example, when the surface wiring pattern 4 is formed or when the conductor film 60 to be the lead-out conductor film 6 is formed, it is divided between the dividing groove 9 and the V groove 7. As a result, the manufacturing method for producing a large number of pieces causes complication of manufacturing.
【0062】尚、裏面側主面Bに形成した分割溝8に関
して、実質的にV溝7と同様の深さとすることが分割性
の点からして望ましい。The dividing groove 8 formed on the back side main surface B preferably has a depth substantially similar to that of the V groove 7 from the viewpoint of dividing property.
【0063】さらに、V溝7内に形成される隣接する回
路基板の領域の導出用導体膜6どうしは接合していない
ことが理想的である。これは、分割処理時に、導出用導
体膜6の剥がれなどが発生しないようにするためであ
り、また、分割処理前に必要に応じて導出用導体膜6の
表面にメッキ処理を行うことができるためである。Further, it is ideal that the lead-out conductor films 6 in the area of the adjacent circuit board formed in the V groove 7 are not joined. This is to prevent the lead-out conductor film 6 from peeling off during the dividing process, and the surface of the lead-out conductor film 6 can be plated if necessary before the dividing process. This is because.
【0064】本発明者らが種々検討した結果、図9の断
面図に示すように、V溝7の先端部分に、該V溝7の開
口角度よりも小さい開口角度の第2のV溝71形成する
ことにより、導出用導体膜6を隣接する回路基板の各領
域毎に接合させずに形成できることを見出した。As a result of various studies by the present inventors, as shown in the sectional view of FIG. 9, the second V-shaped groove 71 having an opening angle smaller than the opening angle of the V-shaped groove 7 is formed at the tip portion of the V-shaped groove 7. It has been found that, by forming the lead-out conductor film 6, the lead-out conductor film 6 can be formed without being joined to each region of the adjacent circuit board.
【0065】上述の製造方法で説明したように、V溝7
内の導出用導体膜6となる導体膜60は、導電性ペース
トをスクリーン印刷法で印刷している。この時、製版ス
クリーンやスキージがV溝7内の面に接触することは実
質的に不可能であり、実際の導体膜60は、基板の裏面
側主面BからV溝7にかけてスクリーン印刷する際、製
版スクリーンから透過した、また裏面側主面Bから流れ
込んだ導電性ペーストがV溝7の傾斜面Cに沿って流れ
て塗布されることによって形成される。As described in the above manufacturing method, the V groove 7 is formed.
The conductor film 60 to be the lead-out conductor film 6 is printed with a conductive paste by screen printing. At this time, it is practically impossible for the plate-making screen or the squeegee to come into contact with the surface in the V-groove 7, and the actual conductor film 60 is printed from the back side main surface B of the substrate to the V-groove 7 by screen printing. The conductive paste that has passed through the plate-making screen and that has flowed from the back-side main surface B flows along the inclined surface C of the V groove 7 and is applied.
【0066】ここで、V溝7の先端にさらに第2のV溝
71を形成することによって、V溝7の傾斜面Cに流れ
た導電性ペーストは、V溝7と第2のV溝71とのなす
稜線部分で、ペーストの表面張力作用により、流れ込み
が制止されることになる。Here, by forming the second V-groove 71 at the tip of the V-groove 7, the conductive paste flowing on the inclined surface C of the V-groove 7 is V-groove 7 and the second V-groove 71. At the ridgeline formed by and, the inflow is stopped by the surface tension action of the paste.
【0067】従って、V溝7内に形成される導出用導電
膜6となる導体膜60は、第2のV71を境界とし分離
された状態に形成される。Therefore, the conductor film 60 to be the lead-out conductive film 6 formed in the V groove 7 is formed in a separated state with the second V 71 as a boundary.
【0068】従って、焼成処理後、分割溝9、第2のV
溝71に沿ってY方向の分割をおこなっても、分割部分
である第2のV溝71には、導体膜60が塗布されてい
ないため、導出用導体膜6の剥離が一切起こらない。Therefore, after the firing process, the dividing groove 9 and the second V
Even if the Y direction is divided along the groove 71, the conductor film 60 is not applied to the second V groove 71 which is the divided portion, and therefore the lead-out conductor film 6 is not peeled at all.
【0069】また、導出用導電体膜6が分離して形成さ
れるため、分割処理前に非常に薄い半田濡れ性用被膜を
形成することができる。この半田濡れ性用被膜は半田濡
れ性を向上されるためのものであり、例えば半田被覆な
どが例示できる。この半田被覆の製造方法は、従来周知
の各種方法によって形成することができる。このように
半田濡れ性用被覆を形成しても、同一V溝7内で、互い
に分割される回路基板の領域に独立した導出用導体膜6
上に形成されているため、分割処理時において、この半
田濡れ性用被膜も安定的に分割することができる。尚、
半田被覆の方法としては、半田の金属成分を溶解させた
有機系溶液を用いて、導出用導体膜6の表面に析出させ
て乾燥する半田析出方法が好ましい。Further, since the lead-out conductor film 6 is formed separately, a very thin solder wettability film can be formed before the dividing process. This solder wettability coating is for improving solder wettability, and for example, solder coating can be exemplified. The solder coating can be manufactured by various conventionally known methods. Even if the solder wettability coating is formed in this way, the lead-out conductor film 6 independent in the area of the circuit board divided into the same V groove 7 is formed.
Since it is formed on the upper side, the solder wettability film can be stably divided during the dividing process. still,
As a method for coating the solder, a solder deposition method in which an organic solution in which a metal component of solder is dissolved is deposited on the surface of the lead-out conductor film 6 and dried is preferable.
【0070】尚、V溝7と第2のV溝71との稜線部分
で、導電性ペーストの流れ込みを制止させているため、
稜線部分の角度θ2 、導電性ペーストの粘度が重要とな
ってくる。種々実験を行った結果、導電性ペーストの粘
度が100〜300ポイズの範囲では、基板1の裏面側
主面BからV溝7に安定的に導電性ペーストが流れこ
み、基板1の裏面側主面BとV溝7との稜線部分で導体
膜60の膜厚が極端に薄くなることがなく、V溝7内に
略均一な導体膜60を形成することができる。The ridge line between the V groove 7 and the second V groove 71 blocks the inflow of the conductive paste.
The angle θ 2 of the ridge and the viscosity of the conductive paste are important. As a result of various experiments, when the viscosity of the conductive paste is in the range of 100 to 300 poise, the conductive paste steadily flows from the rear surface main surface B of the substrate 1 to the V groove 7, and the rear surface main surface of the substrate 1 The film thickness of the conductor film 60 does not become extremely thin at the ridge portion between the surface B and the V groove 7, and a substantially uniform conductor film 60 can be formed in the V groove 7.
【0071】このような粘度が100〜300ポイズの
導電性ペーストの場合、V溝7の傾斜面と第2のV溝7
1の傾斜面とが成す角度θ2 が125〜167.5°、
即ち、第2のV溝71の先端の開口角度が10〜35°
と設定するとことが望ましいことが判った。例えば開口
角度が35°を越えると、V溝7の傾斜面と第2のV溝
71の傾斜面とが成す角度θ2 が180°に近くなり、
導電性ペーストの制止効果を減少し、また、開口角度が
10°未満となると、第2のV溝71の開口幅が狭くな
り、導電性ペーストの制止効果があったとしても、逆表
面張力により、回路基板の領域の境界である第2のV溝
71の幅、例えば20μm程度を越えて、両者の導体膜
が一体化してしまう。In the case of such a conductive paste having a viscosity of 100 to 300 poise, the inclined surface of the V groove 7 and the second V groove 7 are formed.
The angle θ 2 formed by the inclined surface of 1 is 125 to 167.5 °,
That is, the opening angle of the tip of the second V groove 71 is 10 to 35 °.
It turns out that it is desirable to set. For example, when the opening angle exceeds 35 °, the angle θ 2 formed by the inclined surface of the V groove 7 and the inclined surface of the second V groove 71 becomes close to 180 °,
When the restraining effect of the conductive paste is reduced, and when the opening angle is less than 10 °, the opening width of the second V groove 71 becomes narrow, and even if the restraining effect of the conductive paste is exerted, the reverse surface tension causes If the width of the second V-groove 71, which is the boundary of the circuit board region, for example, about 20 μm is exceeded, both conductor films are integrated.
【0072】以上のように、製造方法においては、分割
処理前の大型積層基板の裏面側主面のV溝7には、既に
導出用導体膜6・・となる導体膜60を形成しておれば
よく、その限りにおいては、各工程の入れ換えを行った
り、省略などをおこなってもかまない。As described above, in the manufacturing method, the conductor film 60 serving as the lead-out conductor film 6 ... Is already formed in the V-groove 7 on the back-side main surface of the large-sized laminated substrate before the division treatment. As long as it is sufficient, the steps may be interchanged or omitted.
【0073】次に、単板のセラミック基板を用いた回路
基板を例を説明する。Next, an example of a circuit board using a single ceramic substrate will be described.
【0074】図10はその断面図ある。図において、セ
ラミック基板91の表面には、厚膜技法を用いて、形成
された導体膜92、94、絶縁膜93、必要に応じて抵
抗体膜などが形成され、さらに必要に応じて電子部品な
どか搭載されている。FIG. 10 is a sectional view thereof. In the figure, on the surface of a ceramic substrate 91, formed are conductive films 92 and 94, an insulating film 93, a resistor film, etc., if necessary, using a thick film technique, and further, an electronic component as necessary. And so on.
【0075】セラミック基板91の裏面側主面Bと端面
Eとの成す稜線部分には傾斜面Cが形成されおり、裏面
主面Bと傾斜面Cを利用して導出用導体膜6が形成され
ている。An inclined surface C is formed on a ridge portion formed by the back surface-side main surface B and the end surface E of the ceramic substrate 91, and the lead-out conductor film 6 is formed by utilizing the back surface main surface B and the inclined surface C. ing.
【0076】ここで、基板91の表面側の厚膜導体膜9
2などから成る所定回路と基板91の裏面主面の導出用
導体膜6との接続は、基板91の厚みを貫く導通スルー
ホール95(内壁面に導体膜が形成された貫通穴)やビ
アホール導体(導体が充填された貫通穴)が形成されて
いる。Here, the thick conductor film 9 on the front surface side of the substrate 91
The predetermined circuit composed of 2 or the like and the lead-out conductor film 6 on the back main surface of the substrate 91 are connected to each other through a conductive through hole 95 (a through hole having a conductor film formed on the inner wall surface) or a via-hole conductor. (Through hole filled with a conductor) is formed.
【0077】尚、充実の実施例の製造方法において、V
溝7は未焼成状態の大型積層基板50で形成していた
が、焼成した基板に、ダイヤモンドソーなどを用いてV
溝を形成してもよい。In the manufacturing method of the substantial embodiment, V
The groove 7 was formed on the large-sized laminated substrate 50 in an unfired state.
A groove may be formed.
【0078】さらに、上述の導出用導体膜6は、ビアホ
ール導体3fや導通スルーホール95などに接続して、
所定回路と電気的に接続し、且つマザーボードなどに機
械的に接続するものであるが、その他に、ビアホール導
体3fや導通スルーホール95などに接続に接続するこ
とがない、単にマザーボードに機械的に接続させるだけ
の目的の導体膜6を形成しても構わない。Further, the lead-out conductor film 6 is connected to the via-hole conductor 3f, the conductive through hole 95, etc.,
It is electrically connected to a predetermined circuit and mechanically connected to a mother board or the like, but is not mechanically connected to the via hole conductor 3f, the conductive through hole 95, or the like. You may form the conductor film 6 only for the purpose of connecting.
【0079】[0079]
【発明の効果】以上のように、本発明の表面実装型回路
基板によれば、表面実装型回路基板の裏面と端面との成
す稜線部分が傾斜面となっており、裏面から傾斜面にか
けて導出用導体膜が形成されている。このため、マザー
ボードの所定配線パターンに半田を接合した場合、傾斜
面の導出用端子膜に簡単に半田メニスカスが形成でき、
強固に接合できるとともに、この半田の接合状況が簡単
に確認できるため、接合信頼性が向上する。As described above, according to the surface-mounting type circuit board of the present invention, the ridge portion formed by the back surface and the end surface of the surface-mounting type circuit board is an inclined surface, and is led from the back surface to the inclined surface. A conductor film for use is formed. Therefore, when solder is joined to the predetermined wiring pattern of the mother board, a solder meniscus can be easily formed on the lead-out terminal film on the inclined surface,
Since it is possible to firmly bond and the bonding status of the solder can be easily confirmed, the bonding reliability is improved.
【0080】また、本発明の表面実装型回路基板の製造
方法によれば、各回路基板となる領域を区画するV溝の
形成と、このV溝を跨がって裏面に導体膜を形成し、さ
らにV溝での分割処理によって、簡単に形成することが
でき、従来のように製造工程が煩雑となることがなく簡
単に導出用導体膜を形成することができる。このため、
多数個取りの回路基板の製造方法に適し、全体のコスト
が大きく低下させることができる。Further, according to the method of manufacturing the surface mount type circuit board of the present invention, the V groove for partitioning the area to be each circuit board is formed, and the conductor film is formed on the back surface across the V groove. Furthermore, the lead-out conductor film can be easily formed by the dividing process in the V groove, and the lead-out conductor film can be easily formed without complicating the manufacturing process as in the conventional case. For this reason,
It is suitable for a method for manufacturing a multi-piece circuit board, and can significantly reduce the overall cost.
【0081】また、分割処理時、導体膜が分割されるこ
とになるが、導体膜が平面的に折り曲げられるように切
断されるため、導体膜の剥離や一方側回路基板側に取ら
れることが有効に抑えられ、基板に対して安定的に被覆
した導出用導体膜となる。Further, the conductor film is divided during the dividing process, but since the conductor film is cut so as to be bent in a plane, the conductor film may be peeled off or may be peeled off to one side circuit board side. The lead-out conductor film is effectively suppressed and stably covers the substrate.
【0082】さらに、V溝の先端部分にV溝の開口角度
よりも狭い開口角度の第2のV溝を形成したため、導出
用導体膜を形成するにあたり、V溝と第2のV溝部分の
稜線部分で、導電性ペーストの流れ込みを防止すること
ができる。これにより、V溝内の導出用導体膜を、各回
路基板の領域に分けて分離して形成することができるた
め、分割処理時の分割信頼性が一層向上することにな
る。Further, since the second V groove having an opening angle narrower than the opening angle of the V groove is formed at the tip portion of the V groove, the V groove and the second V groove portion are formed when the lead-out conductor film is formed. It is possible to prevent the conductive paste from flowing into the ridge portion. As a result, the lead-out conductor film in the V groove can be formed separately in the regions of the respective circuit boards, so that the dividing reliability during the dividing process is further improved.
【図1】本発明の表面実装型回路基板である積層セラミ
ック基板の部分断面図である。FIG. 1 is a partial cross-sectional view of a monolithic ceramic substrate which is a surface mount type circuit substrate of the present invention.
【図2】本発明の積層セラミック基板の裏面側の部分斜
視図である。FIG. 2 is a partial perspective view of the back surface side of the laminated ceramic substrate of the present invention.
【図3】本発明の積層セラミック基板をマザーボードに
接合した状態の部分側面図である。FIG. 3 is a partial side view showing a state where the laminated ceramic substrate of the present invention is bonded to a mother board.
【図4】第2の発明の製造方法を説明するための工程図
である。FIG. 4 is a process drawing for explaining the manufacturing method of the second invention.
【図5】主要製造工程における裏面側の部分斜視図であ
る。FIG. 5 is a partial perspective view of the back surface side in the main manufacturing process.
【図6】主要製造工程における裏面側の部分斜視図であ
る。FIG. 6 is a partial perspective view of the back surface side in the main manufacturing process.
【図7】主要製造工程における裏面側の部分斜視図であ
る。FIG. 7 is a partial perspective view of the back surface side in the main manufacturing process.
【図8】主要製造工程における裏面側の部分斜視図であ
る。FIG. 8 is a partial perspective view of the back surface side in the main manufacturing process.
【図9】第3の発明の製造方法を説明するための、主要
工程における断面図である。FIG. 9 is a cross-sectional view in the main process for explaining the manufacturing method of the third invention.
【図10】本発明の他の実施例を示す厚膜回路基板の部
分断面図である。FIG. 10 is a partial cross-sectional view of a thick film circuit board showing another embodiment of the present invention.
10・・・積層セラミック回路基板 1・・・・積層体 1a〜1f・・・・セラミック層 2・・・・内部配線パターン 3・・・・ビアホール導体 4・・・・表面配線パターン 5・・・・電子部品 6・・・・導出用導体膜 B・・・・裏面側主面 E・・・・端面 C・・・・傾斜面 10 ... Laminated ceramic circuit board 1 ... Laminated bodies 1a to 1f ... Ceramic layer 2 ... Internal wiring pattern 3 ... Via hole conductor 4 ... Surface wiring pattern 5 ...・ ・ Electronic parts 6 ・ ・ ・ ・ Leading conductor film B ・ ・ ・ ・ Back side main surface E ・ ・ ・ ・ End surface C ・ ・ ・ ・ Inclined surface
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 淳一 鹿児島県国分市山下町1番1号 京セラ株 式会社鹿児島国分工場内 (72)発明者 植村 浩樹 鹿児島県国分市山下町1番1号 京セラ株 式会社鹿児島国分工場内 (72)発明者 中村 成男 鹿児島県国分市山下町1番1号 京セラ株 式会社鹿児島国分工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Nakamura 1-1 Yamashita-cho, Kokubun-shi, Kagoshima Prefecture Kyocera Stock Company Kagoshima Kokubun Plant (72) Inventor Hiroki Uemura 1-1, Yamashita-cho, Kokubun-shi, Kagoshima Kyocera Stock company Kagoshima Kokubu factory (72) Inventor Shigeo Nakamura 1-1 Yamashita-cho, Kokubun-shi, Kagoshima Kyocera Stock company Kagoshima Kokubu factory
Claims (3)
形成したセラミック基板に所望回路を形成するととも
に、前記所望回路の導出用導体膜をセラミック基板の裏
面から前記傾斜面に形成したことを特徴とする表面実装
用回路基板。1. A desired circuit is formed on a ceramic substrate having an inclined surface formed on a ridge line formed by a back surface and an end surface, and a conductor film for deriving the desired circuit is formed on the inclined surface from the back surface of the ceramic substrate. Surface mount circuit board characterized by.
形成したセラミック基板に所望回路を形成するととも
に、前記所望回路の導出用導体膜をセラミック基板の裏
面から傾斜面に形成した表面実装用回路基板の製造方法
であって、 大型基板の表面側に分割溝、裏面側にV溝を形成し、セ
ラミック基板となる複数の領域に区画する工程と、 前記各領域に設けた所望回路の一部に接続するようにし
て、各領域の裏面側からV溝に跨がって導出用導体膜を
形成する工程と、 前記導出用導体膜が形成された大型基板を、分割溝とV
溝に沿って個々のセラミック基板に分割処理する工程と
を含む表面実装型回路基板の製造方法。2. A surface mounting in which a desired circuit is formed on a ceramic substrate having an inclined surface formed on a ridge line formed by a back surface and an end surface, and a conductor film for deriving the desired circuit is formed on the inclined surface from the back surface of the ceramic substrate. A method of manufacturing a circuit board for use, comprising: forming a dividing groove on a front surface side of a large-sized substrate and forming a V groove on a back surface side of the large-sized substrate to divide the area into a plurality of regions to be a ceramic substrate; Forming a lead-out conductor film from the back surface side of each region across the V-groove so as to connect to a part thereof; and a large-sized substrate on which the lead-out conductor film is formed,
A method of manufacturing a surface mount type circuit board, which comprises a step of dividing each ceramic board along a groove.
端に該V溝の開口角度に比較して小さい開口角度を有す
る第2のV溝を形成することを特徴とする請求項2に記
載の表面実装型回路基板の製造方法。3. The second V groove having an opening angle smaller than the opening angle of the V groove is formed at the tip of the V groove formed on the back surface of the large-sized substrate. A method for manufacturing the surface mount type circuit board as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26781894A JPH0897529A (en) | 1994-07-26 | 1994-10-31 | Surface mounting circuit board and manufacturing method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6-174217 | 1994-07-26 | ||
| JP17421794 | 1994-07-26 | ||
| JP26781894A JPH0897529A (en) | 1994-07-26 | 1994-10-31 | Surface mounting circuit board and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0897529A true JPH0897529A (en) | 1996-04-12 |
Family
ID=26495911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26781894A Pending JPH0897529A (en) | 1994-07-26 | 1994-10-31 | Surface mounting circuit board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0897529A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861588B2 (en) | 2002-07-16 | 2005-03-01 | Murata Manufacturing Co., Ltd. | Laminated ceramic electronic component and method of producing the same |
| JP2022048118A (en) * | 2020-09-14 | 2022-03-25 | エスティーマイクロエレクトロニクス エス.アール.エル. | Packaging semiconductor device with improved reliability and inspection capability and manufacturing method thereof |
-
1994
- 1994-10-31 JP JP26781894A patent/JPH0897529A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861588B2 (en) | 2002-07-16 | 2005-03-01 | Murata Manufacturing Co., Ltd. | Laminated ceramic electronic component and method of producing the same |
| JP2022048118A (en) * | 2020-09-14 | 2022-03-25 | エスティーマイクロエレクトロニクス エス.アール.エル. | Packaging semiconductor device with improved reliability and inspection capability and manufacturing method thereof |
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