JPH0897717A - Lock detection circuit for phase locked loop - Google Patents

Abstract

(57) [Abstract] [Purpose] Lock detection can be performed based on the reference signal and the comparison signal without the need for an external clock with a stable frequency, and even when the phase difference between the reference frequency and the comparison frequency changes. An object of the present invention is to provide a lock detection circuit of a phase locked loop that stably performs lock detection. A first counting means 1 for counting the number of pulses of the second signal f _v within one cycle of the first signal f _r; a first logic level if the number of pulses is 1; The determination means 2 that outputs two logic levels, the second counting means 3 that counts the second logic level output continuous period of the determination means 2 in the cycle of the first signal _fr , and the output of the determination means 2 is the first logic. In the case of the level, the first logic level is set. When the output of the determination means 2 is the second logic level, the first logic level is set when the second counting means 3 is below a predetermined value, and the second counting means 3 is set in the predetermined value. Second when crossed
And an output means 4 for outputting a logic level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase locked loop (PL).
L: Phase Locked Loop) relates to a lock detection circuit for detecting that it is locked at a desired frequency, and in particular, a phase locked loop used for a modulator of a mobile phone requires an external clock with a stable frequency. Instead, lock detection can be performed based only on the reference signal and the comparison signal, and even if the phase difference between the reference frequency and the comparison frequency changes due to the effect of frequency modulation on the phase-locked loop, stable detection is possible. The present invention relates to a lock detection circuit of a phase locked loop capable of performing lock detection.

[0002]

2. Description of the Related Art First, a PLL frequency synthesizer constructed by using a phase locked loop will be described. 5 is P
It is a schematic block diagram of an LL frequency synthesizer.

[0003] The main operation is to use the phase comparator 8 as the reference first.
1 signal (frequency ff_r[Reference frequency ff_r]) And variable
2nd signal (frequency ff_v[Comparison frequency
ff _v]) Phase difference is detected and the error according to the phase difference
Output a signal. In the charge pump 9, the phase comparator 8
The error signal from the "L" level, "H" level, high level
Convert to 3 values of impedance.

A low pass filter (LPF) 10 smoothes the signal from the charge pump 9 and sends a DC component to a voltage controlled oscillator (VCO) 15. Then, the VCO 15 changes the oscillation frequency according to the DC voltage obtained from the LPF 10 and outputs the third signal (frequency ff _IN ). Third
The signal (frequency ff _IN ) is further converted to N by the variable frequency divider 7.
The frequency is divided and input to the phase comparator 8.

In such a phase-locked loop, it is said that the phase finally becomes stable at ff _r = ff _v (= ff _IN ÷ N) and the phase-locked loop is locked. Here, the third signal (f
f _IN ), ff _IN = N × ff _v = N × ff _r
It is represented by the formula. The meaning of this equation is, by changing the division ratio N of the variable frequency divider 7, is that it is possible to obtain N times the frequency of the reference frequency ff _r the oscillation frequency of the VCO 15. The frequency synthesizer configured by such a method is applied to a wireless device or the like.

Next, the lock detection circuit of the phase-locked loop outputs a frequency other than the first logic level (for example, "H" level) and the lock frequency when the phase-locked loop outputs the lock frequency. In this case, the second logic level (for example, "L" level) is output. With such a lock detection circuit, for example, a PLL using a phase locked loop
It is possible to prevent the frequency synthesizer from emitting radio waves other than the specified frequency.

FIG. 6 is a block diagram of a lock detection circuit (first conventional example) of a conventional phase locked loop. The lock detection circuit in the first conventional example has an error having a pulse width corresponding to the phase difference between the reference frequency ff _r (first signal) and the comparison frequency ff _v (second signal) from the phase comparator 8. The lock is detected based on the signal.

That is, the error signal is passed through the gate circuits 101 and 102 formed in the same chip as the phase locked loop to an external smoothing circuit (low pass filter: LPF).
The signal is output to 103 and a DC lock detection signal LD is generated. Although it has a simple circuit configuration, it requires external components and is not suitable for system miniaturization.

FIG. 7 is a block diagram of a conventional lock detection circuit for a phase locked loop (second conventional example). The lock detection circuit in the second conventional example also performs lock detection based on an error signal having a pulse width corresponding to the phase difference between the reference frequency ff _r and the comparison frequency ff _v from the phase comparator 8. The components of the lock detect circuit are built in the same chip as the phase locked loop.

That is, a shift register 115 including a gate circuit 111, flip-flops 112 and 113, and a gate circuit 114, and a flip-flop 116.
It is composed of a counter 119 composed of ˜118 and a reset set latch 120.

In the lock detecting circuit of the second conventional example,
Regarding the error signal supplied from the gate circuit 111, when the pulse width is smaller than the value determined by the external clock CK, the lock detection signal LD (DC signal) of "H" level and "L" level is output when the pulse width is large. Output. This has the advantage that the lock detection circuit of the second conventional example does not require external parts.

[0012]

In such a conventional lock detection circuit for a phase locked loop, for example, when the phase locked loop is used as a PLL modulator, frequency modulation is performed on the voltage controlled oscillator (VCO). Therefore, the phase difference between the reference frequency ff _r and the comparison frequency ff _v constantly changes. Therefore, there is a problem in that the lock detection signal easily becomes unstable operation such as "H" level or "L" level.

Further, in the conventional lock detection circuit of the phase locked loop, in order to detect the lock state based on the pulse width of the error signal, it is necessary to supply an external clock having a stable frequency, and an external additional circuit is required. There is also a problem that it is necessary and is not suitable for downsizing the system.

The present invention solves the above problems,
An object of the present invention is to provide a lock detection circuit of a phase locked loop that performs lock detection based on only a reference signal and a comparison signal without requiring an external clock whose frequency is stable.

Another object of the present invention is to perform stable lock detection even when the phase difference between the reference frequency ff _r and the comparison frequency ff _v changes due to the influence of frequency modulation on the phase locked loop. Another object of the present invention is to provide a lock detection circuit for a phase locked loop.

[0016]

FIG. 1 is a diagram for explaining the principle of the present invention. In order to solve the above-mentioned problems, the lock detection circuit of the phase locked loop according to the first feature of the present invention is, as shown in FIG. 1, phase locked based on the first signal (f _r ) and the second signal (f _v ). A lock detection circuit for a loop, comprising:
Number of pulses of the signal the second signal within one period of _{(f r) (f v)} , or counting the number of pulses of the second signal (f _v) the first signal in one period of (f _r) Based on the output of the first counting means 1 and the first counting means 1, a determination is made to output a first logic level when the number of pulses is "1" and a second logic level when the number of pulses is other than "1". And the means 2.

The second aspect of the present invention is also characterized in that
The phase lock detection circuit according to claim 1,
The lock detection circuit of the
The number means 1 uses the first signal (f_r) As the reset input
And the second signal (f _v) As the clock input,
Alternatively, the second signal (f_v) As the reset input
Together with the first signal (f_r) As the clock input,
Shift shift with the first bit data input fixed level
It is a register, and the determination means 2 is the shift register.
1 is used as a data input, and the first signal (f_r)Also
Is the second signal (f _v) As a clock input
It is

A third aspect of the present invention is the phase-locked loop lock detection circuit according to the first or second aspect of the present invention, wherein the phase-locked loop lock detection circuit includes: The lock detection circuit includes second counting means 3 for counting the continuous period in which the determining means 2 outputs the second logic level in the cycle of the first signal ( _fr ) or the second signal ( _fv ); When the output of the judgment means 2 is the first logic level, the first logic level is set. When the output of the judgment means 2 is the second logic level, the first logic is set when the second counting means 3 is below a predetermined value. The output means 4 outputs the second logic level when the second counting means 3 exceeds a predetermined value.

Further, in the lock detecting circuit of the phase locked loop according to the fourth aspect of the present invention, in the lock detecting circuit of the phase locked loop according to claim 3, as shown in FIG. , A counter having the output of the judging means 2 as a reset input and the first signal (f _r ) or the second signal (f _v ) as a clock input, and the output means 4
Is a reset set latch which receives the output of the judging means 2 and the output of the counter 4.

[0020]

In the lock detecting circuit for the phase locked loop of the first and second features of the present invention, as shown in FIG. 1, the first signal (for example, the reference signal _fr ) and the second signal handled by the phase locked loop are used.
The lock state is detected based only on the signal (for example, the comparison signal f _v ).

That is, the first counting means 1 uses the first signal (f
_r ) or the second signal (f _v ) within one cycle, the number of pulses of the other signal, that is, the second signal (f _v ) or the first signal (f _r ) is counted, and the determination means In 2, the first
Based on the output of the counting means 1, the first logic level is output when the number of pulses is "1", and the second logic level is output when the number of pulses is other than "1".

In particular, in the lock detection circuit of the phase locked loop having the second characteristic, as shown in FIG.
The first signal (f _r ) or the second signal (f _v ) is reset and input, and the other signal, the second signal (f _v ) or the first signal
This is realized by a shift register in which the signal ( _fr ) is used as a clock input and the first bit data input is a fixed level (for example, "H" level), and the determination means 2 uses the output of the shift register 1 as a data input. , The first signal (f _r ) or the second signal (f _v ) as a clock input.

In such a circuit configuration, the shift register 1 counts the number of pulses of the second signal (f _v ) during one cycle of the first signal (f _r ) and outputs the result. The flag register 2 is the first when the number of pulses is "1".
When the level is "0" or "2" or higher, the second level,
The lock detection signal LD is output in synchronization with the first signal ( _fr ).

[0024] Therefore, without requiring a stable external clock frequency as in the prior art, the reference signal (f _r) and the comparison signal (f _v) only can lock detection based on,
A lock detection circuit for a phase locked loop suitable for downsizing of a system that does not require an external circuit can be realized.

Further, in the lock detecting circuit of the phase locked loop according to the third and fourth features of the present invention, as shown in FIG.
The second counting means 3 counts the continuous period in which the judging means 2 outputs the second logic level in the cycle of the first signal ( _fr ) or the second signal ( _fv ), and the output means 4 judges the judging means 2 Is the first logic level, the second logic level is the output of the determining means 2 is the second logic level.
The first logic level is output when the counting means 3 is below a predetermined value, and the second logic level is output when the second counting means 3 exceeds the predetermined value.

In particular, in the lock detecting circuit of the phase locked loop having the fourth characteristic, as shown in FIG.
This is realized by a counter which uses the output of the judging means 2 as a reset input and the first signal (f _r ) or the second signal (f _v ) as a clock input, and the output means 4 sets the output of the judging means 2 as a set input and counter. This is realized by the reset set latch that uses the output of 4 as the reset input.

For example, when the phase locked loop is used as a PLL modulator, frequency modulation is applied to the voltage controlled oscillator (VCO), so that the phase difference between the reference frequency ff _r and the comparison frequency ff _v constantly changes. . Therefore, the number of pulses of the second signal (f _v ) may temporarily become “0” or “2” or more within one cycle of the first signal (f _r ).

When the number of pulses becomes "0" or "2" or more, the flag register 2 becomes the first signal level (for example, "H" level), and at this rise, the counter 3 is reset and the counting operation is started. . The output signal of the flag register 2 is also the set input to the reset set latch 4, and the lock detection signal LD remains at "H" level.

If the counter 3 is not reset by the output signal of the flag register 2 until the preset count value K is counted, the counter 3
Is reset, the reset set latch 4 is reset, and the lock detection signal LD becomes the second signal level (in this case, "L" level). Here, the count value K of the counter 3 is set to an expected number of times according to the system.

As described above, even if the phase difference between the reference frequency ff _r and the comparison frequency ff _v changes due to the influence of the frequency modulation on the phase locked loop, it is recognized as an unlocked state until the predetermined counter set value is exceeded. Therefore, stable lock detection can be performed without causing unstable operations such as the lock detection signal LD becoming "H" level or "L" level.

[0031]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 2 shows a block diagram of a lock detection circuit of a phase locked loop according to an embodiment of the present invention.

In the figure, the lock detection circuit of the phase locked loop of this embodiment has a reference signal f _v which is a second signal within one cycle of the reference signal f _r which is the first signal for the phase locked loop. First counting means 1 for counting the number of pulses of
Based on the output of the counting means 1, the judging means 2 outputs the first logic level when the number of pulses is "1" and outputs the second logic level when the number of pulses is other than "1", and the judging means 2 outputs the second logic level. The second counting means 3 for counting the continuous period of outputting the level in the cycle of the reference signal _fr , and the first logic level when the output of the judging means 2 is the first logic level, and the output of the judging means 2 is the first In the case of two logic levels, the output means 4 outputs the first logic level when the second counting means 3 is below the predetermined value and outputs the second logic level when the second counting means 3 exceeds the predetermined value. And is configured.

The phase locked loop is an oscillator (TCXO).
5, reference frequency divider (÷ R) 6, comparison frequency divider (÷ N) 7, phase comparator 8, charge pump 9, low-pass filter (L
PF) 10 and voltage controlled oscillator (VCO) 15. In this embodiment, the phase locked loop is used as the PLL modulator, and the voltage controlled oscillator (V
A modulation signal is supplied to (CO) and frequency modulation is applied.

The first counting means 1, the reset input of the reference signal f _r having a stable frequency reference frequency divider 6 to R divider frequencies (reference frequency ff _r) from the oscillator 5, VC
This is a shift register in which a reference signal f _v having a frequency (comparison frequency ff _v ) obtained by dividing the oscillation frequency of O15 by N by the comparison frequency divider 7 is used as a clock input, and the data input of the first bit is a fixed level. The shift register 1 includes flip-flops 11 and 12, gate circuits 13 and 14.
It consists of

The judging means 2 is a flag register which receives the output of the shift register 1 as a data input and the reference signal _fr as a clock input, and is realized by a flip-flop 21.

The second counting means 3 includes a flag register 2
Of the flip-flops 31 to 33 as a reset input and a reference signal _fr as a clock input.
Has been realized in.

Further, the output means 4 is a reset set latch which receives the output of the flag register 2 as a set input and the output of the counter 4 as a reset input, and is a gate circuit (N).
AND gates) 41 and 42.

The reference signal f _r and the comparison signal f _v are input to the phase comparator 8, and the charge pump 9 outputs an error signal corresponding to the phase difference. The error signal is smoothed by the LPF 10, the DC voltage is input to the VCO 15, and the oscillation frequency (modulation output) changes according to the voltage.

This phase-locked loop has a reference signal f_rAnd ratio
Comparison signal f_vFrequency ff_rAnd ff _vSo that
To work. The phase relationship is such that the VCO 15 is modulated.
Therefore, it will change constantly.

With respect to such a phase locked loop, the lock detection circuit operates as follows. Flip flop 1
1 and 12 receive the comparison signal f _v as a clock and the reference signal f _v
In the shift register 1 having _r as a reset input, the data input of the flip-flop 11 is connected to the "H" level. The shift register 1 functions to count the number of pulses of the comparison signal f _v that the reference signal f _r enters during one cycle.

That is, when the number of pulses of the comparison signal f _v is “0”, both outputs Q ₁₁ and Q ₁₂ of the flip-flop are “L”.
It is a level. Further, the number of pulses of the comparison signal f _v is “1”
At the time of, the output Q _{11 of the} flip-flop is at “H” level,
Output Q ₁₂ of the flip-flop is "L" level. Further, when the number of pulses of the comparison signal f _v is “2” or more, both outputs Q ₁₁ and Q ₁₂ of the flip-flops are “H” level.

Therefore, the NAND gate circuit 13 is
When the number of pulses of the comparison signal f _v is “1” in one cycle of the reference signal f _r , “L” level is output, and when it is “0” or “2” or more, “H” level is output.

The output X ₁₃ of the NAND gate circuit 13 is supplied to the data input of the flip-flop 21, and the reference signal f
The output Q _{21 of the} flip-flop is output in synchronization with _r .
The flip-flop output Q ₂₁ is supplied to the reset inputs of the flip-flops 31, 32, 33 forming the counter 3 and the set input of the reset set latch 4 formed of the NAND gate circuits 41, 42.

The counter 3 is between the flip-flop output Q ₂₁ is "H" level, the reference signal f _r as the clock input, counts from the count value "0". The output XQ _{33 of the} counter 3 outputs "H" level when the count value is less than "4" and outputs "L" level when the count value becomes "4".

The output XQ _{33 of the} counter 3 is supplied to the reset input of the reset set latch 4, and the output of the NAND gate circuit 41 becomes the lock detection signal LD. By the above operation, the lock detection signal LD outputs the fact that the lock state / unlock state is obtained in the following states. (1) When the number of pulses of the comparison signal f _v in one cycle of the reference signal f _r is "1", the lock detection signal LD outputs an "H" level (that is in the locked state). (2) When the number of pulses of the comparison signal f _v is “0” or “2” within one cycle of the reference signal f _r , the state continues for a preset number of times (K times) or more (shown in FIG. 2). In the case of the circuit configuration, K = 4), and the lock detection signal LD is "L".
The level (in the unlocked state) is output, and the "H" level is output until then.

In (2), the fact that the unlocked state is not output immediately is to determine whether the number of pulses has temporarily changed due to frequency modulation or has changed due to an abnormality. is there. In the case of frequency modulation, even if the number of pulses changes temporarily, it will be set to 1 again after several times.
Become a pulse.

FIG. 3 shows the lock of the phase locked loop of this embodiment.
It is an operation timing chart of each part in the detection circuit. Same figure
3A is a timing diagram in the locked state, and FIG.
Is the reference signal f_r3 (b) shows the comparison signal fv, FIG.
(C) and (d) show the output EU (up
Signal) and ED (down signal), FIG. 3 (e) is shifted
Output Q of flip-flop 11 in register 1₁₁, Fig. 3
(F) is the flip-flop 12 in the shift register 1
Inverted output XQ₁₂3 (g) shows the NAND gate circuit 13
Output X ₁₃3 (h) shows the flag register 2 (flip
Output Q of flop 21)_{twenty one}, FIG. 3 (i) shows the inside of the counter 3.
Inverted output XQ of the flip-flop 31₃₁, FIG. 3 (j)
Is the inverted output XQ of the flip-flop 32 in the counter 3.
₃₂3 (k) shows a flip-flop 33 in the counter 3.
Inverted output XQ₃₃Figure 3 (l) shows the reset set
Output of NAND gate circuit 42 of switch 4₄₂, Fig. 3
(M) is a lock detection signal LD.

In the figure, the reference signal f _r of 1
The number of pulses of the comparison signal f _v per cycle is “2” and “0”, but since it does not occur once or more continuously and is “1” after that, the lock detection signal LD is stable and “ The H "level (indicating that it is in the locked state) is output.

FIG. 4 is an operation timing chart of each part in the lock detection circuit of the phase locked loop of this embodiment. This figure is a timing chart in the unlocked state, and shows the same signals as in FIG. 3 as the signals of the respective parts.

In the figure, since the number of pulses of the comparison signal f _v per cycle of the reference signal f _r is “2” four times or more consecutively, the unlocked state is detected. That is,
After the reset input of counter 3 becomes active,
The lock detection signal LD becomes "L" level at the rising _edge of the reference signal fr in the fourth cycle, indicating an unlocked state.

As described above, the phase locked loop of this embodiment
In the lock detection circuit of, the reference signal f _rAnd comparison signal f_vof
Since the lock detection is based on only
Does not require an external clock as in
Are suitable.

Further, even when the phase difference between the reference frequency ff _r and the comparison frequency ff _v changes due to the influence of frequency modulation on the phase locked loop, the change occurs continuously over the set value expected according to the system. Otherwise, it is not considered that an abnormality has occurred (unlocked state), so it is possible to perform stable lock detection ignoring temporary fluctuations in the phase difference.

[0053]

As described above, according to the lock detection circuit of the phase locked loop of the first and second features of the present invention, the first counting means is within one cycle of the first signal or the second signal. , The number of pulses of the other signal, that is, the second signal or the first signal, is counted, and the determination unit determines whether the pulse number is “1” based on the output of the first counting unit.
When the logic level is other than "1", the second logic level is output, and the lock state is based on only the first signal (for example, the reference signal) and the second signal (for example, the comparison signal) handled by the phase locked loop. Therefore, it is possible to provide a lock detection circuit of a phase locked loop which does not require an external clock and consequently does not require an external circuit externally and which can be adapted to system miniaturization.

Further, according to the lock detecting circuit of the phase locked loop of the third and fourth aspects of the present invention, the second counting means causes the determining means to output the second logic level during the continuous period of the first signal or Counting in the cycle of the second signal, the output means determines the first logic level when the output of the determination means is the first logic level, and the second counting means when the output of the determination means is the second logic level. Since the first logic level is output when the value is less than the value and the second logic level is output when the second counting unit exceeds the predetermined value, the reference frequency is output due to the influence of frequency modulation on the phase locked loop. Even if the phase difference of the comparison frequency changes, the unlock state is not recognized until the predetermined counter setting value is exceeded, so the lock detection signal can be stably detected without falling into unstable operation. It is possible to provide a lock detection circuit of a phase locked loop.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a lock detection circuit of a phase locked loop according to an embodiment of the present invention.

FIG. 3 is an operation timing chart (locked state) of each part in the lock detection circuit of the phase locked loop of the embodiment.

FIG. 4 is an operation timing chart (unlocked state) of each part in the lock detection circuit of the phase locked loop of the embodiment.

FIG. 5 is a schematic configuration diagram of a PLL frequency synthesizer.

FIG. 6 is a conventional phase lock loop lock detection circuit (first
It is a block diagram of (conventional example).

FIG. 7 is a lock detection circuit of a conventional phase locked loop (second
It is a block diagram of (conventional example).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Shift register (first counting means) 2 ... Flag register (determination means) 3 ... Counter (second counting means) 4 ... Reset set latch (output means) 5 ... Oscillator (TCXO) 6 ... Reference frequency divider (÷ R) 7 ... Comparative frequency divider (÷ N) 8 ... Phase comparator 9 ... Charge pump 10 ... Low-pass filter (LPF) 15 ... Voltage controlled oscillator (VCO) 11, 12, 21, 31-33 ... Flip-flop 13, 14 ... gate circuits 41 and 42 ... gate circuit (NAND gate) f _r ... first signal (reference signal) f _v ... second signal (comparison signal) f _IN ... third signal LD ... lock detection signal EU ... phase the output Q ₂₁ of the comparator 8 outputs (up signal) ED ... output of the phase comparator 8 (down signal) Q ₁₁ ... flip-flop 11 in the shift register 1 ... flag register 2 (flip 21) output X ₁₃ ... output of NAND gate circuit 13 X ₄₂ ... output of NAND gate circuit 42 of reset set latch 4 XQ ₁₂ ... inverted output of flip-flop 12 in shift register 1 XQ ₃₁ ... in counter 3 Inverted output of the flip-flop 31 in the counter XQ ₃₂ ... Inverted output of the flip-flop 32 in the counter 3 XQ ₃₃ ... Inverted output of the flip-flop 33 in the counter 3

Claims (4)

[Claims] 1. A lock detection circuit for a phase-locked loop based on a first signal and a second signal, the number of pulses of the second signal within one period of the first signal, or 1 of the second signal. Based on the output of the first counting means and the first counting means for counting the number of pulses of the first signal within a cycle, when the number of pulses is "1", the first logic level is other than "1" Is a lock detection circuit for a phase-locked loop. 2. The first counting means uses the first signal as a reset input and the second signal as a clock input, or the second signal as a reset input and the first signal as a clock input. Is a shift register in which the data input of the first bit is a fixed level, and the determination means is a flag register in which the output of the shift register is a data input and the first signal or the second signal is a clock input. The lock detection circuit of the phase-locked loop according to claim 1, wherein the lock detection circuit is provided. 3. The lock detection circuit of the phase-locked loop, wherein the determination means outputs a continuous period during which the second logic level is output,
Second counting means for counting in the cycle of the first signal or the second signal; and a first logic level when the output of the judging means is the first logic level, and a second logic level when the output of the judging means is the second logic level. Means a second logic level when the second counting means is below a predetermined value and a second logic level when the second counting means exceeds a predetermined value.
3. A lock detection circuit for a phase locked loop according to claim 1, further comprising output means for outputting each logic level. 4. The second counting means is a counter which uses the output of the judging means as a reset input and the first signal or the second signal as a clock input, and the output means outputs the output of the judging means. 4. The lock detection circuit of the phase locked loop according to claim 3, wherein the lock detection circuit is a reset set latch that receives the output of the counter.