JPH09101978A - Layout verification method - Google Patents

Abstract

(57) Abstract: In a layout verification for verifying that layout data has an arrangement and shape that function as an LSI, pseudo errors are reduced and a verification rule is optimized for a process. In a layout verification for verifying that a geometric condition is satisfied for an intermediate graphic generated by giving an attribute to a layout graphic and performing graphic processing one or more times to input the layout graphic, an intermediate graphic is generated. Is further processed to generate a virtual figure. At that time, information for identifying the intermediate figure that is the source of the virtual figure is held. The verification process is performed by replacing the original intermediate figure with this virtual figure, and attributes are assigned in the same manner as the intermediate figure. Here, there are provided an attribute when the virtual figure is not used, a step of detecting a change of the attribute when the virtual figure is used, and a step of identifying an intermediate figure which causes the attribute change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI layout design method, and more particularly to a layout verification for verifying that a layout graphic has an arrangement and a shape that function as an LSI.

[0002]

2. Description of the Related Art In LSI design, layout verification verifies that a layout graphic has a shape and arrangement in accordance with design rules. Most of the verification rules used for verification are applied only to layout graphics with specific conditions,
It is a conditional verification rule. Therefore, in the prior art, layout graphics are limited by various conditions, a set consisting only of layout graphics that meet the conditions is generated, and verification is performed on the set. The flow will be described below with reference to the drawings.

FIG. 13 is a flowchart of a conventional example. First, in a data input step 101, a layout graphic and a verification rule are input. In the intermediate figure generation step 102, attributes are given to the layout figure according to the verification rule, graphic processing such as logical operation, geometric conversion, and selection processing is performed to generate an intermediate figure necessary for the verification processing. In the verification step 103, the verification rule is applied to the intermediate figure, and it is confirmed that the verification rule is satisfied. When the verification processing is repeatedly performed on the intermediate figure and the verification processing for all the verification items is completed, the verification result is output in the result output step 108.

[0004]

However, in the conventional verification method, the attribute is only given to the combination of layout graphics, and the use of the attribute is only a criterion for graphic selection. That is, the attribute change under a specific condition cannot be used for the verification, and the verification rule given as the conditional verification rule can only be given a simple condition that does not require the attribute change. As a result, when verifying a verification rule of a complicated condition, it is necessary to replace it with a simple condition that does not use the attribute change. However, under simple conditions, the layout figures to be verified cannot be sufficiently narrowed down, and more layout figures than the intended intention of the design rule will be verified. Further, by verifying the graphic that does not need to be applied, the layout area is increased due to the generation of the pseudo error or the change to the layout graphic in which the pseudo error does not occur. The present invention shows a layout verification method in which a conditional verification rule applied only under a complicated condition is simply described and verification is performed.

[0005]

In order to solve the above-mentioned problems, in the layout verification method of the present invention, a step of generating a virtual figure by combining the result of the verification for the layout figure with the layout figure, And a step of giving attributes to the virtual figures and a step of comparing attributes between the virtual figures. The virtual figure holds the verification result which is the cause thereof together with the shape information and attributes of the figure. By comparing the attributes given to the virtual layout figure with the attributes of the layout figure and the intermediate figure, the verification result that is the cause of the virtual figure is selected, and the verification applied only under complicated conditions is realized.

Further, a logical operation is performed on the layout figure,
Comparing the steps of performing geometric processing such as geometric conversion and selection to generate figures in different states as virtual figures, giving attributes to virtual figures, and comparing attributes of virtual figures with other figures The step of recognizing the change of the attribute from the result and identifying the figure causing the change is provided. As a result, complicated verification whose verification condition is to cause an attribute change is realized.

Further, there are a step of extracting circuit information formed by a layout graphic and an intermediate graphic and consisting of circuit elements and connection wirings thereof, a step of extracting circuit information from the virtual graphic, and a step of comparing the circuit information. With the provision, a method of generating a virtual figure that changes circuit information can be treated as a verification item.

[0008]

According to the verification method having the above steps, it is possible to use a virtual layout graphic using the verification result of the layout graphic and use the change of the attribute given to the graphic as a condition for verification. Further, it is possible to generate a virtual figure according to the possibility that the layout figure changes, and verify the influence of the change of the layout figure as a change of the attribute. As a result, it becomes possible to perform verification applied only under complicated conditions, and strict classification is performed to improve verification accuracy, prevent increase in layout area, and prevent occurrence of pseudo error.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a flow chart of this embodiment. First, in a data input step 101, a verification rule and a layout graphic to be verified are input. In the intermediate figure generation step 102, attributes are given to the layout figure in accordance with the verification rule, and graphic processing such as logical operation, geometric conversion, or figure selection based on conditions is performed on the layout figure, and the intermediate figure used for the verification process has attributes. Generate a shape. In the verification step 103, a verification rule is applied to the intermediate graphic to perform verification processing, an error part is generated as an error graphic, and the cause of the error graphic is generated as a verification result. If there is a verification item using a virtual figure, a virtual figure is generated from the layout figure, the intermediate figure, the error figure, and the verification result in the virtual figure generating step 104. Here, the virtual figure is a figure generated by adding or deleting a part of the intermediate figure or the error figure to the intermediate figure indicated by the verification rule and the verification result. The virtual figure is treated in the same manner as the layout figure in the intermediate figure generation step 102 and used for generating the intermediate figure. Further, the virtual figure attribute giving step 105 gives an attribute to the virtual figure, the attribute comparing step 106 compares the attributes of the virtual figure and the intermediate figure, or the mutual attributes of the virtual figures, and the verification result selecting step 107 produces the virtual figure from the comparison result. Select the verification result used to The verification process is repeatedly performed on the intermediate graphic generated from the layout graphic and the virtual graphic, and when the verification process for all the verification items is completed, the verification result is output in the result output step 108. A virtual figure is a figure calculated by combining an error figure with a layout figure or an intermediate figure,
The verification result corresponding to the used error graphic is retained in addition to the shape as a graphic. Therefore, the verification result corresponds to each virtual figure, and the selection of the verification result is realized by selecting the virtual figure.

An example of the verification process using a virtual figure will be described below with reference to the drawings. FIG. 2 shows layers 201 and 20.
2 is an example of a layout figure composed of three types of layers, a layer 203 and a layer 203. The figures 201A to 201F of the layer 201 are connected if the figures are adjacent to each other. Further, the figures connected to the common figure are also connected to each other. That is, the figures 201A and 201B are
They are connected via the figure 201C. Similarly, figure 20
1D, figure 201E, and figure 201F are also connected. The layer 203 is a layer that connects the layer 201 and the layer 202, and is connected to another layer that overlaps. Therefore, the graphic 201A is the graphic 203 of the layer 203.
A is connected to the figure 202 on the layer 202, and is further connected to the figure 201B via the figure 203B on the layer 203.

At this time, consider a verification in which a portion where the width of the layer 201 is narrower than a threshold value is output as an error. However, even if it is assumed that the narrow portion of the layer 201 is removed from the layout graphic, an error does not occur if the connection of other portions is maintained.

FIG. 3 is a part of an intermediate figure generated for performing the above-described verification on the figure shown in FIG. 2, in which the layout figure is labeled as an attribute. The same label is given to the connected figures, and the presence or absence of the connection can be confirmed by the label. Figure 201C and Figure 20 in this state
When the verification process is performed with a value slightly wider than the width of 1F as a threshold value, the figures 201C and 201F are obtained as error figures. In the verification of this example, a figure obtained by removing the error figure from the layout figure given as an input is used as a virtual figure. At this time, if the figures 201C and 201F are removed from the layout figure of FIG. 3 and a label is given as an attribute to generate a virtual figure, the figure of FIG. 4 is obtained. The figures 201A and 201B in FIG. 4 have the error figure 201C that is the cause of the virtual figure as an attribute, and the figures 201D and 201E similarly have the error figure 201F as an attribute. In FIG. 4, unlike the intermediate figure generated from the layout figure in FIG. 3, different labels are attached because the figures 201D and 201E are not connected. In this verification item, the case where the labels are different between the virtual figures having the same attribute value representing the error figure that is the cause of the virtual figure is selected as an error. In this example, the figure 201F is determined as an error among the figures which are error candidates.

In the conventional method, the graphic 201C and the graphic 201
Since F cannot be identified, both have to be errors, and the verification rule is only the verification of the threshold value without proviso. In this method, the verification rule as intended can be set, and only the graphic 201F is output as an error.

(Embodiment 2) FIG. 5 is a flow chart of this embodiment. In the data input step 101 and the intermediate figure generation step 102, an intermediate figure is generated as in the first embodiment,
Verification step 103 for verification items that do not use virtual figures
And perform the same verification as before. Virtual figure generation step 50
In 4, the virtual figure is generated by performing processing such as logical operation on the intermediate figure. Virtual figure attribute assignment step 1
At 05 and attribute comparison step 106, attributes are given to the virtual figure and compared as in the first embodiment. After receiving the comparison result,
In the causative figure identification step 507, the figure that caused the difference in attributes is identified. The specified figure is
It is treated as a verification error graphic like any other error graphic.

An example of verification by the method of this embodiment will be shown below.
FIG. 6 is an example of a layout figure composed of three types of layers, a layer 601, a layer 602, and a layer 603. When layer 601 and layer 602 overlap,
Further, if the layers 603 overlap, it is assumed that they are connected. Therefore, although the graphic 601A of the layer 601 and the graphic 602 of the layer 602 are not connected,
The figure 601B is connected to the figure 602, and if the same label is given as an attribute to the connected figure, the labels of the figure 601B and the figure 602 become the same, and the figure 6
Only the label of 01A is different. Here, it is considered to verify that an extra connection does not occur when the layer 603 is expanded and not expanded. Here, a figure 603E obtained by enlarging the figure 603 of the layer 603.
Is used as a virtual figure, the state shown in FIG. 7 is obtained. In this state, when the layer 601 and the layer 602 overlap and the layer 603E overlaps, it is assumed that the layer 601 and the layer 602 are connected, and if a label indicating the connection state is given as an attribute as in FIG. The labels of 601A, figure 601B, and figure 602 are all the same.
This is recognized as an error because the attribute has changed from the state of FIG. In this verification, the graphics with the same label are grouped by the label that does not use the virtual graphic, and the virtual graphic that overlaps both groups and causes the connection between the layers and the original graphic are set as the error graphic.

(Third Embodiment) FIG. 8 is a flow chart of this embodiment. In addition to the same processing as in the second embodiment, in the circuit information extraction step 810 following the intermediate graphic generation step 102, the circuit element formed by the layout graphic and the wiring between the circuit elements are extracted as circuit information. In addition, the circuit information extraction step 8 from the layout graphic including the virtual graphic.
The circuit information is extracted according to 11. The extracted circuit information is compared in the circuit information comparison step 812,
If a difference is found, the virtual figure used for the circuit information extraction and the original figure are set as error figures.

An example of verification by the method of this embodiment will be shown below.
FIG. 9 is an example of an intermediate graphic generated by a layout graphic. The circuit shown in FIG. 10 is obtained by extracting circuit information from the intermediate figure of FIG. 9 and expressing it as a circuit diagram. Here, FIG. 11 shows a result of enlarging the layer 901 of the intermediate figure in FIG. 9 to generate the layer 901E of the virtual figure. When the virtual figure layer 901E is regarded as the intermediate figure layer 901 and the circuit information is extracted from the figure of FIG. 11 and expressed as a circuit diagram, FIG. 12 is obtained. When FIG. 10 and FIG. 12 are compared, there is one more wiring in FIG. 12, and the circuit information when the virtual figure is used is different from the circuit information when not used.
Therefore, the result that this verification example includes an error graphic is obtained.

[0019]

By using the verification method of the present invention,
It becomes possible to verify the verification items to be applied only under the complicated condition that causes the attribute change, and the accuracy of the verification is improved by strictly performing the verification case. As a result, the layout flexibility is increased and the layout area is reduced,
Prevent the occurrence of pseudo errors.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout verification method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout graphic used in layout verification in the first embodiment.

FIG. 3 is a diagram showing an example of an intermediate graphic used in layout verification in the first embodiment.

FIG. 4 is a diagram showing an example of a virtual figure used in layout verification in the first embodiment.

FIG. 5 is a flowchart of a layout verification method according to the second embodiment of the present invention.

FIG. 6 is a diagram showing an example of an intermediate graphic used in layout verification in the second embodiment.

FIG. 7 is a diagram showing an example of a virtual figure used for layout verification in the second embodiment.

FIG. 8 is a flowchart of a layout verification method according to a third embodiment of the present invention.

FIG. 9 is a diagram showing an example of an intermediate graphic used in layout verification in the third embodiment.

FIG. 10 is a diagram showing circuit information extracted from an intermediate graphic used in layout verification in the third embodiment.

FIG. 11 is a diagram illustrating an example of a virtual figure used in layout verification in the third embodiment.

FIG. 12 is a diagram showing circuit information extracted from a virtual figure used for layout verification in the third embodiment.

FIG. 13 is a flowchart of a layout verification method using a conventional method.

[Explanation of symbols]

 101 data input step 102 intermediate figure generation step 103 verification step 104 virtual figure generation step from error figure 105 virtual figure attribute assignment step 106 attribute comparison step 107 verification result selection step 108 result output step 201A-201E layer 201 figures 203A-203B Graphic of layer 203 504 Virtual graphic generation step from intermediate graphic 601A to 601B Graphic of layer 601 603E Graphic enlarged of graphic of layer 603 810 Circuit information extraction step from intermediate graphic 811 Circuit information extraction step from virtual graphic 812 Circuit information Comparison step 901E Graphic obtained by enlarging the graphic of the layer 901

Claims (5)

[Claims] 1. A layout verification method for verifying that an intermediate graphic generated by giving an attribute to a layout graphic, performing graphic processing one or more times with the layout graphic as an input and giving the attribute satisfies a geometric condition, Generating a virtual figure by performing one or more figure processes using the intermediate figure as an input; giving an attribute to the virtual figure; A layout verification method comprising: a step of comparing attributes; and a step of identifying a figure causing an attribute difference. 2. The layout verification method according to claim 1, wherein the step of generating the virtual figure includes combining the layout figure verification result figure with the layout figure to perform a figure process to generate the virtual figure, and further A layout verification method comprising a step of selecting a verification result from a comparison result. 3. A layout verification method for verifying that an intermediate graphic generated by giving an attribute to a layout graphic, performing graphic processing one or more times with the layout graphic as an input and giving the attribute, satisfies a geometric condition. Extracting circuit information consisting of circuit elements and wirings from the layout graphic; generating a virtual graphic by performing graphic processing one or more times with the intermediate graphic as an input; and circuit elements and circuits from the virtual graphic. A layout verification method comprising: a step of extracting circuit information composed of connection information; and a step of comparing circuit information extracted from the layout figure with circuit information extracted from the virtual figure. 4. The layout verification method according to claim 3, wherein the step of generating the virtual figure generates a virtual figure by combining an intermediate verification result of the layout figure with the layout figure. 5. The layout verification method according to claim 2, further comprising the step of extracting circuit information consisting of circuit elements and wirings from the layout graphic, and the step of extracting circuit information consisting of circuit elements and wirings from the virtual graphic. A layout verifying method comprising: comparing circuit information extracted from the layout graphic with circuit information extracted from the virtual graphic.