JPH09102585A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor device having at least a transistor and a capacitor has a reduced area of the capacitor, and such a semiconductor device is manufactured by a simple manufacturing process. In a semiconductor device such as an MMIC, an F
An electrode 17 for a capacitor is formed of ohmic metal in the same layer as the source electrode 12 and the drain electrode 13 of the ET. The electrode 21 and the interlayer insulating film 23 are formed on the capacitor composed of the electrode 17, the interlayer insulating film 5 and the electrode 21.
And a capacitor constituted by wiring formed of the metal film 24 and the plated layer 25 are stacked, and these capacitors are connected in parallel. In another example, a capacitor electrode is further formed of the same layer of ohmic metal as the gate electrode 11, and a three-layer capacitor including the capacitor composed of this electrode, the interlayer insulating film 4, and the electrode 17 is laminated. , These capacitors are connected in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly suitable for application to a semiconductor device having a transistor such as a field effect transistor and a capacitor.

[0002]

2. Description of the Related Art A monolithic microwave integrated circuit (MMIC) is known as a semiconductor device for high frequency applications used in mobile phones and the like.

FIG. 13 is a sectional view showing an example of a conventional MMIC.

As shown in FIG. 13, this conventional MMIC is used.
In the above, in the semi-insulating GaAs substrate 101, an element isolation region 102 in which, for example, boron (B) is ion-implanted is provided. An insulating film 103 such as a silicon nitride (Si ₃ N ₄ ) film is provided on the semi-insulating GaAs substrate 101. Interlayer insulating films 104 and 105 such as a silicon dioxide (SiO ₂ ) film are sequentially provided on the insulating film 103.

A p ^-- type region 106 is provided in the semi-insulating GaAs substrate 101 surrounded by the element isolation region 102. In the p ⁻ type region 106, an n type channel region 107, an n ⁺ type source region 108 and a drain region 109 are provided. Furthermore, a p ⁺ type gate region 110 is provided in the n type channel region 107. Then, the n-type channel region 107 and the gate region 1
A junction field effect transistor (JFET) is composed of 10, the source region 108 and the drain region 109. Insulating film 103 and interlayer insulating films 104 and 105
Are provided with contact holes C1 ′, C2 ′, C3 ′ at portions corresponding to the gate region 110, the source region 108 and the drain region 109, respectively. Then, the gate region 110 is formed through the contact hole C1 '.
A gate electrode 111 that makes ohmic contact with the source region 108 is provided through a contact hole C2 ′.
A source electrode 112 that makes ohmic contact with the drain region 10 is provided through a contact hole C3 ′.
9 is provided with a drain electrode 113 which makes ohmic contact.

An n-type region 114 is provided in another part of the semi-insulating GaAs substrate 101 surrounded by the element isolation region 102. This n-type region 114 constitutes a resistor.
The insulating film 103 and the interlayer insulating films 104 and 105 are provided with contact holes C4 ′ and C5 ′, respectively, at portions corresponding to one end and the other end of the n-type region 114. Then, these contact holes C4 ', C5'
Electrodes 115 and 116 are provided in ohmic contact with the n-type region 114 through. These electrodes 11
5, 116 are the source electrode 112 and the drain electrode 1
It is formed of the same layer material as 13.

Reference numerals 117, 118, 119, 120, 1
21 are contact holes C1 ', C2', C3, respectively.
The electrodes formed on ', C4', and C5 'are shown. These electrodes 117 to 121 are the gate electrode 111, the source electrode 112, the drain electrode 113, the electrodes 115, 1 respectively.
It is connected to 16. Further, the electrode 120 extends to the capacitor region on the interlayer insulating film 105.

An interlayer insulating film 122 such as a SiO ₂ film is provided so as to cover the electrodes 117 to 121. Contact holes C6 ′ and C7 ′ are provided in the interlayer insulating film 122 at portions corresponding to the electrodes 119 and 121.

On the inter-layer insulation film 122, a wire made of a metal film 123 and a plating layer 124 having a predetermined shape is provided as an air bridge wire. This wiring composed of the metal film 123 and the plated layer 124 has a contact hole C.
It is connected to the electrode 119, that is, the drain electrode 113 of the JFET through 6 ', and is also connected to the electrode 121, that is, the electrode 116 of the n-type region 114 that constitutes a resistor through the contact hole C7'. Further, a passivation film 125 such as a SiN film is provided so as to cover the plated layer 124.

In this MMIC, a capacitor is formed by the electrode 120, the interlayer insulating film 122 on the electrode 120, and the wiring made of the metal film 123 and the plating layer 124 on the electrode 120. One electrode of this capacitor, that is, the wiring formed of the metal film 123 and the plated layer 124 is connected to the drain electrode 113 of the JFET via the electrode 119. Also, the other electrode 120 of this capacitor
Is connected to the electrode 115 of the n-type region 114 that constitutes the resistor.

By the way, in the above MMIC, the JFET is
The source electrode 112 and the drain electrode 113 and the resistance electrodes 115 and 116 are formed by a lift-off method. The method of forming these electrodes will be described below.

As shown in FIG. 14, after the gate electrode 111 is formed, an interlayer insulating film 104 is formed on the entire surface. Next, a resist pattern 131 having a predetermined shape is formed on the interlayer insulating film 104, in which portions corresponding to one end and the other end of the source region 108, the drain region 109, and the n-type region 114 are opened.

Next, as shown in FIG. 15, the contact holes C2 ', C3', C4 ', C5' are formed by etching away a predetermined portion of the interlayer insulating film 104 and the insulating film 103 using the resist pattern 131 as a mask. After the formation, an ohmic metal film 132 such as an AuGe / Ni film is formed on the entire surface.

Next, the resist pattern 131 is removed together with the ohmic metal film 132 thereon. Thereby, as shown in FIG. 16, the source electrode 112, the drain electrode 113, and the electrodes 115 and 116 are formed.

[0015]

By the way, it is effective to reduce the area of the capacitor in order to reduce the element area in the MMIC in which the ratio of the area of the capacitor to the entire element is large.

In order to reduce the area of the capacitor in the MMIC shown in FIG. 13 described above, which is composed of the electrode 120, the interlayer insulating film 122, the wiring made of the metal film 123 and the plated layer 124, without changing the capacitance. There is a method of reducing the thickness of the interlayer insulating film 122 in the capacitor region. However, since the thickness of the interlayer insulating film 122 is limited by the breakdown voltage of the capacitor, there is a limit in reducing the area of the capacitor by this method.

As another method of reducing the area of the capacitor, there is a method of forming a structure in which a plurality of capacitors are laminated and connecting the plurality of capacitors in parallel (Japanese Patent Laid-Open No. 1-1999).
120052). According to this method, the area of the capacitors can be further reduced by increasing the number of capacitors to be stacked. However, increasing the number of capacitors to be stacked complicates the manufacturing process because the number of manufacturing processes such as electrode formation increases.
Manufacturing costs also increase.

Therefore, an object of the present invention is to provide a semiconductor device having at least a transistor and a capacitor, in which the area of the capacitor can be reduced, and such a semiconductor device can be manufactured by a simple manufacturing process. It is to provide a method for manufacturing a semiconductor device.

[0019]

To achieve the above object, a first invention of the present invention is, in a semiconductor device having at least a transistor and a capacitor, at least one electrode of the transistor and one electrode of the capacitor. Are formed of the same layer material.

In one embodiment of the first invention of the present invention, the transistor is a field effect transistor, and the source electrode and drain electrode of this field effect transistor and one electrode of the capacitor are formed of the same layer material. It For this field effect transistor,
For example, JFET, metal-semiconductor field effect transistor (MESFET) and high electron mobility transistor (H
EMT) and the like.

In another embodiment of the first invention of the present invention, the transistor is a field effect transistor, and the gate electrode of this field effect transistor and one electrode of the capacitor are formed of the same layer material.

In still another embodiment of the first aspect of the present invention, the transistor is a bipolar transistor, and at least one of an emitter electrode, a base electrode and a collector electrode of the bipolar transistor and one of the capacitors are provided. The electrode and the electrode are formed of the same layer material.

According to a second aspect of the present invention, in a semiconductor device having at least a field effect transistor and a capacitor, the gate electrode of the field effect transistor is provided on the semiconductor substrate and the insulating film is provided on the semiconductor substrate. In addition, it has a first electrode formed of the same layer material as the gate electrode, has a source electrode and a drain electrode of the field effect transistor on the semiconductor substrate, and has a first interlayer insulating film on the first electrode. A second electrode formed of the same layer material as the source electrode and the drain electrode, the second electrode being provided via the second interlayer insulating film, and the first electrode being provided on the second electrode. A third electrode connected to the electrode at a predetermined portion, and a third electrode on the third electrode.
A fourth capacitor which is provided via the interlayer insulating film of the first electrode and is connected to the second electrode at a predetermined portion by the first electrode, the first interlayer insulating film and the second electrode. And a second capacitor is constituted by the second electrode, the second interlayer insulating film and the third electrode, and a third capacitor is constituted by the third electrode, the third interlayer insulating film and the fourth electrode. Is formed, and the first capacitor, the second capacitor, and the third capacitor are connected in parallel.

According to a third aspect of the present invention, in a method of manufacturing a semiconductor device having at least a transistor and a capacitor, a step of simultaneously forming at least one electrode of the transistor and one electrode of the capacitor with the same layer material is used. It is characterized by having.

In one embodiment of the third invention of the present invention, the transistor is a field effect transistor, and the source electrode and drain electrode of this field effect transistor and one electrode of the capacitor are simultaneously formed of the same layer material. To do.

In another embodiment of the third aspect of the present invention, the transistor is a field effect transistor, and the gate electrode of this field effect transistor and one electrode of the capacitor are simultaneously formed of the same layer material.

In still another embodiment of the third invention of the present invention, the transistor is a bipolar transistor, and at least one of the emitter electrode, the base electrode and the collector electrode of the bipolar transistor and one of the capacitors are provided. The electrodes and the material of the same layer are simultaneously formed.

A fourth aspect of the present invention is a method of manufacturing a semiconductor device having at least a transistor and a capacitor, and corresponds to a formation region of at least one electrode of the transistor on an insulating film formed on a semiconductor substrate. A step of forming a first resist pattern having a first opening in a portion; a step of exposing the surface of the semiconductor substrate by etching the insulating film using the first resist pattern as a mask; And a step of forming a second resist pattern having a second opening in a portion corresponding to the first opening and a portion corresponding to the formation region of one electrode of the capacitor, and using the second resist pattern as a mask. Patterning the first resist pattern, forming a conductive film on the semiconductor substrate, and Characterized by a step of removing with resist pattern and second resist pattern formed thereon conductive film.

According to the present invention, since at least one electrode of a transistor such as a field effect transistor or a bipolar transistor and one electrode of a capacitor can be simultaneously formed by using the material of the same layer, the increase in manufacturing steps can be minimized. It is possible to reduce the area of the capacitor by multilayering the capacitor while suppressing the limit.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 1 shows an M according to the first embodiment of the present invention.
It is sectional drawing which shows MIC.

As shown in FIG. 1, in the MMIC according to the first embodiment, an element isolation region 2 in which, for example, B is ion-implanted is provided in a semi-insulating GaAs substrate 1. An insulating film 3 such as a Si ₃ N ₄ film is provided on the semi-insulating GaAs substrate 1.
Interlayer insulating films 4 and 5 such as a SiO ₂ film are sequentially provided on the insulating film 3.

A p ^-- type region 6 is provided in the semi-insulating GaAs substrate 1 surrounded by the element isolation region 2. In the p ⁻ type region 6, an n type channel region 7, an n ⁺ type source region 8 and a drain region 9 are provided.
Further, a p ⁺ type gate region 10 is provided in the n type channel region 7. Then, the n-type channel region 7,
The gate region 10, the source region 8 and the drain region 9 form a JFET. Contact holes C1, C2, and C3 are provided in the insulating film 3 and the interlayer insulating films 4 and 5 at the portions corresponding to the gate region 10, the source region 8, and the drain region 9, respectively. A gate electrode 11 which makes ohmic contact with the gate region 10 is provided through the contact hole C1, and a source electrode 12 which makes ohmic contact with the source region 8 is provided through the contact hole C2.
A drain electrode 13 that makes ohmic contact with the drain region 9 is provided through the electrode 3.

An n-type region 14 is provided in another portion of the semi-insulating GaAs substrate 1 surrounded by the element isolation region 2. This n-type region 14 constitutes a resistor. Contact holes C are formed in the insulating film 3 and the interlayer insulating films 4 and 5 at portions corresponding to one end and the other end of the n-type region 14.
4 and C5 are provided. Then, electrodes 15 and 16 which make ohmic contact with the n-type region 14 through the contact holes C4 and C5 are provided. These electrodes 15 and 16 are formed of ohmic metal in the same layer as the source electrode 12 and the drain electrode 13.

An electrode 17 is provided between the interlayer insulating film 4 and the interlayer insulating film 5 in the capacitor region. The electrode 17 includes a source electrode 12 and a drain electrode 13
It is formed of the same layer as the ohmic metal.

Reference numerals 18, 19, 20, 21, and 22 denote electrodes formed in the contact holes C1, C2, C3, C4, and C5, respectively. These electrodes 18 to 22 are the gate electrode 11, the source electrode 12, and the drain electrode 1, respectively.
3, connected to the electrodes 15 and 16. In addition, the electrode 21
Extend to the capacitor region on the interlayer insulating film 5.

For example, Si so as to cover the electrodes 18 to 22.
An interlayer insulating film 23 such as an O ₂ film is provided. Contact holes C6 and C7 are provided in the interlayer insulating film 23 at portions corresponding to the electrodes 20 and 22. Further, in the interlayer insulating film 23 and the interlayer insulating film 5, a contact hole C8 is provided in a predetermined portion of the capacitor region.

On the inter-layer insulation film 23, a wiring composed of a metal film 24 and a plating layer 25 having a predetermined shape is provided as an air bridge wiring. This wiring composed of the metal film 24 and the plated layer 25 is connected to the electrode 20 and hence the drain electrode 13 of the JFET through the contact hole C6, and also through the contact hole C7 to the electrode 22 and thus the electrode of the n-type region 14 constituting the resistance. It is connected to 16. The wiring formed of the metal film 24 and the plated layer 25 is connected to the electrode 17 through the contact hole C8. Furthermore, plated layer 2
A passivation film 26 such as a SiN film is provided so as to cover the film 5.

In this MMIC, the electrode 17, the inter-layer insulating film 5 on it and the electrode 21 on it form a first capacitor, and the electrode 21 and the inter-layer insulating film 2 on it.
A second capacitor is composed of 3 and the wiring formed of the metal film 24 and the plated layer 25 thereon. The first capacitor and the second capacitor have a common electrode 21, and one electrode of the first capacitor,
That is, the electrode 17 and one electrode of the second capacitor,
That is, the wiring formed of the metal film 24 and the plated layer 25 is connected to each other through the contact hole C8. Therefore, the first capacitor and the second capacitor are connected in parallel.

Further, one electrode of the second capacitor, that is, the wiring composed of the metal film 24 and the plated layer 25, is
It is connected to the drain electrode 13 of the JFET via the electrode 20. Therefore, one electrode of the first capacitor, that is, electrode 17 is also the drain electrode 1 of the JFET.
3 is connected. Further, the common electrode of the first capacitor and the second capacitor, that is, the electrode 21 is connected to the electrode 15 of the n-type region 14 forming the resistor.

Next, the first structure constructed as described above
A method of manufacturing the MMIC according to the embodiment will be described. 2 to 7 show the MMIC according to the first embodiment.
FIG. 6 is a cross-sectional view showing the manufacturing process of.

In order to manufacture the MMIC according to the first embodiment, as shown in FIG. 2, the gate electrode 11 is formed according to a normal manufacturing process of the MMIC, and the interlayer insulating film is formed on the entire surface by, for example, the CVD method. 4 is formed, a resist pattern 31 having a predetermined shape in which portions corresponding to one end and the other end of the source region 8, the drain region 9 and the n-type region 14 are opened is formed on the interlayer insulating film 4.
Next, using the resist pattern 31 as a mask, the interlayer insulating film 4 and the insulating film 3 in a predetermined portion are etched and removed by, for example, a reactive ion etching (RIE) method to form contact holes C2 to C5.

Next, as shown in FIG. 3, a resist pattern 32 having a predetermined shape in which contact holes C2 to C5 and a portion corresponding to the capacitor region are opened is formed on the resist pattern 31, and then the resist pattern 32 is used as a mask. By patterning the resist pattern 31 as, the resist pattern 31 in the capacitor region is opened.

Next, as shown in FIG. 4, using the resist pattern 32 and the resist pattern 31 as a mask, an ohmic film such as an AuGe / Ni film is formed on the entire surface of the semi-insulating GaAs substrate 1 by, for example, vacuum deposition or sputtering. The metal film 33 is formed.

Next, the resist pattern 32 and the resist pattern 31 are removed together with the ohmic metal film 33 on the resist pattern 32. Thereby, as shown in FIG. 5, the source electrode 12, the drain electrode 13, and the electrodes 15, 16 and 17 are formed.

Next, as shown in FIG. 6, semi-insulating GaA
After the interlayer insulating film 5 such as a SiO ₂ film is formed on the entire surface of the substrate 1 by the CVD method, the portions of the interlayer insulating film 5 corresponding to the contact holes C1 to C5 are removed. Next, a metal film such as a gold (Au) film is formed on the entire surface of the semi-insulating GaAs substrate 1 by, for example, a vacuum deposition method or a sputtering method, and then this metal film is patterned by etching to form the electrodes 18 to 22. To form.

Next, as shown in FIG. 7, semi-insulating GaA
After the interlayer insulating film 23 such as a SiO ₂ film is formed on the entire surface of the substrate 1 by the CVD method or the like, predetermined portions of the interlayer insulating film 23 and the interlayer insulating film 5 are removed by etching, whereby the contact holes C6 to Form C8.

Next, as shown in FIG. 1, the interlayer insulating film 23 is formed.
After forming a resist pattern (not shown) of a predetermined shape for forming an air bridge wiring on the top, a metal film 24 is formed on the entire surface by, for example, a vacuum deposition method or a sputtering method.
Next, the metal film 24 is patterned into a predetermined shape.
Next, a plating layer 2 is formed on the metal film 24 by electroplating.
5 is formed. After that, by plasma CVD method or the like,
A passivation film 26 is formed on the entire surface.

As described above, the desired MMIC is manufactured.

As described above, according to the first embodiment, in addition to the electrode 21 and the wiring including the metal film 24 and the plating layer 25 similar to the conventional MMIC shown in FIG. The electrode 17 is provided so as to substantially overlap with the electrode 21, and the electrode 17, the interlayer insulating film 5 thereon and the electrode 21 thereon constitute a first capacitor, and the electrode 21 and the interlayer above The insulating film 23 and the wiring formed of the metal film 24 and the plated layer 25 on the insulating film 23 constitute a second capacitor stacked on the first capacitor. Then, the first capacitor and the second capacitor are connected in parallel with the electrode 21 being common. Therefore, assuming that the capacitances of the first capacitor and the second capacitor are substantially equal to each other, the area of the capacitor required to obtain the same capacitance is about 1 / th that of the conventional MMIC shown in FIG. The area of 2 is enough. That is, the area of the capacitor can be significantly reduced. Then, by this, the element area can be reduced.

For the electrode 17, the source electrode 12 and the drain electrode 1 can be obtained by simply adding a lithography process for forming the resist pattern 32 to the conventional lift-off method.
Since it can be formed simultaneously with 3 and the electrodes 15 and 16 by the same layer of ohmic metal, an increase in the number of manufacturing steps can be suppressed to a minimum and manufacturing costs can be suppressed to a low level.

Next, M according to the second embodiment of the present invention.
The MIC will be described.

As shown in FIG. 8, in the MMIC according to the second embodiment, the MMI according to the first embodiment is used.
In addition to the structure C, an electrode 34 is further provided between the insulating film 3 and the interlayer insulating film 4 in the capacitor region. The electrode 34 is formed of an ohmic metal in the same layer as the gate electrode 11. Further, the electrode 34 is connected to the electrode 21 through the contact hole C4. The other configuration is the MM according to the first embodiment.
The description is omitted because it is the same as the IC.

In the MMIC according to the second embodiment, the electrode 34, the interlayer insulating film 4 formed thereon and the electrode 17 formed thereon constitute a first capacitor, and the electrode 17 and the interlayer insulating film 5 formed thereon are formed. A second capacitor is formed by the electrode 21 and the electrode 21 thereon, and further, the electrode 21, the interlayer insulating film 23 thereon, the metal film 24 thereon and the plating layer 25.
A third capacitor is formed by the wiring consisting of. Of these first capacitor, second capacitor and third capacitor, the first capacitor and the second capacitor have a common electrode 17, and the second capacitor and the third capacitor have a common electrode. 21. Further, one electrode of the first capacitor, that is, the electrode 34, and the common electrode 21 of the second capacitor and the third capacitor are connected to each other through the contact hole C4. Further, the common electrode 17 of the first capacitor and the second capacitor, and one electrode of the third capacitor, that is, the metal film 24 and the plating layer 2
The wiring composed of 5 is connected to each other through a contact hole C8. Therefore, the first capacitor, the second capacitor, and the third capacitor are connected in parallel.

Further, one electrode of the third capacitor, that is, the wiring formed of the metal film 24 and the plating layer 25, is
It is connected to the drain electrode 13 of the JFET via the electrode 20. Further, the common electrode of the second capacitor and the third capacitor, that is, the electrode 21 is connected to the electrode 15 of the n-type region 14 forming the resistor.

Next, this second, constructed as described above,
A method of manufacturing the MMIC according to the embodiment will be described. 9 to 12 show the MMI according to the second embodiment.
It is sectional drawing which shows the manufacturing process of C.

That is, the MM according to the second embodiment
In order to manufacture an IC, as shown in FIG.
Contact hole C according to the normal manufacturing process of
After forming up to 1, an ohmic metal film is formed on the entire surface by a vacuum vapor deposition method or a sputtering method, and the ohmic metal film is patterned by, for example, an ion milling method to form the gate electrode 11 and the electrode 34.

Next, as shown in FIG. 10, for example, CVD
After the interlayer insulating film 4 is formed on the entire surface by the method, the source region 8, the drain region 9 and the n-type region 1 are formed on the interlayer insulating film 4.
A resist pattern (not shown) having a predetermined shape in which portions corresponding to one end and the other end of 4 are opened is formed. Next, using the resist pattern as a mask, the interlayer insulating film 4 and the insulating film 3 in a predetermined portion are removed by etching to form contact holes C2 to C5. Next, after forming a resist pattern (not shown) of a predetermined shape in which contact holes C2 to C5 and portions corresponding to the capacitor regions are opened on this resist pattern, the resist pattern of the lower layer is used as a mask with the resist pattern of the upper layer as a mask. Is patterned to open the resist pattern in the lower layer of the capacitor region. Next, using these upper layer resist pattern and lower layer resist pattern as a mask,
An ohmic metal film (not shown) such as an AuGe / Ni film is formed on the entire surface of the semi-insulating GaAs substrate 1 by, for example, a vacuum deposition method or a sputtering method.

Next, the upper layer resist pattern and the lower layer resist pattern are removed together with the ohmic metal film on the upper layer resist pattern. As a result, FIG.
As shown in, the source electrode 12, the drain electrode 13 and the electrodes 15, 16 and 17 are formed.

Next, as shown in FIG. 11, semi-insulating Ga
After the interlayer insulating film 5 such as a SiO ₂ film is formed on the entire surface of the As substrate 1 by, for example, the CVD method, the portions of the interlayer insulating film 5 corresponding to the contact holes C1 to C5 are removed. Next, a metal film such as an Au film is formed on the entire surface of the semi-insulating GaAs substrate 1 by, for example, a vacuum vapor deposition method or a sputtering method, and then this metal film is patterned by etching to form electrodes 18 to 22. .

Next, as shown in FIG. 12, semi-insulating Ga
For example, SiO _{2 is formed on} the entire surface of the As substrate 1 by the CVD method.
After forming the interlayer insulating film 23 such as a film, contact holes C6 to C8 are formed by etching away a predetermined portion of the interlayer insulating film 23 and the interlayer insulating film 5.

Next, as shown in FIG. 9, the interlayer insulating film 23 is formed.
After forming a resist pattern (not shown) of a predetermined shape for forming an air bridge wiring on the top, a metal film 24 is formed on the entire surface by, for example, a vacuum deposition method or a sputtering method.
Next, the metal film 24 is patterned into a predetermined shape.
Next, a plating layer 2 is formed on the metal film 24 by electroplating.
5 is formed. After that, by plasma CVD method or the like,
A passivation film 26 is formed on the entire surface.

As described above, the desired MMIC is manufactured.

As described above, according to the second embodiment, in addition to the electrode 21 similar to the conventional MMIC shown in FIG. 13, the wiring including the metal film 24 and the plating layer 25,
The electrode 17 in the lower layer of the electrode 21 is provided so as to substantially overlap with the electrode 21, and the electrode 34 in the lower layer of the electrode 17 is provided so as to substantially overlap with the electrode 17. Then, the electrode 34, the interlayer insulating film 4 formed thereon and the electrode 17 formed thereon form a first capacitor, and the electrode 17 and the interlayer insulating film 5 formed thereon and the electrode 21 formed thereon form a second capacitor.
Is formed, and further, the electrode 21, the interlayer insulating film 23 on the electrode 21, the metal film 24 on the electrode 21, and the plating layer 2 are formed.
The wiring composed of 5 forms a third capacitor,
These first capacitor, second capacitor and third capacitor are sequentially stacked. The first capacitor and the second capacitor are connected in parallel with the electrode 17 in common, and the second capacitor and the third capacitor are connected in parallel with the electrode 21 in common. Therefore, these first capacitors, the second
And the third capacitor are connected in parallel with each other. Therefore, assuming that the capacitances of the first capacitor, the second capacitor, and the third capacitor are substantially equal to each other, the area of the capacitor required to obtain the same capacitance is the same as that of the conventional MMIC shown in FIG. Compared to the area of about 1/3. In addition, M according to the first embodiment
The area is about 2/3 of that of the MIC. That is, it is possible to further reduce the area of the capacitor.
Then, by this, the element area can be reduced.

The electrode 34 can be formed simultaneously with the gate electrode 11 by using the same layer of ohmic metal, and the electrode 17 can be formed by adding the lithography process once to the conventional lift-off method. Since the electrodes 13 and the electrodes 15 and 16 can be simultaneously formed of the same layer of ohmic metal, the increase in the number of manufacturing steps can be minimized and the manufacturing cost can be suppressed low.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, the above-mentioned first embodiment and second embodiment
In the above embodiment, the electrode 17 of the capacitor is formed by the ohmic metal film in the same layer as the source electrode 12, the drain electrode 13 and the electrodes 15 and 16. However, this ohmic metal film is further utilized for forming the wiring. Good.
In this case, the wiring made of this ohmic metal film is provided in the lower layer of the wiring formed by the metal film for forming the electrodes 18 to 22, and the wirings of the upper and lower layers are used as the wiring. By doing so, it is possible to reduce the resistance of the wiring by the amount of the wiring in the lower layer made of the ohmic metal film. In this case, since it is not necessary to form a thick metal film for forming the electrodes 18 to 22 to reduce the resistance of the wiring, the film formation time and the amount of metal used for film formation do not increase.

[0068]

As described above, according to the semiconductor device of the present invention, since at least one electrode of the transistor and one electrode of the capacitor are formed of the same layer material, the multilayer structure of the capacitor is obtained. Due to
The area of the capacitor can be reduced.

Further, according to the method of manufacturing the semiconductor device of the present invention, at least one electrode of the transistor and one electrode of the capacitor are simultaneously formed by using the material of the same layer. Therefore, the semiconductor device of the present invention can be easily manufactured. It can be manufactured in process.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of an MMIC according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the method of manufacturing the MMIC according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the MMIC according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the MMIC according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the MMIC according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the MMIC according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the MMIC according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing the structure of an MMIC according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the MMIC according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the MMIC according to the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the MMIC according to the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the method of manufacturing the MMIC according to the second embodiment of the invention.

FIG. 13 is a sectional view showing the structure of an MMIC according to a conventional technique.

FIG. 14 is a cross-sectional view showing the method of manufacturing the MMIC according to the conventional technique.

FIG. 15 is a cross-sectional view showing the method of manufacturing the MMIC according to the conventional technique.

FIG. 16 is a cross-sectional view showing the method of manufacturing the MMIC according to the conventional technique.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 element isolation region 3 insulating film 4, 5, 23 interlayer insulating film 6 p ⁻ type region 7 n type channel region 8 source region 9 drain region 10 gate region 11 gate electrode 12 source region 13 drain electrode 14 n-type region 15 to 22, 34 electrode 24 metal film 25 plating layer 26 passivation film 31, 32 resist pattern 33 ohmic metal film

Claims (10)

[Claims] 1. A semiconductor device having at least a transistor and a capacitor, wherein at least one electrode of the transistor and one electrode of the capacitor are formed of the same layer material. . 2. The transistor is a field effect transistor, wherein a source electrode and a drain electrode of the field effect transistor and one electrode of the capacitor are formed of the same layer material. Item 1. The semiconductor device according to item 1. 3. The transistor is a field effect transistor, and the gate electrode of the field effect transistor and one electrode of the capacitor are formed of the same layer material. Semiconductor device. 4. The transistor is a bipolar transistor, wherein at least one electrode of the emitter electrode, base electrode and collector electrode of the bipolar transistor and one electrode of the capacitor are formed of the same layer material. The semiconductor device according to claim 1, wherein 5. A semiconductor device comprising at least a field effect transistor and a capacitor, wherein the gate electrode of the field effect transistor is provided on a semiconductor substrate, and the gate electrode is provided on the semiconductor substrate via an insulating film. And a source electrode and a drain electrode of the field effect transistor on the semiconductor substrate, and a first interlayer insulating film on the first electrode. And a second electrode formed of the same layer material as the source electrode and the drain electrode, the second electrode being provided via the second interlayer insulating film. A third electrode connected at a predetermined portion to the first electrode, provided on the third electrode via a third interlayer insulating film, and connected to the second electrode. A fourth electrode connected at the portion, the first electrode, the first interlayer insulating film and the second
A second capacitor, a second capacitor, a second interlayer insulating film, and a third capacitor.
A second capacitor is formed by the electrode of, and the third electrode, the third interlayer insulating film, and the fourth electrode.
A third capacitor is formed by the electrode of, and the first capacitor, the second capacitor, and the third capacitor are connected in parallel. 6. A method of manufacturing a semiconductor device having at least a transistor and a capacitor, comprising the step of simultaneously forming at least one electrode of the transistor and one electrode of the capacitor with a material of the same layer. Of manufacturing a semiconductor device. 7. The transistor is a field effect transistor, and the source electrode and the drain electrode of the field effect transistor and one electrode of the capacitor are simultaneously formed of the same layer material. Of manufacturing a semiconductor device of. 8. The semiconductor device according to claim 6, wherein the transistor is a field-effect transistor, and the gate electrode of the field-effect transistor and one electrode of the capacitor are simultaneously formed of the same layer material. Manufacturing method. 9. The transistor is a bipolar transistor, and at least one electrode of the emitter electrode, the base electrode, and the collector electrode of the bipolar transistor and one electrode of the capacitor are simultaneously formed of the same layer material. 7. The method of manufacturing a semiconductor device according to claim 6, wherein. 10. A method of manufacturing a semiconductor device having at least a transistor and a capacitor, wherein a first opening is formed in a portion corresponding to a formation region of at least one electrode of the transistor on an insulating film formed on a semiconductor substrate. Forming a first resist pattern having: a step of exposing the surface of the semiconductor substrate by etching the insulating film using the first resist pattern as a mask; and, on the first resist pattern, Forming a second resist pattern having a second opening in a portion corresponding to the first opening and a portion corresponding to a formation region of one electrode of the capacitor, and using the second resist pattern as a mask Patterning the first resist pattern, and forming a conductive film on the semiconductor substrate Process and method of manufacturing a semiconductor device characterized by a step of removing together with the first resist pattern and the second resist pattern the conductive film formed thereon the.