JPH09102773A - ATM / STM converter - Google Patents

Abstract

(57) Abstract: To improve data quality without losing normal data when overflow occurs. An overflow underflow determination circuit 4 monitors overflow and underflow of a data memory circuit 1 on the basis of a write address from a write address generation circuit 2 and a read address from a read address generation circuit 3, and outputs an overflow signal. It writes to the data memory circuit 1 and outputs an underflow signal to the OR circuit 6.
The OR circuit 6 performs a logical sum operation of the overflow information read from the data memory circuit 1 and the underflow signal from the overflow underflow determination circuit 4, and outputs the operation result to the data clamp circuit 5. The data clamp circuit 5 immediately clamps the read data from the data memory circuit 1 according to the calculation result from the OR circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM / STM converter, and more particularly to an ATM (Asynchronous).
Transmit Mode) ATM data and STM for information such as voice and image in terminals accommodated in a network
(Synchronous Transmit Mod
e) Concerning conversion with data.

[0002]

2. Description of the Related Art Since an ATM signal rides on an information transmission basket called an ATM cell and is sent to a partner device, jitter (jitter) is generated every time it passes through a cross-connect device and a cell multiplexing device in an ATM network. Will end up.

On the other hand, the STM signal is an isochronous signal which does not cause fluctuation like the ATM signal, and the continuity and periodicity of information must be kept constant.

In the ATM / STM conversion circuit for converting the ATM signal and the STM signal, the ATM signal is temporarily stored, and the stored data is read out at an isochronous timing without fluctuation, so that the ATM signal and the STM signal can be read. Is being converted. In that case, as a circuit for temporarily storing the ATM signal, a buffer memory [for example, a FIFO (first-in first-out) memory] capable of sequentially writing and sequentially reading and absorbing delay variation is used.

The memory capacity of this memory circuit is determined according to the fluctuation amount of the ATM signal. The larger the fluctuation amount, the more the memory capacity is required. If there is no fluctuation, the memory capacity may be 1 in principle.

When reading data from the above memory circuit,
That is, when converting to an STM signal, it is necessary to give the STM signal a certain periodicity.
It is necessary to start reading from the memory circuit after the TM signal has been written to some extent, that is, after the amount of data that exceeds the fluctuation amount generated in the ATM signal has been stored. If this read control is not performed, fluctuations in the ATM signal cause the memory circuit to become empty (underflow), resulting in STM.
The signal cycle is broken.

On the other hand, when the fluctuation amount generated in the ATM signal becomes larger than expected and the fluctuation amount exceeds the memory capacity of the memory circuit, an underflow or overflow (memory capacity of the memory circuit becomes full and data is (Unable to write) occurs. In this case, in order to prevent the dust data from being output as the STM signal, generally, the read data from the storage circuit is clamped to notify the abnormal state to the outside.

In this type of ATM / STM conversion circuit, as shown in FIG. 4, a data memory circuit 11, a write address generation circuit 12, and a read address generation circuit 1 are provided.
3, an overflow / underflow determination circuit 14, a data clamp circuit 15, and an OR circuit 16.

The ATM input signal 110 is written in the data memory circuit 11 by the write address 112 from the write address generation circuit 12, and the read address generation circuit 1
The read address 113 from 3 is read from the data memory circuit 11.

The overflow / underflow judgment circuit 14 uses the write address 11 from the write address generation circuit 12.
Overflow and underflow of the data memory circuit 11 are monitored based on 2 and the read address 113 from the read address generation circuit 13, and an overflow signal (alarm) 114 and an underflow signal (alarm) 115 are output.

The OR circuit 16 performs a logical sum operation of the overflow signal 114 and the underflow signal 115 from the overflow / underflow determination circuit 14, and the operation result 1
17 is output to the data clamp circuit 15.

When the overflow / underflow determination circuit 14 detects an overflow or an underflow, the data clamp circuit 15 calculates the result 11 from the OR circuit 16.
7, the read data 111 from the data memory circuit 11 is immediately clamped. The data clamp circuit 1
If the overflow underflow determination circuit 14 detects neither overflow nor underflow, the read data 111 is output as the STM output signal 116 as it is.

The above-mentioned ATM / STM conversion circuit operates as shown in FIG. 6, and in that case, the data memory circuit 11
Shows a memory map as shown in FIG.

The ATM input signal 110 is 1-cell n-bit data (n is a positive integer), and has fluctuation in cell units. The write address generation circuit 12 is composed of an increment counter (not shown) that operates each time an ATM cell is input, and outputs a write address 112. In this case, since the data memory circuit 11 has a 4-bank configuration, the write address 112 is “1” → “2” →
Change from “3” → “4” → “1” → ...

The read address generation circuit 13 is composed of an increment counter (not shown) which operates periodically based on the timing signal 118 having a fixed cycle from the STM side, and outputs the read address 113. In this case, the read address 113 is also “1” → “2” → “3” → “4” → “1” → ...
... and change. The read address generation circuit 13 is started after ΔT has passed since the write address generation circuit 12 was started (after the writing of two cells).

As described above, the data memory circuit 11 is a 4-cell buffer and is composed of the write address 112 from the write address generating circuit 12 and the read address generating circuit 1.
3 and the read address 113 from FIG.
It operates as shown in FIG.

The overflow / underflow determination circuit 14 outputs the overflow signal 114 and the underflow signal 115 by subtracting and comparing the write address 112 and the read address 113. That is, the subtraction result of the overflow / underflow determination circuit 14 indicates the number of staying cells in the data memory circuit 11, and when a read is performed with the staying cell number of 0, an underflow occurs and the staying cell number of 4
If a light comes in, it will overflow.

The overflow signal 114 and the underflow signal 115 are logically ORed by the OR circuit 16 and output to the data clamp circuit 15. As described above, the data clamp circuit 15 clamps data to all "0" s or the like in order to prevent a lower device (not shown) from malfunctioning due to abnormal data when the data memory circuit 11 is abnormal. Is.

[0019]

SUMMARY OF THE INVENTION The conventional ATM described above.
In the / STM conversion circuit, when an overflow occurs in the data memory circuit, for example, when the cell H is read from the data memory circuit 11 in FIG. 6 and the overflow occurs when the cell M is written in the data memory circuit, the data clamp is performed. Since the circuit immediately clamps the data read from the data memory circuit, the cells I, J, K, and L retained in the data memory circuit are immediately clamped by the data clamp circuit. , K, L to S
It cannot be output as a TM output signal.

Therefore, an object of the present invention is to solve the above problems and improve the data quality without losing normal data at the time of overflow.
It is to provide a conversion device.

[0021]

An ATM / S according to the present invention.
The TM conversion device is an ATM / STM conversion device including a buffer memory for converting a cell for an asynchronous transfer mode into data of a synchronous transfer mode, and a detection means for detecting overflow and underflow of the buffer memory, Holding means for holding the overflow information detected by the detection means in correspondence with the overflow detection position, and clamps read data from the buffer memory when the overflow information is read from the holding means. And clamping means.

Another ATM / STM converter according to the present invention is an ATM / STM including a buffer memory for converting cells for asynchronous transfer mode into data for synchronous transfer mode.
A TM conversion device, comprising: a detection unit that detects an overflow and an underflow of the buffer memory; a holding unit that holds information on the overflow detected by the detection unit in correspondence with a detection position of the overflow; Clamping means for clamping the read data from the buffer memory when the overflow information is read from the holding means and the underflow is detected by the detecting means.

Another ATM / STM converter according to the present invention is an ATM / STM including a buffer memory for converting cells for asynchronous transfer mode into data for synchronous transfer mode.
A TM conversion device, comprising: detection means for detecting overflow and underflow of the buffer memory based on a write address and a read address for the buffer memory; and the detection corresponding to the cell written in the buffer memory. Holding means for holding overflow information indicating whether or not the overflow is detected by the means, and clamping means for clamping read data from the buffer memory when the overflow information is read from the holding means. .

Still another ATM / STM converter according to the present invention is an AT including a buffer memory for converting cells for asynchronous transfer mode into data for synchronous transfer mode.
An M / STM conversion device, comprising: detection means for detecting an overflow and an underflow of the buffer memory based on a write address and a read address for the buffer memory; and a cell to be written in the buffer memory. Holding means for holding overflow information indicating whether or not the overflow is detected by the detecting means, and reading of the overflow information from the holding means and detection of the underflow by the detecting means are performed. And a clamp means for clamping the read data from the buffer memory.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

By passing the overflow alarm detected by the overflow underflow judgment circuit, that is, the overflow alarm generated at the timing of the ATM signal system, through the data memory circuit, the processing for the overflow alarm by the data clamp circuit is changed to the timing of the STM signal system. Since it can be processed, it becomes possible to relieve the staying cell in the data memory circuit which has been conventionally clamped.

In a system in which fluctuations in ATM cells are large, the memory capacity of the data memory circuit is large and the number of staying cells in the data memory circuit is also large. Therefore, if these staying cells can be relieved, the effect of preventing data loss in the system will be obtained. It becomes big.

That is, in general, a large time rate of cell fluctuation is very small, and therefore data loss is more likely to occur than in the conventional method in which the data of the entire data memory is lost each time the cell fluctuation exceeds the data memory amount. Since it can be prevented, the overall data quality can be considerably improved.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure, ATM /
The STM converter comprises a data memory circuit 1, a write address generation circuit 2, a read address generation circuit 3, an overflow underflow determination circuit 4, a data clamp circuit 5, and an OR circuit 6.

The ATM input signal 100 is written in the data memory circuit 1 by the write address 102 from the write address generating circuit 2 and read from the data memory circuit 1 by the read address 103 from the read address generating circuit 3.

The overflow / underflow determination circuit 4 has a write address 102 from the write address generation circuit 2 and a read address 103 from the read address generation circuit 3.
The overflow signal and the underflow signal of the data memory circuit 1 are monitored based on the
Is output to the data memory circuit 1 and an underflow signal (alarm) 105 is output to the OR circuit 6.

The OR circuit 6 performs a logical sum operation of the overflow information 106 read from the data memory circuit 1 and the underflow signal 105 from the overflow underflow determination circuit 4, and outputs the operation result 108 to the data clamp circuit 5. To do.

When the overflow / underflow is detected by the overflow / underflow determination circuit 4, the data clamp circuit 5 immediately reads the read data 10 from the data memory circuit 1 by the operation result 108 from the OR circuit 6.
Clamp 1 The data clamp circuit 5 outputs the read data 101 as it is as the STM output signal 107 if neither overflow nor underflow is detected by the overflow underflow determination circuit 4.

FIG. 2 is a diagram showing a memory map of the data memory circuit 1 of FIG. In the figure, the data memory circuit 1 has a 4-bank structure, and has a structure in which 1 bit is allocated to hold overflow information. That is, in the data memory circuit 1, a storage area 1b from the address 1 area to the address 4 area in which the ATM input signal 100 is written, and a write area 1a in which overflow information is written corresponding to each area of the storage area 1b. It consists of

FIG. 3 is a timing chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

The ATM input signal 100 is 1-cell n-bit data (n is a positive integer), and has fluctuation in cell units. The write address generation circuit 2 is composed of an increment counter (not shown) that operates each time an ATM cell is input, and outputs a write address 102. In this case, since the data memory circuit 1 has a 4-bank configuration, the write address 112 is “1” → “2” → “3”.
→ "4" → "1" → ... changes.

The read address generation circuit 3 is composed of an increment counter (not shown) that operates periodically based on the timing signal 109 having a fixed cycle from the STM side, and outputs the read address 103. In this case, the read address 103 is also “1” → “2” → “3” → “4” → “1” → ...
And change. The read address generating circuit 3 is started after ΔT has passed since the write address generating circuit 2 was started (after the completion of writing of two cells).

The overflow / underflow determination circuit 4 outputs the overflow signal 104 and the underflow signal 105 by subtracting and comparing the write address 102 and the read address 103. That is, the subtraction result of the overflow / underflow determination circuit 4 indicates the number of staying cells in the data memory circuit 1. When a read is entered with the number of staying cells of 0, an underflow occurs and a write is entered with the number of staying cells of 4. If it does, overflow will occur.

The overflow signal 104 is written in the write area 1a of the data memory circuit 1 corresponding to the write position of the ATM input signal 100 when it is detected, and the underflow signal 105 is output to the OR circuit 6.

In the OR circuit 6, the logical sum of the overflow information 106 read from the write area 1a of the data memory circuit 1 and the underflow signal 105 from the overflow underflow judgment circuit 4 is calculated, and the operation result 108 is obtained by the data clamp circuit. Output to 5.

When the data clamp circuit 5 is notified by the operation result 108 from the OR circuit 6 that overflow or underflow is detected by the overflow / underflow determination circuit 4, that is, when the data memory circuit 1 is abnormal, The data is clamped to all "0" or the like in order to prevent a lower device (not shown) from malfunctioning due to the data.

The overflow signal from the overflow underflow determination circuit 4 is "0" at the write position of the write area 1a corresponding to the cells A to L in which the data memory circuit 1 is in the normal state (no alarm state). Therefore, "0" is written.

If the read address is "1" when an M cell is to be written in the address 1 area of the data memory circuit, the overflow / underflow judgment circuit 4 judges by subtraction comparison that the number of staying cells is 4. Because
“1” is output to the overflow signal 104.

"1" of the overflow signal 104 is written in the write area 1a corresponding to the address 1 area, and the timing of reading the data in the address 1 area (the timing of reading the unwritten M cells). Is read from the writing area 1a.

Therefore, after the L cell is read from the data memory circuit 1, the overflow information 106 read from the write area 1a is notified to the data clamp circuit 5 through the OR circuit 6, so that the data clamp circuit 5 is operated by the data memory. The read data 101 from the circuit 1 is clamped to all "0" or the like.

In general, this overflow state is recovered in a short time, so the read data 101 from the data memory circuit 1 is immediately restored to normal data after the overflow state is recovered.

As described above, the overflow alarm detected by the overflow underflow determination circuit 4 (generated at the timing of the ATM signal system) is passed through the data memory circuit 1 to allow the data clamp circuit 5 to process the overflow alarm. Since the processing can be performed by changing to the timing of the signal system, it is possible to relieve the staying cell in the data memory circuit 1 which is conventionally clamped.

In a system in which the fluctuation of ATM cells is large, the memory capacity of the data memory circuit 1 is large and the number of staying cells in the data memory circuit 1 is also large. Therefore, if these staying cells can be relieved, the loss of data in the system can be prevented. The effect is great.

That is, in general, since the large time rate of cell fluctuation is very small, data loss can be suppressed more than in the conventional method in which the data of the entire data memory is lost each time the cell fluctuation exceeds the data memory amount. As a result, it is possible to considerably improve the overall data quality. Therefore, it is possible to improve the data quality without losing normal data at the time of overflow.

[0050]

As described above, according to the present invention, the overflow of the buffer memory is detected in the ATM / STM converter including the buffer memory for converting the cell for the asynchronous transfer mode into the data for the synchronous transfer mode. When the overflow information is read out from the buffer memory when the overflow information is read from the holding means, the overflow information is held in the holding means in correspondence with the overflow detection position. There is an effect that the data quality can be improved without losing the data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a memory map of the data memory circuit of FIG.

FIG. 3 is a timing chart showing the operation of one embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional example.

5 is a diagram showing a memory map of the data memory circuit of FIG. 4;

FIG. 6 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 1 data memory circuit 1a write area 1b storage area 2 write address generation circuit 3 read address generation circuit 4 overflow underflow determination circuit 5 data clamp circuit 6 OR circuit

Claims (4)

[Claims] 1. An A including a buffer memory for converting a cell for an asynchronous transfer mode into data for a synchronous transfer mode.
A TM / STM converter, which is a detection unit for detecting overflow and underflow of the buffer memory,
Holding means for holding the overflow information detected by the detection means in correspondence with the overflow detection position, and clamps read data from the buffer memory when the overflow information is read from the holding means. AT having clamp means
M / STM converter. 2. An ATM / STM conversion device including a buffer memory for converting a cell for an asynchronous transfer mode into data for a synchronous transfer mode, said detection means detecting an overflow and an underflow of the buffer memory. Holding means for holding the overflow information detected by the detecting means in correspondence with the overflow detection position; reading of the overflow information from the holding means; and detection of the underflow by the detecting means. An ATM / STM conversion device comprising: clamp means for clamping read data from the buffer memory when any of the above is performed. 3. An ATM / STM converter including a buffer memory for converting cells for asynchronous transfer mode into data for synchronous transfer mode, wherein the ATM / STM converter is based on a write address and a read address for the buffer memory. Detecting means for detecting overflow and underflow of the buffer memory, holding means for holding overflow information indicating whether or not the overflow is detected by the detecting means in correspondence with the cell written in the buffer memory, AT having a clamp means for clamping read data from the buffer memory when the overflow information is read from the holding means.
M / STM converter. 4. An ATM / STM converter including a buffer memory for converting cells for asynchronous transfer mode into data for synchronous transfer mode, wherein the ATM / STM converter is based on a write address and a read address for the buffer memory. Detecting means for detecting overflow and underflow of the buffer memory, holding means for holding overflow information indicating whether or not the overflow is detected by the detecting means in correspondence with the cell written in the buffer memory, ATM / clamping means for clamping read data from the buffer memory when the overflow information is read from the holding means and the underflow is detected by the detecting means. STM converter.