JPH09102790A - High-speed processing method for received frames - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To gradually reduce a processing delay and improve a frame transfer capability. SOLUTION: A network controller unit 1 sets frame data D1 received from a physical transmission line to an address A1.
Is written to the memory 2. In parallel with this reception processing, the parallel protocol processing unit 3 identifies the frame type of the received frame and determines the transfer destination, and writes the result D2 in the memory 2 at the address A2. The frame transfer processing unit 4 transfers the received frame to the transmission side network interface unit based on the processing result of the protocol processing unit 3. In this way, the reception process and the frame identification process and the transfer destination determination process in the protocol process can be simultaneously performed, and the frame transfer process can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed processing system for speeding up frame processing in a receiving side network interface section in a gateway device.

[0002]

2. Description of the Related Art For a gateway device that connects a plurality of networks to each other and provides frame transfer between the networks, it is desired that the internal processing capacity be improved with the increase of transmission line speed and the spread of multimedia communication. It is rare.
Conventionally, as shown in FIG. 8, in a receiving side network interface section in a gateway device, a network controller section 51 detects the beginning of a received frame from a transmission path and sequentially stores the frame data in a predetermined area of a memory 52. The frame reception process for writing is performed.

Then, the protocol processing unit 53, after the frame receiving process of the network controller unit 51 is completed,
The frame is read from the memory 52, protocol processing is performed, and the transmission side network interface is determined from the destination address. Then, the frame transfer processing unit 54
Transfers the frame to the transmission side network interface unit according to the transfer destination information determined by the protocol processing unit 53.

[0004]

As described above, in the conventional receiving side network interface section, since each processing for the received frame is performed sequentially, the reception of one frame in the network controller section is completed unless the reception is completed. The protocol processing for the frame cannot be executed, and unless the protocol processing is completed, the frame cannot be transferred to the transmission side network interface section, and the transfer processing for one frame takes a long time as a whole. was there.
The present invention has been made to solve the above problems,
An object of the present invention is to provide a high-speed processing method capable of gradually reducing the processing delay and improving the frame transfer capability of the gateway device as a whole.

[0005]

According to the present invention, in a receiving side network interface section of a gateway device,
The network controller unit has a parallel protocol processing unit that performs protocol processing of the received frame in parallel with the frame reception processing of writing the received frame in the memory. As a result, the frame reception process and the protocol process can be performed at the same time. Also, the parallel protocol processing unit identifies the frame type of the received frame and writes the identification result in the memory in association with the received frame. Thus, the frame receiving process and the frame identifying process in the protocol process can be performed at the same time.

Further, the parallel protocol processing unit identifies the frame type of the received frame, and based on the destination logical address in the network layer in the received frame, obtains the transfer destination corresponding to this, according to the frame type. The transfer destination information thus obtained is written in the memory in association with the received frame. Thereby, the frame receiving process and the frame identifying process and the routing process in the protocol process can be performed at the same time. Further, the parallel protocol processing unit obtains a transfer destination corresponding to the destination physical address corresponding to the physical transmission line in the received frame, and writes the obtained transfer destination information in the memory in association with the received frame. Is. This allows
The frame receiving process and the switching process in the protocol process can be performed at the same time.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

1. Embodiment 1. FIG. 1 is a block diagram of a receiving side network interface section showing a high speed processing system according to a first embodiment of the present invention. Reference numeral 1 is a network controller unit that receives a frame from the physical transmission path 5, 2 is a memory that stores the received frame received by the controller unit 1, and 3 is a frame reception process in which the controller unit 1 writes the received frame to the memory 2. A parallel protocol processing unit 4 that performs protocol processing of the received frame is a frame transfer processing unit that transfers the received frame stored in the memory 2 to a transmission side network interface unit (not shown).

Next, the operation of such a receiving side network interface section will be described. The network controller unit 1 receives a frame from the physical transmission line 5, and uses the received frame data D1 as a predetermined write address A1.
Is written in a predetermined area 2a of the memory 2. In parallel with such frame reception processing, the parallel protocol processing unit 3 takes in the write address A1 and the frame data D1 output from the network controller unit 1, identifies the frame type of the received frame, and outputs this identification result. The data is written in the memory 2 in association with the received frame.

FIG. 2 is a block diagram of the parallel protocol processing unit 3. The address decoder 11 fetches the write address A1 output from the controller unit 1 and analyzes the address A1 to start writing the frame data D1 in the memory 2 by the controller unit 1 (hereinafter referred to as frame write start timing). Is detected, and this is notified to the latch pulse generation unit 12.

The latch pulse generator 12 generates a timing pulse for fetching header information from the frame data D1 flowing on the data bus. FIG. 3 (a)
FIG. 3 is a diagram showing a header information portion of the IEEE 802 standard frame format and the Ethernet format frame format, and the vertical size is 32 bits.

In FIG. 3A, 101 is a destination address (MAC Dest. Add .: Media Access Control Destinatio).
n Address) is stored in the field, and 102 is a source address (MAC Sour.Add .: Media Access Control Sou
rce Address) is stored in the field, 103 is a frame type / frame length (Ethernet format; Fram
e Type / IEEE802 standard; Length) is a field that is stored.

Reference numeral 104 denotes a source service access point and a destination service access point field (LLC SSAP DSAP: in the IEEE 802 standard).
Logical Link Control Source Service Access Point D
Destination Service AccessPoint), a field 105 stores control data (LLC Cont .: Logical Link Control Control) in the IEEE 802 standard, and a field 106 stores a sub-network access protocol (LLC SN) in the IEEE 802 standard.
AP: Logical Link Control Sub-Network Access Proto
col) is the field that is stored. In the Ethernet format, data of upper protocols are stored in the fields 104 to 106.

Further, T1 shown in FIG. 3B is a section t1.
Data, that is, a timing pulse for capturing the upper 32 bits of the field 101. Similarly, T2 shown in FIG. 3C is a pulse for fetching the data in the section t2, that is, the lower 16 bits of the field 101 and the upper 16 bits of the field 102, and T3 is the pulse for fetching the lower 32 bits of the field 102. pulse,
T4 is a pulse for fetching data in the section t4, T5
Is a pulse for capturing the data in the section t5, and T6 is a pulse for capturing the data in the section t6.

In the frame format of the IEEE 802 standard and the Ethernet format, it is known in advance where the header information as shown in FIG. 3A is placed. Therefore, the latch pulse generator 12 starts the frame writing. From timing to timing pulse T1-T
6 can be generated. Next, the header comparison unit 13
Analyzes the header information of the received frame and identifies the frame type. FIG. 4 is a block diagram of the header comparison unit 13.

The latch units 21 to 25 transmit the frame data D1 output from the network controller unit 1 to the timing pulse T output from the latch pulse generation unit 12.
Latch by 1, T2, T4 to T6. The address comparison unit 26 stores an address assigned to itself (here, the network controller unit 1) in advance, compares it with the destination address of the field 101 held by the latch units 21 and 22, and It is determined whether the frame received by the unit 1 is addressed to itself.

When it is determined that the addresses do not match and the address is not addressed to itself, the comparison result holding register 1
Of the identification information in 4, the 12th bit from the bottom (B in FIG.
Ridge) is set to bit "1". If the addresses match and it is determined that the address is addressed to itself, the registers 27 to 29 are enabled.

The register 27 stores a section t4 in the header information.
A plurality of data patterns corresponding to the data of (fields 103 and 104) are stored in each area, and when in the enabled state, the data of the section t4 held by the latch circuit 23 is changed to the data pattern stored in each area. The comparison is made, and if they match, the output of the area is set to bit "1". Here, "8137XXXX" is stored as a data pattern in the area 27a of the register 27. Note that all data patterns described below are represented in hexadecimal notation, and “X” is arbitrary data (that is, not subject to comparison).

In the area 27b, "8038XXXX
~ 8042XXXX "is stored and" 6 "is stored in the area 27c.
000XXXX to 6099XXXX "," 0800XXXX "in the area 27d, and" 0806XX "in the area 27e.
XX ”, and“ 0600XXXX ”is stored in the area 27f.

The upper 16 bits of the area 27g are "0000-05DC" and the lower 16 bits are "FFF".
"F" is stored, and "0" is stored in the upper 16 bits of the area 27h.
000-05DC "and the lower 16 bits are" FEF "
"E" and "0000-0" in the upper 16 bits of the area 27i.
5DC "," E0E0 "in the lower 16 bits, area 27
“0000-05DC” is stored in the upper 16 bits of j, “4242” is stored in the lower 16 bits, “0000-05DC” is stored in the upper 16 bits of area 27k, and “AAAAA” is stored in the lower 16 bits.

Further, the register 28 stores a plurality of data patterns corresponding to the data in the section t5 in the header information. When the register 28 is enabled, like the register 27, the section 28 in the section t5 held by the latch circuit 24 is stored. The data is compared with the data pattern stored in each area. In the area 28a of the register 28, "03XXXXXX
"X" is stored, and "0300000" is stored in the area 28b.
0 ", area 28c has" AFXXXXXX ", area 28
"BFXXXXXXX" in d, and "E3X" in area 28e.
“XXXXXXX”, and “F3XXXXXXX” is stored in the area 28f.

Further, the register 29 stores a plurality of data patterns corresponding to the data of the section t6 in the header information. When the register 29 is enabled, the data of the section t6 held by the latch circuit 25 is stored in each area. Compare with the data pattern stored in. Area 29 of this register 29
“8137XXXX” is stored in a, and the area 29b
Is "809BXXX", and the area 29c is "80F3".
“XXXX” is stored.

In such registers 27-29,
For example, when the data held by the latch circuit 23 matches the data pattern stored in the area 27a or 27g, the register 27 outputs the output of this area to bit "1".
Set to. As a result, the comparison result holding register 14
The 11th bit from the bottom (IPX in FIG. 4) is set to “1”. In this way, the frame received by the controller unit 1 is identified as an IPX (Internet Packet Exchange) protocol format frame. Note that for the IPX, "1" may be set even when another condition is satisfied, which will be described later.

The data of the latch circuit 23 is stored in the area 27.
When it matches the data of b or 27c, 1 of register 14
The 0th bit (DECnet) is set to "1".
Thus, the received frame is identified as a digital equipment (DEC) network format frame. When the data in the latch circuit 23 matches the data in the area 27d, the 9th bit (IP: Internet Protocol) of the register 14 is set to "1". This means that the received frame is identified as an IP format frame.

The data of the latch circuit 23 is stored in the area 27.
When it matches the data of e, the 8th bit (ARP: Address Resolusion Protocol) of the register 14 is set to "1". This means that the received frame has been identified as an ARP format frame. When the data in the latch circuit 23 matches the data in the area 27f, the 7th bit of the register 14 (XNS: Xerox Network)
k System) is set to "1". This means that the received frame was identified as a Xerox network format frame.

Next, when the data in the latch circuit 23 matches the data in the area 27h, the register 27 receives the data in the area 27h.
The output of is set to "1", but at this time, register 14
6th bit (OSI: Open Systems Interconnectio)
n) is set to "1" when the buffer 30 is enabled. In order for the buffer 30 to be enabled, the data held in the latch circuit 24 must match the data pattern stored in the area 28a of the register 28. If such a match is established, the enable signal (“1”) is sent to register 2
8 and the buffer 30 is enabled.

Therefore, if the above two conditions are satisfied,
The 6th bit of the register 14 is set to "1", which means that the received frame is identified as a frame of the OSI protocol format.

Further, the data of the latch circuit 23 is stored in the area 27.
When the data of i matches, the output of the area 27i is set to "1". At this time, the 11th bit (IPX) of the register 14 is set to "1" because the same condition as above is satisfied. This is when the buffer 31 is enabled. If the above two conditions are met, register 1
The 11th bit of 4 is set to "1", which means that the received frame is identified as an IPX protocol format frame.

The data of the latch circuit 23 is stored in the area 27.
If the data of j matches, the output of the area 27j is set to "1". At this time, the fifth bit (STP: Spanning Tree Protocol) of the register 14 is set to "1", which is the same as above. This is when the buffer 32 is enabled due to the satisfaction of the condition. If the above two conditions are satisfied, the fifth bit of the register 14 is set to "1". This means that the received frame has been identified as an STP format frame.

The register 28 is connected to the latch circuit 24.
If the data in the area 28c or 28d matches the data in the area 28c or 28d, the 4th bit (XID: Exchange Ide
ntification) to "1". This means that the received frame has been identified as an LLC format frame. Similarly, the data of the latch circuit 24 is stored in the area 2
When it matches the data of 8e or 28f, the third bit (TEST) of the register 14 is set to "1". This means that the received frame has been identified as an LLC format frame.

Next, when the data held by the latch circuit 25 matches the data stored in the area 29a, the register 29 sets the output of the area 29a to "1". At this time, 11 bits of the register 14 are set. Eyes (IPX)
Is set to "1" when the buffer 33 is enabled.

In order to enable the buffer 33, the data of the latch circuit 23 is stored in the area 2 of the register 27.
It is necessary to match the data of 7k and the data of the latch circuit 24 to match the data of the area 28b of the register 28. Due to such coincidence, an enable signal is output from the registers 27 and 28, the output of the AND circuit 36 becomes "1", and the buffer 33 is enabled. Therefore, if the above conditions are satisfied, the 11th bit of the register 14 is set to "1" and the received frame is I
It has been identified as a frame of the PX protocol format.

Further, the data of the latch circuit 25 is stored in the area 29.
If the data of b matches, the output of the area 29b is set to "1". At this time, the second bit (Apple) of the register 14 is set to "1" because the same condition as above is satisfied. This is when the buffer 34 is enabled. If the above two conditions are satisfied, the second bit of the register 14 is set to "1" and the received frame is identified as a network format frame of Apple Inc.

Similarly, the data of the latch circuit 25 is stored in the area 2
If it matches the data of 9c, the output of the area 29c is "1".
The first bit (Apple ARP) of the register 14 is set to "1" at this time.
This is when the buffer 35 is enabled by the satisfaction of the same condition as described above. If the above two conditions are satisfied, the first bit of the register 14 is set to "1",
The received frame has been identified as an Apple network format frame.

To identify the frame type described above, the data patterns in the header information pre-assigned to each protocol format are stored in the registers 27 to 29, and this is compared with the header information of the received frame. It is for identification. By such identification, the corresponding bit among the bits of the register 14 is set to "1".

Next, the address generator 15 generates a write address A2 corresponding to the write address A1 so that the information in the register 14 can be written in the memory 2 in association with the frame data D1 written in the memory 2. In this way, the 16-bit identification information D2 (significant bits are lower 12 bits) held in the comparison result holding register 14 is written in the predetermined area 2b of the memory 2 by the write address A2.

When the type of the received frame is obtained in this way, firmware (not shown) can process the frame stored in the memory 2 based on this. For example, the firmware obtains the transfer destination of this received frame based on the frame type, and passes this to the frame transfer processing unit 4, whereby the frame transfer processing unit 4 is stored in the memory 2 according to this transfer destination information. The received frame is transferred to the corresponding transmission side network interface section.

2 of the embodiment. Next, a case of a protocol process (routing process) for searching a transfer destination from the destination logical address using the destination logical address in the network layer will be described. Also in the present embodiment, the overall configuration of the receiving side network interface unit is almost the same as that of the first embodiment, and the only difference is the parallel protocol processing unit. Therefore, the configuration and operation of this parallel protocol processing unit will be described.

FIG. 5 is a block diagram of a parallel protocol processing unit showing a high speed processing system according to another embodiment of the present invention, and the same components as those in FIG. 2 are designated by the same reference numerals. First, the address decoder 11 detects the frame write start timing as in the first embodiment, and the latch pulse generator 12a generates timing pulses T1 to T6 in the same manner as the latch pulse generator 12.

Next, the internal structure of the header comparing section 13a is as follows.
This is the same as the header comparison unit 13, but the eleven outputs (Brid) written in the register 14 in the first embodiment.
ge is not used) is used as an enable signal of a routing processing unit which will be described later and performs processing independently for each protocol of the network layer.

Routing processing units 16-1 to 16-n
Is provided for each protocol format. Therefore, the frame type is IP as in the first embodiment.
There are 11 types from X to Apple ARP, and if one is provided for each, the number is 11. Each enable signal from the header comparison unit 13a is connected to the routing processing unit corresponding to the frame protocol, and the routing processing unit is activated when the enable signal becomes "1".

Here, the IP routing process using the network address in the IP address as an example of the destination logical address in the network layer will be described. FIG. 6 shows the routing processing units 16-1 to 16-16.
It is a block diagram of the routing processing part corresponding to the frame type (protocol) IP in -n.

The shift register 31 delays the frame data D1 by a predetermined time from the frame writing start timing output from the latch pulse generator 12a,
This is output as frame data D3. This predetermined time is the enable signal IP of bit "1" after the beginning of the frame data D1 is input to the header comparison unit 13a.
This is the time until ena (IP in FIG. 4) is output.

Thus, the start of the frame data D3 and the timing of the enable signal IPena coincide with each other. Then, the buffer 32 is enabled when the received frame is determined to be an IP format frame and the enable signal IPena becomes "1", and the input frame data D3 and the clock signal CLK synchronized with this data D3 are header-latched. It is output to the unit 33.

Next, the header latch section 33 latches the destination IP address in the frame data D3 based on the clock signal CLK. It is known in advance which position in the frame data D3 the destination IP address is stored in, and the destination IP address can be extracted from this.

Subsequently, the address class identification unit 34 determines the network class (A, B or C) from the upper 2 bits of the destination IP address held by the header latch unit 33.
Address mask register 3 according to the class
Assert the value of 5. That is, if it is class A,
Since the upper 8 bits of the IP address are network addresses, this part of the destination IP address is set to bit "1" and the other parts are set to "0".

In the case of class B, the upper 16 bits are the network address, and in class C, the upper 24 bits are the network address. Therefore, similarly, this portion is set to bit "1". Then, the AND circuit 36 takes the logical product of the output value of the address mask register 35 and the destination IP address held in the header latch unit 33. In this way, the network address in the destination IP address is obtained.

Next, in the IP routing table 37, the network addresses IP1 to IPn and the number N1 of the transmission side network interface section (corresponding to 55a to 55c in FIG. 8) corresponding to the network address are stored.
Correspondences with ~ Nn are stored. The IP routing table 37 is searched using the network address obtained by the AND circuit 36 as a key.

The network addresses IP1 to I
If there is an address matching the key in Pn, the number of the transmission side network interface unit corresponding to the address is output. This is the transfer destination information D4. On the other hand, the address generator 38, like the address generator 15, receives the write address A2 corresponding to the write address A1.
Generate

In this way, the transfer destination information D4 output from the parallel protocol processing unit of this embodiment is written in the predetermined area of the memory (area 2 in FIG. 1) by the write address A2.
(corresponding to b). Then, the frame transfer processing unit (processing unit 4 in FIG. 1) transfers the received frame stored in the memory according to the transfer destination information D4 to the corresponding transmission side network interface unit.

3. of the embodiment. Next, a case of a protocol process (switching process) of searching a transfer destination from this address using a destination physical address corresponding to a physical transmission line will be described. Also in the present embodiment, the overall configuration of the receiving side network interface unit is almost the same as that of the first embodiment, and the only difference is the parallel protocol processing unit. Therefore, the configuration and operation of this parallel protocol processing unit will be described. FIG. 7 is a block diagram of a parallel protocol processing unit showing a high speed processing system according to another embodiment of the present invention, and the same components as those in FIG. 2 are designated by the same reference numerals.

Then, a description will be given here of the case where the destination MAC address is the target physical address. First, the address decoder 11 detects the frame write start timing as in the first embodiment, and the latch pulse generation unit 12b causes the timing pulses T1 to T described above.
Among them, pulses T1 and T2 are generated.

The header latch unit 17 receives the destination MAC in the frame data D1 according to the timing pulses T1 and T2.
Latch the address (101 in FIG. 3). Next, in the switching table 18, the destination MAC addresses MA1 to MA1
The correspondence relationship between MAn and the numbers N1 to Nn of the transmission side network interface units connected to the physical transmission path where the terminal having the MAC address exists is stored.

The switching table 18 is searched using the destination MAC address held by the header latch section 17 as a key. The destination MAC address M
If there is an address that matches the key in A1 to MAn, the number of the transmission side network interface unit corresponding to the address is output. This is the transfer destination information D5.

On the other hand, the address generator 19 generates the write address A2 corresponding to the write address A1 similarly to the address generator 15. In this way, the transfer destination information D5 output from the parallel protocol processing unit of the present embodiment is written in the predetermined area (corresponding to the area 2b in FIG. 1) of the memory by the write address A2. Then, the frame transfer processing unit (processing unit 4 in FIG. 1)
Transfers the received frame stored in the memory according to the transfer destination information D5 to the corresponding transmission side network interface section.

Note that the transport layer (fourth layer) for frame conversion, security functions, accounting processing, etc.
Only the relay device having the above functions may be referred to as a gateway device (here, a gateway device in a narrow sense), but the present invention can be applied to a gateway device in a broad sense that connects networks. That is, a bridge (corresponding to the gateway device in the third embodiment) operating in the data link layer (second layer) and a router (the gateway device in the first and second embodiments) operating in the network layer (third layer) and below. Needless to say, it is applicable to a network relay device such as a bruta in which these are combined, and is not limited to the gateway device in the narrow sense described above.

[0056]

According to the present invention, the network controller unit performs the protocol processing in parallel with the frame receiving processing for writing the received frame in the memory, so that the protocol processing can be performed without waiting for the completion of writing the received frame in the memory. It can be started, and the protocol processing is completed at the end of writing the received frame to the memory by performing the protocol processing in the parallel protocol processing unit (hardware), so the frame transfer can be executed immediately. . This shortens the overall processing time at the receiving side network interface unit,
It is possible to speed up the frame transfer process.

Further, the parallel protocol processing unit identifies the frame type of the received frame and writes the identification result in the memory, whereby the frame receiving process and the frame identifying process in the protocol process can be performed at the same time. It is possible to immediately execute frame transfer to a unit that performs the next process such as determination of a transfer destination according to.

Further, the parallel protocol processing section identifies the frame type of the received frame, obtains the transfer destination corresponding to the destination logical address, and writes the obtained transfer destination information in the memory, thereby performing the frame receiving process and the protocol process. The frame identification process and the routing process can be performed at the same time, and since the transfer destination is determined when the writing of the received frame to the memory is completed, the frame transfer to the transmission side network interface unit can be immediately executed.

Further, the parallel protocol processing unit obtains the transfer destination corresponding to the destination physical address and writes the obtained transfer destination information in the memory, so that the frame receiving process and the switching process in the protocol process can be performed at the same time. Since the transfer destination is determined at the end of writing the received frame to the memory, the frame transfer to the transmission side network interface unit can be executed immediately.

[Brief description of the drawings]

FIG. 1 is a block diagram of a receiving-side network interface section showing a high-speed processing system according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a parallel protocol processing unit in FIG.

3 is a timing chart showing the relationship between the timing pulse generated by the latch pulse generation unit of FIG. 2 and header information.

FIG. 4 is a block diagram of a header comparison unit in FIG.

FIG. 5 is a block diagram of a parallel protocol processing unit showing a high-speed processing system according to another embodiment of the present invention.

FIG. 6 is a block diagram of a routing processing unit corresponding to a frame type IP.

FIG. 7 is a block diagram of a parallel protocol processing unit showing a high-speed processing system according to another embodiment of the present invention.

FIG. 8 is a block diagram of a conventional receiving-side network interface unit.

[Explanation of symbols]

1 ... Network controller section, 2 ... Memory, 3 ... Parallel protocol processing section, 4 ... Frame transfer processing section.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Kurokawa 5-2-6 Toranomon, Minato-ku, Tokyo Stock company ultra-high-speed network computer technology research institute

Claims (4)

[Claims] 1. A reception side network interface section of a gateway device having a network controller section for receiving a frame from a physical transmission line and a memory for storing the reception frame received by the controller section, wherein the network controller section receives the reception frame. A high-speed processing method for a received frame, which has a parallel protocol processing unit for performing a protocol processing of the received frame in parallel with the frame receiving processing for writing the data into the memory. 2. The high-speed processing method for a received frame according to claim 1, wherein the parallel protocol processing unit identifies a frame type of the received frame and writes the identification result in a memory in association with the received frame. Yes, a high-speed processing method for received frames, characterized in that the frame reception processing and the frame identification processing in the protocol processing are simultaneously performed. 3. The high-speed processing method for a received frame according to claim 1, wherein the parallel protocol processing unit identifies a frame type of the received frame, and based on a destination logical address in a network layer in the received frame, Is performed according to the frame type, and the obtained transfer destination information is written in the memory in association with the received frame. The frame receiving process and the frame identifying process and the routing process in the protocol process are performed. A high-speed processing method for received frames, which is characterized by performing simultaneously. 4. The high-speed processing system for a received frame according to claim 1, wherein the parallel protocol processing unit determines a transfer destination corresponding to a destination physical address according to a physical transmission line in the received frame. A high-speed processing method for a received frame in which the obtained transfer destination information is written in a memory in association with the received frame, and the frame receiving process and the switching process in the protocol process are simultaneously performed.