JPH09130231A - Semiconductor integrated device - Google Patents

Abstract

(57) Abstract: In a semiconductor integrated device using a deep submicron process or a semiconductor integrated device aiming at ultra-low power consumption, a wiring change such as an aluminum wiring is performed by using, for example, a 3v system miniaturization process. A signal voltage level conversion circuit capable of quickly converting a narrow logic amplitude signal of a low power supply voltage of 2v system or 1v system into a wide logic amplitude signal of a high power supply voltage with the same power consumption as the conventional one. I will provide a. SOLUTION: First and second M of a signal voltage level conversion circuit
A first inversion logic circuit including first and second conductivity type MOS transistors for switching control of the OS transistor
The conductivity type MOS transistor applies a first power supply voltage, which is higher than the ground power supply voltage level, to a well that is a back gate electrode of the first conductivity type MOS transistor, and is higher than the ground power supply voltage level and at a first level. A second power supply voltage higher than the first power supply voltage level is applied to the source electrode of the first conductivity type MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor provided with a signal voltage level conversion circuit for converting an input signal having a narrow logical amplitude in the range of 0 to 3v into an output signal having a wide logical amplitude in the range of 0 to 5v. Regarding an integrated device.

[0002]

2. Description of the Related Art In a semiconductor integrated device using a semiconductor miniaturization process such as a submicron design rule,
The power supply voltage of the internal circuit is 5v from the viewpoint of reliability and power consumption.
It is in the direction of lowering to about 3v. In the transition period from 5v to 3v, how to match the input / output level with the 5v type LSI that remains in the peripheral LSI during system design becomes a problem. For example, 0 obtained by the 3v system circuit
In the case where a signal having a narrow logical amplitude in the range of 3v is processed by a 5v system circuit, an input signal having a narrow logical amplitude of 3v is set to 5
A signal voltage level conversion circuit for converting an output signal into a v-system wide logical amplitude (range of 0 to 5v) is required. As this signal voltage level conversion circuit, a low power consumption type flip-flop type circuit configuration as shown in FIG. 8 can be considered. The signal voltage level conversion circuit shown in FIG. 8 includes a P-channel MOS transistor 801 and an N-channel MOS transistor 801 which generate an inversion signal VIN (bar) having a narrow logic amplitude of 0 to 3v by an input signal VIN having a narrow logic amplitude of 0 to 3v. A CMOS inverter circuit configured by 802, a first MOS transistor 803 whose switching is controlled by an input signal VIN, and a first MOS transistor 803 which is switching controlled by an inversion signal VIN (bar) are opened and closed exclusively. Second MOS transistor 805 and the second M
It is connected to the OS transistor 805 in series and the first MO
Third closed control by closing the S-transistor 803
And a fourth MOS transistor 804 which is in series with the first MOS transistor 803 and which is closed and controlled by closing the second MOS transistor 805.

The circuit operation of this signal voltage level conversion circuit will be described in detail with reference to FIG. When the input signal VIN shown in FIG. 9 becomes a high level of 3v, the first MOS transistor 803 is closed and the inverted signal VIN
(Bar) is the low level of 0v, so the second MOS
The transistor 805 is in an open state. By closing the first MOS transistor 803,
A potential of 0v is applied to the gate electrode of the MOS transistor 806 of FIG. 3 and the third MOS transistor 806 is closed, and the output signal OUT2 is maintained at the high level of 5v. When the output signal OUT2 is at the high level, the fourth MOS transistor 804 is in the open state, and the output signal OUT1 is maintained at the low level of 0v. Thus, when the 3v system input signal VIN is at a high level (3v), the 5v system output signal OUT1 is at a low level (0v) and OUT2 is at a high level (5v). On the other hand, the input signal V
When IN becomes a low level of 0v, the first MOS transistor 803 is in an open state, and the inversion signal VIN (bar) becomes a high level. Therefore, the second MOS transistor 80
5 is in a closed state. This second MOS transistor 8
When 05 is closed, a potential of 0 V is applied to the gate electrode of the fourth MOS transistor 804, so that the fourth MOS transistor 804 is closed and the third MOS transistor 806 is opened. It becomes a state. As a result, the output signal OUT1 is at high level (5v).
And OUT2 is maintained at a low level (0v). To output this output signal with the same logic as the internal signal VIN, take out the output signal from OUT2 and output the output signal with inverted logic with respect to the internal signal VIN,
An output signal will be taken out from OUT1.

Next, an example of actual use of the signal voltage level conversion circuit will be described with reference to FIG. FIG. 10 shows a process of converting a 3v system signal processed in the semiconductor integrated device into a 5v system signal and outputting the 5v system signal to an external semiconductor integrated device by using an output driver circuit. Input signal IN_
P and IN_N are a P-channel type MOS transistor 1007 and an N-channel type M which form an output driver circuit.
In order to control each OS transistor 1008 independently,
This is a 3v system input signal controlled by an internal circuit. The IN_P and IN_N are converted to the signal voltage level conversion circuit 10
After being converted to a 5v system signal by 01 and 1003, the signal is amplified by the buffer circuits 1005 and 1006, and the P-channel type MOS transistor 1007 and the N-channel type MOS transistor 1008 of the output driver circuit are controlled to output from the PAD which is the output terminal. It is also output to an external semiconductor integrated device. The output driver circuit may be directly controlled without amplifying the signal by the buffer circuits 1005 and 1006.

[0005]

However, in the semiconductor integrated device using the deep submicron process or the semiconductor integrated device aiming at ultra-low power consumption, the internal signal is changed from 3v system to 2v system or 1v system. As the voltage is further reduced, the delay time of the MOS transistor is significantly increased due to the lower voltage. As measures against this, there are means such as forming a thin gate oxide film to improve the driving capability of the MOS transistor, but changing the gate oxide film is equivalent to developing a completely new MOS transistor, and a new process for low voltage is used. Development results in increased development time and increased costs. Further, the increase in the delay time of the internal circuit can be redesigned by increasing the channel length of the MOS transistor, but input / output signals are handled between the outside of the semiconductor integrated device and the logic circuit formed in the internal region. The peripheral area has a limited layout area of input and output cells due to the increase in the number of pins of the semiconductor integrated device.
Therefore, there is no degree of freedom in design changes such as increasing the channel length of the MOS transistor as in the internal region.

Therefore, the present invention is to solve the above-mentioned problems, and the problem is to use a 3v system miniaturization process and only change the wiring such as aluminum wiring, and a low power supply of 2v system or 1v system. It is an object of the present invention to provide a signal voltage level conversion circuit capable of converting a narrow logic amplitude signal due to a voltage into a wide logic amplitude signal having a high power supply voltage at a high speed and with the same power consumption as the conventional one.

[0007]

A semiconductor integrated device of the present invention is a first MO that is switching-controlled by an input signal.
The S-transistor and the second MOS transistor that is switching-controlled by the inverted signal of the S-transistor are opened and closed exclusively with the first MOS transistor, and the second MOS transistor is connected in series to the second MOS transistor. A third MOS transistor that is controlled to be closed and a second MO transistor that is in series with the first MOS transistor
Fourth MO controlled to be closed by closing the S-transistor
In a signal voltage level conversion circuit having an S transistor, the first conductivity type MOS transistor of each inverting logic circuit composed of first and second conductivity type MOS transistors for controlling switching of the first and second MOS transistors is grounded. A first power supply voltage higher than the power supply voltage level is applied to the well which is the back gate electrode of the first conductivity type MOS transistor, and is higher than the ground power supply voltage level and higher than the first power supply voltage level. It is characterized in that a high second power supply voltage is applied to the source electrode of the first conductivity type MOS transistor.

Further, in the peripheral region and the inner peripheral region, or a part of the internal region, to which the second power supply voltage higher than the ground power supply voltage level and higher than the first power supply voltage level is applied, A gate oxide film thicker than the gate oxide film formed in the center of the internal region is formed, and the signal voltage level conversion circuit or the first and second M
Each inversion logic circuit including first and second conductivity type MOS transistors for switching control of the OS transistor has a peripheral region having a gate oxide film thicker than the gate oxide film formed in the central portion of the internal region, or an outer peripheral portion of the internal region. ,
Alternatively, it is characterized in that it is formed in a part of the internal area.

[0009]

Embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a signal voltage level conversion circuit of the present invention. The first MOS transistor 105 switching-controlled by an input signal and the first MOS transistor 105 switching-controlled by an inverted signal thereof are opened and closed exclusively. 2 MOS transistor 107,
A third MOS transistor 108 that is in series with the second MOS transistor 107 and that is closed and controlled by closing the first MOS transistor 105;
A fourth M connected in series with the transistor 105 and controlled to be closed by closing the second MOS transistor 107.
It is composed of the OS transistor 106. In a CMOS inverter circuit composed of a P-channel type MOS transistor 101 and an N-channel type MOS transistor 102 for controlling switching of the first MOS transistor 105 of this signal voltage level conversion circuit, the P-channel type MOS transistor 101 is a ground power supply voltage. Level V
The first power supply voltage VDD1 higher than SS is applied to the well that is the back gate electrode, and is higher than the ground power supply voltage level VSS and the first power supply voltage level V
A second power supply voltage VDD2 higher than DD1 is applied to the source electrode. In addition, the first MOS transistor 105
And a second MOS transistor 107 that is opened and closed exclusively with
In the CMOS inverter circuit including the P-channel type MOS transistor 103 and the N-channel type MOS transistor 104 for switching control of the P-channel type MOS transistor 103, the P-channel type MOS transistor 103 has the first power supply voltage higher than the ground power supply voltage level VSS. The circuit configuration is such that VDD1 is applied to the well that is the back gate electrode, and the second power supply voltage VDD2, which is higher than the ground power supply voltage level VSS and higher than the first power supply voltage level VDD1, is applied to the source electrode. ing.

With respect to the circuit operation of the signal voltage level conversion circuit of the present invention, a process of level-converting an internal signal of 3v system to 5v system will be described in detail with reference to FIGS. 2 and 3. When the internal signal of 0v is received by the CMOS inverter circuit composed of the P-channel type MOS transistor 101 and the N-channel type MOS transistor 102, VIN which is an inverted signal of the internal signal is 3v + α (about 4v).
Is at a high level. The level of VIN increases to 3v + α (about 4v) because the P-channel MO shown in FIG.
As shown in the gate voltage (VGS) vs. drain-source current (log IDS: logarithmic display) of the S transistor, if a voltage higher than the potential (well) of the back gate electrode is applied to the source electrode, the drain of the MOS transistor is drained due to the substrate bias effect. The leak current between the sources increases, and the operation is similar to that of a diode formed from a P + impurity diffusion layer that is a drain electrode and an N + impurity diffusion layer that is a back gate electrode (well). Therefore, the P-channel type MO
The high-level output of the CMOS inverter circuit composed of the S-transistor 101 and the N-channel type MOS transistor 102 is higher than VDD2 applied to the source electrode of the P-channel type MOS transistor 101 by the P + impurity diffusion layer which is the drain electrode. VDD2-VTH (3v + α) lower than the threshold voltage of the diode formed from the N + impurity diffusion layer that is the back gate electrode (well)
Becomes This 3v + α is input to the first MOS transistor 105 forming the signal voltage level conversion circuit, and the closed state is established. Further, since the inverted signal VIN (bar) is at a low level of 0v, the second MOS transistor 107 is in the open state. When the first MOS transistor 105 is in the closed state, the potential of 0 V is applied to the gate electrode of the third MOS transistor 108, so that the third MOS transistor 108 is in the closed state and the output signal OUT2 is 5
maintained at a high level of v. When the output signal OUT2 is at the high level, the fourth MOS transistor 106 is in the open state, and the output signal OUT1 is maintained at the low level of 0v. Thus, when the 3v system input signal VIN is at the high level (3v), the 5v system output signal OUT1 is converted to the low level (0v) and OUT2 is converted to the high level (5v).

On the other hand, the 0v internal signal is transmitted to the P channel type MO.
VIN, which is the inversion signal of the internal signal when received by the CMOS inverter circuit composed of the S transistor 101 and the N-channel type MOS transistor 102, is 0v.
Is at a low level. When the input signal VIN has a low level of 0v, the first MOS transistor 105 is in an open state, and the inverted signal VIN (bar) has a high level of 3v + α. The level of VIN (bar) rises to 3v + α (about 4v) is due to the P-channel MOS transistor 1 described above.
01 and N-channel type MOS transistor 102, which is similar to the CMOS inverter circuit shown in FIG.
As shown in (a), the substrate bias effect increases the leak current between the drain and source of the MOS transistor, and the P + impurity diffusion layer that is the drain region and the N + impurity diffusion layer that is the back gate electrode (well) are formed. Since the operation is similar to that of a diode, the P-channel MOS transistor 103 and the N-channel MOS transistor 1
The high level output of the CMOS inverter circuit composed of 04 is higher than VDD2 applied to the source electrode of the P-channel type MOS transistor 103, and P + impurity diffusion layer which is a drain region and N + which is a back gate electrode (well). VDD2-VTH (3v + α) is lower than the threshold voltage of the diode formed from the impurity diffusion layer. This 3v + α is input to the second MOS transistor 107 to enter the closed state. When the second MOS transistor 107 is closed, the fourth MOS transistor 1
Since the potential of 0 V is applied to the gate electrode of 06, the fourth MOS transistor 106 is closed and the third MOS transistor 106 is closed.
The MOS transistor 108 is opened. As a result, when the 3v system input signal VIN is at a low level (0v), the 5v system output signal OUT1 is converted to a high level (5v) and the OUT2 is converted to a low level (0v). If you want to output this output signal with the same logic as VIN,
Take the output signal from UT2. Also, the output signal is VIN
On the other hand, when it is desired to output in the inverted logic, the output signal is extracted from OUT1.

Next, regarding the circuit operation of the signal voltage level conversion circuit of the present invention, for example, an internal signal of 1 to 2v system is converted to 3v.
System, or delay time when converting to 5v system,
The power consumption will be described with reference to FIGS. FIG. 4 (a) shows the delay time until the level conversion of the internal signal of the 1 to 2v system to the 3v system, where x indicates the conventional circuit and o indicates the signal voltage level conversion circuit of the present invention. is there. When the internal signal 2.2v is converted to 3v, the level can be converted about 20% faster than the conventional signal voltage level conversion circuit, and when the internal signal 1.8v is converted to 3v, the level can be converted about 40% faster. And the internal signal 0.9v is 3v
In the case of converting to, the follow-up operation becomes impossible in the conventional circuit. Further, the power consumption is equivalent to that of the conventional signal voltage level conversion circuit as shown in FIG. 5A, and each inversion for controlling the switching of the first and second MOS transistors of the signal voltage level conversion circuit. By improving the drive capability of the P-channel MOS transistor in the logic circuit, the level of internal signals of the 1 to 2v system can be converted at high speed. Also, as shown in FIGS. 4 (b) and 5 (b),
The same applies to level conversion of an internal signal of 1 to 3v system to 5v system.

FIG. 6 shows a process cross section of the P-channel MOS transistor of each inverting logic circuit which controls switching of the first and second MOS transistors of the signal voltage level conversion circuit according to the present invention. FIG. 6A shows each inversion logic circuit that controls switching of the first and second MOS transistors of the signal voltage level conversion circuit, and the process of the P-channel MOS transistors 601 and 603 of this inversion logic circuit. A cross-sectional view is shown in FIG. P-channel MOS transistor 60
The wells 609 which are the back gate electrodes of Nos. 1 and 603 are common, and the back gate electrode extraction portions 611 and 615 are provided.
A first power supply voltage higher than the ground power supply voltage level is applied to the drain electrodes 612 and 614,
A second power supply voltage higher than the ground power supply voltage level and higher than the first power supply voltage level is applied by aluminum wiring or the like. Therefore, since the first power supply voltage applied to the well is the same as that of the internal region, it can be formed in the well common to the internal region, but the gate oxide film of the MOS transistor to which the second power supply voltage is applied is It is necessary to form the gate oxide film thicker than the MOS transistor in the internal region so as to withstand the second power supply voltage.

FIG. 7 shows a region in which the gate oxide film is formed thicker than the MOS transistor in the internal region so as to withstand the second power supply voltage. FIG. 7 shows a peripheral region of the semiconductor integrated device and a part of the outer peripheral portion of the internal region.
Pad electrodes PAD1, PAD2, PAD3, regions I and II forming P-channel and N-channel output drivers, and peripheral regions including regions III and IV forming signal voltage level conversion circuits or input / output control circuits, Region V where internal MOS transistor is formed
It is divided into an internal area consisting of. The regions to which the second power supply voltage is applied are regions I and II forming P-channel and N-channel output drivers, and region II forming a signal voltage level conversion circuit or an input / output control circuit.
This is a range I consisting of I and region IV, and it is necessary to form a gate oxide film that is thicker than at least the internal region V in this region. In addition, by forming a thick gate oxide film up to the range II including a part of the internal region, the regions III and IV can be formed.
Is eliminated and a signal voltage level conversion circuit or an input / output control circuit is formed in the region V, the area of the semiconductor integrated device can be reduced. This is because the signal voltage level conversion circuit of the present invention can configure the circuit only by changing the wiring such as aluminum wiring, so that the gate oxide film can be formed anywhere as long as it can withstand the second power supply voltage. The signal voltage level conversion circuit of the invention can be constructed.

[0015]

According to the effects of the invention described above, 2v
Since it is not necessary to newly develop a new process for low voltage of 1V system or 1V system, it is possible to prevent an increase in development time and cost and to use, for example, a 3V system miniaturization process and aluminum wiring. 2v only by changing the wiring
There is an effect that a narrow logic amplitude signal of a low power supply voltage of a system or a 1v system can be converted into a wide logic amplitude signal of a high power supply voltage at high speed and with the same power consumption as the conventional one.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a signal voltage level conversion circuit according to the present invention.

FIG. 2 is an operation waveform diagram of the signal voltage level conversion circuit according to the present invention.

FIG. 3 is a characteristic diagram of gate-source voltage vs. drain-source current (logarithm) of a MOS transistor for explaining the operation of the signal voltage level conversion circuit of the present invention.

FIG. 4 is a characteristic diagram comparing the delay times of the signal voltage level conversion circuit of the present invention and the conventional signal voltage level conversion circuit.

FIG. 5 is a characteristic diagram comparing the power consumptions of the signal voltage level conversion circuit of the present invention and the conventional signal voltage level conversion circuit.

FIG. 6 is a process sectional view of a signal voltage level conversion circuit of the present invention.

FIG. 7 is a layout diagram of a signal voltage level conversion circuit of the present invention.

FIG. 8 is a circuit diagram of a conventional signal voltage level conversion circuit.

FIG. 9 is an operation waveform diagram of a conventional signal voltage level conversion circuit.

FIG. 10 is a diagram showing an example of actual use of a conventional signal voltage level conversion circuit.

[Explanation of symbols]

101, 103, 106, 108, 601, 603, 8
01, 804, 806, 1007 ...
-P-channel type MOS transistors 102, 104, 105, 107, 602, 604, 8
02, 803, 805, 1008 ...
-N-channel type MOS transistors 401, 402, 403, 404, 405, 406, 4
07, 408, 409, 410, 411, 412, 41
3, 414 ... Delay time 501, 502, 503, 504, 505, 506, 5
07, 508, 509, 510, 511, 512, 51
3, 514 ... Power consumption 605, 606 ... Gate electrode 613 ... Source electrode 612, 614 ... Drain electrode 611, 615, 702 ... Back gate electrode extraction part 607, 608 ... Element Separation 609 ... Well 610 ... Substrate 701 ... Source / drain region 1001, 1003 ... Signal voltage level conversion circuit 1002, 1004 ... Inversion logic circuit 1005, 1006 ... Buffer circuit internal signal, VIN, VIN (bar), IN_P, IN_
N ... Input signal OUT1, OUT2 ... Output signal VDD1 ... First power supply voltage VDD2 ... Second power supply voltage VSS ... Ground power supply voltage P0, P1, P2, P3 ... PTr Threshold voltage N0, N1, N2, N3 ... NTr threshold voltage PAD, PAD1, PAD2, PAD3 ... Output terminal range I, range II, region I, region II, region III, region IV
・ ・ ・ Peripheral area Area V ・ ・ ・ Internal area

Claims (3)

[Claims] 1. A first MOS transistor switching-controlled by an input signal, a second MOS transistor switching-controlled by an inversion signal thereof and opening / closing exclusively with the first MOS transistor, and a second MOS transistor. A third MOS transistor that is in series with the first MOS transistor and is controlled to be closed by closing the first MOS transistor, and a third MOS transistor that is in series with the first MOS transistor and is closed by closing the second MOS transistor. In the signal voltage level conversion circuit having a fourth MOS transistor, the first conductivity type of each inverting logic circuit composed of first and second conductivity type MOS transistors for switching control of the first and second MOS transistors. The MOS transistor has a first conductive voltage that is higher than the ground power supply voltage level. Applied to the well which is the back gate electrode of the MOS transistor of the first conductivity type, and supplies to the source electrode of the MOS transistor of the first conductivity type a second power supply voltage higher than the ground power supply voltage level and higher than the first power supply voltage level. A semiconductor integrated device characterized by being applied. 2. An internal region mainly formed in a central portion of the semiconductor integrated device for forming a predetermined logic circuit, and formed around the internal region outside the semiconductor integrated device and in the internal region. In a semiconductor integrated device having an input cell handling an input / output signal with a logic circuit, or a peripheral region including an output cell, the peripheral region and the outer peripheral portion of the internal region, or a part of the internal region, the center of the internal region. A semiconductor integrated device characterized by forming a gate oxide film thicker than the gate oxide film formed in the portion. 3. The signal voltage level conversion circuit according to claim 1, or each inverting logic circuit including first and second conductivity type MOS transistors for switching control of the first and second MOS transistors. A semiconductor integrated device characterized in that it is formed in a peripheral region having a gate oxide film thicker than the gate oxide film formed in the central part of the internal region, in the outer peripheral part of the internal region, or in a part of the internal region.