JPH09148331A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: To improve the production efficiency of a bump base metal and a bump forming process, reduce the manufacturing cost, and suppress the cost increase due to the investment of new equipment. An intermediate layer 3 made of tungsten is formed on an upper layer of a wiring 2 formed on a main surface of a semiconductor substrate 1 to form a first metal layer 6 made of nickel and a second metal layer 7 made of gold. The bump base metal composed of is stably formed by electroless plating. In addition, a wafer inspection is performed before the formation of the bump underlying metal, the wafer is diced and divided, and then the process proceeds to the next step of forming the bump underlying metal only on the semiconductor substrate 1 determined to be a good product by the inspection, and the defective product The determined semiconductor chip is not processed in the next step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor integrated circuit device in which a semiconductor chip is mounted on a wiring board by bump electrodes (bumps). It is a thing.

[0002]

2. Description of the Related Art In a connection method such as a flip chip method or a tape carrier method, a protruding electrode is used for electrically connecting a semiconductor chip to a wiring board such as a ceramic substrate or a resin substrate.

The mounting of the semiconductor chip having the protruding electrodes is known as CCB (Controlled Collapse Bonding) mounting and TAB (Tape Automated Bonding) mounting.

The protruding electrode is generally formed by a bump made of PbSn alloy or the like, and is generally arranged with a bump underlying metal (BLM) interposed therebetween. A multi-layer metal film is used for the bump base metal, and Cr / Cu / Au, Cr / Ni / Au, Ti / C are used.
Combinations of U / Au, Ti / Ni / Au, etc. are known. The bump underlying metal is formed by a thin film forming method such as a sputtering method and then etched using a patterned photoresist as a mask, and the bump is formed by vapor deposition using the patterned resist as a mask or a metal mask. It is generally done.

As an example of the literature describing the bump and the metal underlying the bump, published by the Industrial Research Committee on January 15, 1980, "IC mounting technology" p175 and p84.
Or, issued by Ohmsha Co., Ltd. on November 30, 1984,
There are "LSI Handbooks" p409 to p410.

In order to realize the formation of the bump electrodes at a low cost, a technique of forming the bump base metal by electroless plating after zincating the wiring in the region where it is to be formed, 1995 Flip Chip, BGA, TAB & AP Symposiu
m, pp16 ~ 21, “Low cost bumping process for flip
chip ”.

[0007]

In the case of the prior art,
Since the bump base metal and the bumps are formed on the premise of a photo process, they are processed on a wafer-by-wafer basis as in the previous step of the semiconductor process. Therefore, even if there is a defective portion in the wafer, it is necessary to perform the processing at the same time without separating the defective portion from the non-defective portion. That is,
The bump base metal and bump forming process must be continuously performed even for defective locations that do not need to continue the subsequent processes, resulting in wasted material costs and manufacturing costs, which increases manufacturing costs. It becomes a factor.

Further, the bump base metal by the electroless plating method for the purpose of lowering the cost, the aluminum wiring surface of the semiconductor chip on which it is formed is treated with zinc (Alkaline).
It is necessary to zincate, and the process becomes complicated.

Further, on the premise of wafer processing, as the wafer size increases, new equipment for large-diameter wafers is required, resulting in an increase in product cost due to amortization of this equipment investment.

An object of the present invention is to eliminate the processing or processing on the defective metal in the bump base metal and the bump forming process, improve the production efficiency of the process, and reduce the manufacturing cost.

Another object of the present invention is to provide a technique capable of stably realizing an electroless plating method, which is considered to be effective for realizing a low price, without going through a complicated process such as a zinc treatment.
It is to realize simplification and shortening of the process.

Still another object of the present invention is to invest a new equipment by developing a bump base metal and a bump forming process capable of continuously using the conventional equipment regardless of the increase in wafer size. It is to suppress the cost increase due to.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is such that an intermediate layer for forming the bump underlying metal by electroless plating is formed between the bump underlying metal and the wiring formed on the semiconductor substrate. .

By forming such an intermediate layer,
It is possible to stably form the bump base metal by the electroless plating method. The electroless plating method does not require processing on a wafer-by-wafer basis and can be processed even after the wafer has been cut into semiconductor chips.Therefore, it is possible to form bump base metal and bumps only on selected good chips. It will be possible. As a result, it is possible to eliminate wasteful processing on a defective portion in the wafer and contribute to cost reduction.

Since the intermediate layer is formed on the electrode portion of the semiconductor substrate, it is preferably a conductive material, and at least a semiconductive material is necessary. Also,
The intermediate layer needs to be a material capable of favorably depositing a bump underlying metal such as nickel formed in the subsequent step by electroless plating. At the initial stage of deposition in the electroless plating method, it is considered that element substitution type deposition proceeds, so the intermediate layer is composed of an element having a greater ionization tendency than the element forming the bump base metal that is the object to be plated. It is necessary to On the other hand, it exists stably in the atmosphere,
It is also necessary that the material is not easily oxidized. As a material satisfying the above requirements, in the case of a single element material, a material composed of an element (excluding nickel, palladium, and platinum) between groups IVa and VIII in the periodic table is suitable. These elements have a greater ionization tendency than nickel and are relatively stable elements.

In the semiconductor integrated circuit device of the present invention, the intermediate layer formed between the bump underlying metal and the wiring is a thin film made of an element selected from tungsten, molybdenum, chromium or titanium. Is.

By using tungsten, molybdenum, chromium, or titanium as the intermediate layer, the bump base metal can be formed more stably. That is, the material has a greater ionization tendency than a metal under bump such as nickel, and in addition to being a relatively stable material, the surface is cleaned by an appropriate activation treatment,
This is because the surface can be made suitable for plating.

Further, in the semiconductor integrated circuit device of the present invention, the bump base metal is a laminated metal film of two or more layers, and the first metal layer is plated with copper, nickel, cobalt or tin formed by an electroless plating method. The second metal layer is a plating layer made of gold, silver or platinum which is also formed by electroless plating.

In this way, the bump underlying metal is formed into a laminated metal film, and the surface layer (second metal layer) is formed of a noble metal such as gold, silver or platinum to form a bump on the bump underlying metal later. By reflowing, the bump underlying metal remains stable without being altered by oxidation or the like until the bump electrode is formed. As a result, the reliability of reflow can be improved. In addition, by using nickel, cobalt or tin as the first metal layer of the bump underlying metal formed on the intermediate layer of tungsten, molybdenum, chromium or titanium, the first metal layer can be electroless plated. It can be stably formed.

The noble metal which is the second metal layer has a smaller ionization tendency than nickel, cobalt or tin which is the first metal layer, and a stable electroless plating layer is formed on the material forming the first metal layer. Can be formed. Thus, the bump base metal can be formed by the electroless plating method, which is advantageous in productivity, for both the first metal layer and the second metal layer.

Further, in the semiconductor integrated circuit device of the present invention, the intermediate layer formed under the bump underlying metal has an opening portion of the surface protective film opened for connecting the wiring, and the periphery of the opening portion. It is formed on the upper surface of the surface protective film.
That is, the intermediate layer is formed not only on the opening but also on the surface protective film around the opening.

With such a semiconductor integrated circuit device, it becomes possible to easily carry out a device inspection before wafer cutting even when the opening is minute. That is, the wiring dimension is miniaturized as the degree of integration is improved,
The pad portion forming the protruding electrode also tends to be miniaturized. Therefore, in the inspection before the wafer division in which the needle electrode such as the microprobe is brought into contact with the pad portion to perform the measurement, the contact of the needle electrode becomes difficult as the area of the pad portion is reduced. Therefore, the semiconductor integrated circuit device of the present invention is
The above problem is solved by forming the intermediate layer also on the surface protective film around the opening and substantially functioning as an inspection pad. Further, there is also an effect that it is possible to secure a certain area required when the bump base metal and the bump are formed later.

In the semiconductor integrated circuit device of the present invention, the material of the bump formed on the above-mentioned bump base metal is P
b.Sn alloy, Sn.Ag alloy or Au.

By using such a material, the bump base metal and the bump can be melted together in the reflow process to form a bump electrode having excellent adhesion and reliability.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, after the semiconductor integrated circuit element is formed on the semiconductor substrate, the wiring and the bump base electrode connected to this semiconductor integrated circuit element are formed by electroless plating. For forming an intermediate layer for the purpose, then forming a surface protective film, forming a hole at a required location, and forming a bump base metal on the upper layer of the intermediate layer exposed in the hole by electroless plating. Is.

When such a method for manufacturing a semiconductor integrated circuit device is used, the bump underlying metal can be stably formed by electroless plating, and the intermediate layer is formed at the same time as the wiring. It is possible to simplify.

Here, the wiring can be made of aluminum or its alloy, and the intermediate layer can be made of tungsten, molybdenum, chromium or titanium as described above. Both the wiring and the intermediate layer can be patterned by performing film formation on the entire surface of the substrate in a continuous process by a sputtering method to form a laminated film, and then simultaneously etching and patterning using a photoresist.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, after the semiconductor integrated circuit element and the wiring connected thereto are formed on the semiconductor substrate, the surface protection film is formed to form the required openings, After that, an intermediate layer for forming a bump base electrode by electroless plating is formed on the upper surface of the wiring exposed in the opening and the upper surface of the surface protective film around the opening, and the bump is formed on the surface of the intermediate layer. The base metal is formed by electroless plating.

According to such a method of manufacturing a semiconductor integrated circuit device, even if the opening of the surface protective film becomes finer in response to the miniaturization of the wiring due to the improvement of the integration degree, the wiring is electrically connected to the wiring. The required intermediate layer can secure a required area regardless of the area of the opening of the surface protective film.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the formed semiconductor integrated circuit is inspected before the step of forming the bump base metal in the above-mentioned manufacturing method, and the semiconductor substrate is diced. The semiconductor device is characterized in that it is divided into semiconductor chips, and only those semiconductor chips which are judged to be non-defective by the inspection are sorted and passed to the next step.

According to such a method for manufacturing a semiconductor integrated circuit device, only non-defective products are selected and defective products are not processed before the bump base metal and bump forming process, so that the waste of the process is eliminated. It is possible to reduce the manufacturing cost. Further, in the steps after the step of forming the bump base metal, the processing is carried out in units of semiconductor chips, so that it is not necessary to newly introduce an apparatus to be used in response to an increase in the size of the semiconductor substrate, which suppresses the manufacturing cost. It becomes possible.

In the method for manufacturing a semiconductor integrated circuit device of the present invention, bumps are formed by the transfer bump method after forming the bump base electrodes.

In the method of manufacturing a semiconductor integrated circuit device as described above, it is possible to relatively easily deal with the bump forming process for each semiconductor chip by using the transfer bump method, which simplifies the process and reduces the cost. Can contribute.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a partial sectional view showing an example of a protruding electrode which is one of the embodiments of a semiconductor integrated circuit device of the present invention.

A semiconductor integrated circuit element (not shown) is formed on the main surface of the semiconductor substrate 1 in a wafer state, a wiring 2 connected to the semiconductor integrated circuit element, and an intermediate layer 3 on the upper layer of the wiring 2. Has been done.

A surface protective film 4 is formed so as to cover the semiconductor substrate 1, the wiring 2 and the intermediate layer 3, and the wiring 2 and the intermediate layer 3 are electrically connected to the portion of the surface protective film 4 where the protruding electrodes are formed. An opening 5 is provided to secure the physical contact.

A bump base metal is formed on the intermediate layer 3 in the region where the opening 5 is provided. The bump base metal is composed of a first metal layer 6 and a second metal layer 7,
Bumps 8 are formed on the bump base metal.

The semiconductor substrate 1 is made of single crystal silicon.
The wiring 2 is made of aluminum or an alloy containing aluminum as a main component, and a simple substance or compound such as titanium, chromium, tungsten, molybdenum, or titanium nitride may be formed as a barrier layer on the upper or lower layer thereof.

The intermediate layer 3 is provided to form the bump base metal by electroless plating, and examples thereof include tungsten, molybdenum, chromium and titanium.
However, the present invention is not limited to these, as long as the bump base metal can be stably formed. The conditions for the stable formation of the bump base metal are, as already described,
The element constituting the underlying intermediate layer 3 has a higher ionization tendency in the plating solution than the element constituting the bump underlying metal, and the surface of the intermediate layer 3 is hard to be oxidized and stably exists. Or, the surface of the intermediate layer 3 is easily activated. In the present embodiment, as an example, the intermediate layer 3 is made of tungsten.

The surface protection film 4 can be a silicon oxide film formed by the plasma CVD method or the SOG method. The size of the opening 5 is 60 μm □.

The first metal layer 6 of the bump underlying metal is formed by an electroless plating method, and its material is copper, nickel,
Examples thereof include cobalt and tin, but the present invention is not limited to this, and may be any one formed on the intermediate layer 3 by an electroless plating method. In order to form the first metal layer 6 by the electroless plating method, a metal salt and a reducing agent which are dissolved in an appropriate solution, a pH adjusting agent as an auxiliary component, a buffering agent, a complexing agent, an accelerator, and a stabilizer. And improved materials are required. The material is exemplified as one satisfying these requirements. In the present embodiment, nickel is used as the first metal layer 6, and the film thickness can be set to 2 μm, for example.

The second metal layer 7 is also formed by the electroless plating method like the first metal layer 6, and examples of the material thereof include gold, silver and platinum. The metal salt used in the electroless plating method for forming the second metal layer 7 has a small ionization tendency, and the formed metal film is very stable. It can be carried out with stable metal and high reflow reliability.
It also has the effect of improving the wettability of the solder in the reflow process. In this embodiment, gold is used, and the film thickness can be set to 0.1 μm, for example.

The bumps 8 are made of Pb / Sn alloy, Sn / Ag.
Made of alloy or gold. In this embodiment, a Pb.Sn alloy generally used for CCB bumps is used.

After the bumps 8 are melted by reflow, the gold which is the second metal layer 7 of the bump underlying metal is Pb.
A part of nickel, which is the first metal layer 6 of the bump base metal, is melted into the Sn alloy to form a Ni.Sn alloy and bonded to the bump 8.

Next, an example of a specific method of manufacturing the above-mentioned bump electrode will be described with reference to FIGS. The manufacturing process (so-called pre-process) of a semiconductor integrated circuit element such as CMOS formed on the main surface of the semiconductor substrate 1 is a well-known technique, and is therefore omitted. In this embodiment, it is the final stage of the pre-process. The steps after the step of forming the wiring 2 will be mainly described.

First, according to a well-known manufacturing method, a semiconductor integrated circuit element (not shown) is formed on the main surface of the semiconductor substrate 1, and a connection hole for connecting wiring is opened.

After that, a metal film 10 made of, for example, aluminum or an aluminum alloy, which is a wiring material, is formed on the entire surface of the semiconductor substrate 1 by a sputtering method or a vacuum evaporation method, and an intermediate layer, for example, made of tungsten is formed on the metal film 10. The thin film 11 is formed by the sputtering method (FIG. 2).

Next, a resist pattern made of a photoresist (hereinafter simply referred to as a resist) is formed on the thin film 11, the thin film 11 and the metal film 10 are etched by using this resist pattern as a mask, and the wiring 2 and the intermediate layer 3 are formed.
Are formed (FIG. 3). The etching can be performed by dry etching using a fluorine type gas or wet etching using a mixed acid type etchant containing phosphoric acid and nitric acid as main components.

Next, after removing the resist pattern, a surface protective film 4 made of silicon oxide is formed on the entire surface of the semiconductor substrate 1 on which the wiring 2 and the intermediate layer 3 are formed, for example, plasma CVD method, SOG method, or heat treatment. It is formed by the CVD method. After that, a resist pattern having an opening in the upper layer of the intermediate layer 3 is formed, and using this as a mask, an opening 5 is formed in the surface protective film 4 (FIG. 4). The opening 5 is formed by
Although wet etching with an acid-based etchant can be performed, dry etching using a halogen-based gas or the like is preferable in consideration of reduction of damage to the intermediate layer 3.

Next, after removing the resist pattern, a microprobe (not shown) is brought into contact with the intermediate layer 3 exposed by the opening 5 to inspect the semiconductor integrated circuit element. The area determined to be defective as a result of the inspection is appropriately marked so that it can be distinguished from the non-defective portion.

Next, the semiconductor substrate 1 in a wafer state
Is divided into semiconductor chips which are one unit of the semiconductor integrated circuit device. The division is performed by dicing using a dicer. The divided semiconductor chips are sorted according to the presence or absence of the marking, defective products are discarded or recycled, and only good products are passed to the next step.

Next, in order to activate the surface of the intermediate layer 3 of the semiconductor chips selected as non-defective, the semiconductor substrate 1
To wash.

Next, the semiconductor substrate 1 is treated with the first metal layer 6
To form nickel on the upper surface of the intermediate layer 3 exposed in the openings 5. As the plating conditions at this time, for example, the metal salt may be nickel chloride or nickel sulfate or a mixture thereof, and the reducing agent may be sodium phosphite, sodium borohydride or hydrazine. PH adjuster if necessary,
Buffering agents, complexing agents, promoters, stabilizers and modifiers may be added. Further, as an example, the pH value may be 4 to 6, the plating bath temperature may be 80 ° C. to 100 ° C., and the plating time may be about 10 minutes. At this time, the nickel film thickness is 2μ
m.

Next, the semiconductor substrate 1 is immersed in another plating bath for forming the second metal layer 7, and the first metal layer 6 is formed.
The top surface of the is plated with gold (Fig. 5). As the plating conditions at this time, for example, gold chloride or potassium gold cyanide can be used as the metal salt, and tartaric acid, aldehyde, sodium hypophosphite, etc. can be used as the reducing agent, and the pH can be adjusted as necessary.
As in the case of the nickel plating bath, it is possible to add a regulator and the like. Further, as an example, the pH value is 5 to
7.5, the plating bath temperature may be 80 ° C to 100 ° C, and the plating time may be several minutes. The gold film thickness at this time is
It becomes 0.1 μm.

Next, bumps 8 are formed on the upper surface of the second metal layer 7.
And then reflow to melt the bumps 8,
An alloy was formed with a part of the bump base metal composed of the first metal layer 6 and the second metal layer 7 to ensure the adhesion.
Here, the bumps 8 are solders made of Pb.Sn alloy and are formed by the transfer bump method. The transfer bump method is a method in which bumps are arranged in advance on another substrate, mounted on the semiconductor substrate 1 on which a semiconductor integrated circuit element is formed, and solder reflow is performed to transfer the bumps.

By the above manufacturing method, the bump electrode shown in FIG. 1 is almost completed.

According to the semiconductor integrated circuit device and the method of manufacturing the same of the above-described embodiment, the following effects can be obtained.

(1) By forming the intermediate layer 3 in the region where the bump underlying metal is formed, the bump underlying metal can be stably formed by the electroless plating method.

(2) By using tungsten for the intermediate layer 3 and nickel for the first metal layer 6 of the bump underlying metal, the electroless plating method can be carried out more stably.

(3) By using gold as the second metal layer of the bump undercoat metal, the bump undercoat metal can be stably maintained until the reflow process without deteriorating its surface.

(4) The manufacturing process can be simplified by forming the wiring 2 and the intermediate layer 3 as a laminated film and then simultaneously etching and patterning.

(5) Before forming the bump base metal and bumps, a good product and a defective product are selected by an inspection by electrical measurement, and then the substrate in a wafer state is diced and divided, so that the inspection results in a good product. The bump base metal and the bump forming process can be performed only on the semiconductor substrate 1 in the formed chip state. Thereby, the manufacturing cost can be suppressed and the manufacturing time can be shortened. Further, it is not necessary to newly install equipment used in the step of forming the bump base metal and the bump to cope with the increase in the diameter of the semiconductor wafer, and the manufacturing cost can be reduced.

(6) By forming the bumps 8 by the transfer bump method, the bump forming process can be performed relatively easily even in the case where the semiconductor substrate 1 is in the chip state. It becomes possible to do.

(Second Embodiment) In the second embodiment, a case where the intermediate layer 3 is partially formed on the upper surface of the surface protective film 4 beyond the area of the opening 5 will be described.

FIG. 6 is a partial cross-sectional view showing an example of the bump electrode which is one of the embodiments of the semiconductor integrated circuit device of the present invention.

A semiconductor integrated circuit element (not shown) is formed on the main surface of the semiconductor substrate 1, and a wiring 2 connected to the semiconductor integrated circuit element is formed.

A surface protective film 4 is formed so as to cover the semiconductor substrate 1 and the wiring 2, and an electrical contact with the wiring 2 is ensured in a region of a portion of the surface protective film 4 where a protruding electrode is formed. An opening 5 is provided for this purpose.

The intermediate layer 3 is formed on the upper surface of the surface protective film 4 in the region where the opening 5 is provided and the periphery thereof, and the bump underlying metal is formed on the intermediate layer 3. The bump base metal is
The first metal layer 6 and the second metal layer 7 are formed, and the bump 8 is formed on the bump underlying metal.

The material characteristics and physical properties of the semiconductor substrate 1, the wiring 2, the intermediate layer 3, the surface protective film 4, the first metal layer 6, the second metal layer 7 and the bumps 8 are described in the first embodiment. Since it is similar to that of the first embodiment, the description in the second embodiment will be omitted.

Unlike the first embodiment, the size of the opening 5 may be smaller than 60 μm □ in the second embodiment. Embodiment 1
However, since it was necessary to contact a microprobe for electrical measurement with the opening, the above-mentioned 60 μm □ was required as the minimum area where the contact can be reliably made.
However, in the second embodiment, the intermediate layer 3 is formed with the opening 5
Since it is also formed on the upper surface of the surface protective film 4 around, the contact area of the microprobe for the electrical measurement is the opening 5
Even if the area is small, it can be made sufficiently wide. Since the area of the opening 5 can be reduced, it is possible to deal with the miniaturization of the wiring 2 associated with the improvement in the degree of integration, and the degree of freedom in layout can be increased.

Next, an example of a specific method for manufacturing the protruding electrode of the second embodiment will be described with reference to FIGS. The description of the same items as in the first embodiment will be omitted, and the description will focus on the features that are characteristic of the second embodiment.

A metal film made of, for example, aluminum or an aluminum alloy for forming wiring on the semiconductor substrate 1 in a wafer state on which the semiconductor integrated circuit element is formed is formed by the sputtering method or the vacuum evaporation method, and the upper layer of this metal film is formed. Then, a mask made of resist is formed and the metal film is etched to form the wiring 2 (FIG. 7). Etching and the like are the same as those in the first embodiment.

Next, after removing the resist pattern, a surface protective film 4 made of silicon oxide is formed on the entire surface of the semiconductor substrate 1 on which the wiring 2 is formed, and a resist pattern in which an upper layer of the wiring 2 is opened is formed. Then, using this as a mask, an opening 5 is formed in the surface protective film 4 (FIG. 8). The method of forming the surface protective film 4, the method of forming the openings 5, etc. are the same as those in the first embodiment.

Next, a tungsten film is formed on the entire surface of the semiconductor substrate 1 on which the surface protective film 4 is formed by a sputtering method, a resist mask is formed, and the tungsten film is etched to form an intermediate layer 3. (FIG. 9).

Next, after removing the resist pattern, a microprobe (not shown) is brought into contact with the intermediate layer 3 to inspect the semiconductor integrated circuit device. The area determined to be defective as a result of the inspection is appropriately marked so that it can be distinguished from the non-defective portion.

Next, the semiconductor substrate 1 in a wafer state
Is divided into semiconductor chips which are one unit of the semiconductor integrated circuit device. The division is performed by dicing using a dicer. The divided semiconductor chips are sorted according to the presence or absence of the marking, defective products are discarded or recycled, and only good products are passed to the next step.

Next, in order to activate the surface of the intermediate layer 3 of the semiconductor chips that have been selected as good products, the semiconductor substrate 1
To wash.

Next, the semiconductor substrate 1 is processed by a method similar to the plating method described in the first embodiment to form the first metal layer 6 and the second metal layer 7 on the intermediate layer 3. (FIG. 10).

Next, the bumps 8 are formed on the upper surface of the second metal layer 7 by the same method as in the first embodiment, and then the reflow is performed to melt the bumps 8 and the first metal layer 6 and An alloy is formed with a part of the bump base metal formed of the second metal layer 7. As a result, the bump 8 surely adheres to the bump underlying metal, and the bump electrode shown in FIG. 6 is almost completed.

According to the semiconductor integrated circuit device and the method of manufacturing the same of the above-described embodiment, the following effects can be obtained in addition to the effects described in the first embodiment.

(1) By forming the intermediate layer 3 on the upper surface of the opening 5 and the surface protective film 4 around the opening 5, the area of the opening 5 is ensured while ensuring the area required for contact of the microprobe during electrical measurement. It is possible to reduce the area. This allows
It becomes possible to deal with the miniaturization accompanying the improvement of integration,
Also, the degree of freedom of layout can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, the bump 8
Although the description has been given of the case where the semiconductor substrate 1 is formed on the semiconductor substrate 1 side by the transfer bump method, the semiconductor substrate 1 side may have only electrodes composed of bump underlying metal and the bumps may be formed on the package substrate side. Absent. The semiconductor substrate 1 and the package substrate are then CCB-connected by a reflow process, and the essence of the present invention is not affected by which substrate the bumps are formed on.

Further, in the above-mentioned embodiment, the case where the wiring 2 is made of aluminum or its alloy has been described, but the wiring 2 is not limited to these materials, but is a conductor such as copper or a semiconductor such as silicon. May be. Further, for example, the wiring may have a laminated structure in which a barrier layer of tungsten, molybdenum, chromium, or the like is laminated on the upper layer and / or the lower layer of the wiring 2.

[0088]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) It is possible to stably form the bump base metal by the electroless plating method and keep the surface stable without degrading the surface.

(2) The manufacturing process can be simplified, wasteful processing can be rationalized, new equipment investment can be suppressed, and the manufacturing cost can be suppressed and the manufacturing time can be shortened.

(3) It is possible to deal with the miniaturization of the wiring dimension due to the improvement in the degree of integration, and it is possible to increase the degree of freedom in design layout.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing an example of a protruding electrode which is one of embodiments of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a partial cross-sectional view showing an example of a process of manufacturing a bump electrode which is one of the embodiments of the semiconductor integrated circuit device of the present invention.

FIG. 3 is a partial cross-sectional view showing an example of a process of manufacturing a bump electrode which is one of the embodiments of the semiconductor integrated circuit device of the present invention.

FIG. 4 is a partial cross-sectional view showing an example of a process of manufacturing a bump electrode which is one of the embodiments of the semiconductor integrated circuit device of the present invention.

FIG. 5 is a partial cross-sectional view showing an example of a process of manufacturing a bump electrode which is one of the embodiments of the semiconductor integrated circuit device of the present invention.

FIG. 6 is a partial cross-sectional view showing an example of a protruding electrode which is another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 7 is a partial cross-sectional view showing an example of a process of manufacturing a bump electrode which is another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 8 is a partial cross-sectional view showing an example of a process for manufacturing a bump electrode which is another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 9 is a partial cross-sectional view showing an example of a process for manufacturing a bump electrode which is another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 10 is a partial cross-sectional view showing an example of a process of manufacturing a bump electrode which is another embodiment of the semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Wiring 3 Intermediate Layer 4 Surface Protective Film 5 Opening 6 First Metal Layer 7 Second Metal Layer 8 Bump 10 Metal Film 11 Thin Film

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/92 603D 604M

Claims (9)

[Claims] 1. A semiconductor substrate having a semiconductor integrated circuit element on its main surface, a wiring formed on the main surface of the semiconductor substrate and connected to the semiconductor integrated circuit element, the semiconductor substrate and the wiring. A surface protective film formed in contact with, an opening portion of the surface protective film formed by opening the surface protective film on the wiring, and formed in the opening portion, or formed to cover the opening portion. A semiconductor integrated circuit device including a bump underlying metal, wherein an intermediate layer for forming the bump underlying metal by electroless plating is formed on a lower surface of the bump underlying metal. . 2. The semiconductor integrated circuit device according to claim 1, wherein the intermediate layer is a thin film made of an element selected from tungsten, molybdenum, chromium, or titanium. apparatus. 3. The semiconductor integrated circuit device according to claim 1, wherein the bump base metal is a first metal layer made of copper, nickel, cobalt or tin formed by an electroless plating method, A semiconductor integrated circuit device comprising a laminated metal film including a second metal layer made of gold, silver or platinum. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the intermediate layer is formed on the upper surface of the surface protection film around the opening and the opening. A semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, 2, 3, or 4, wherein a Pb.Sn alloy, Sn.A is provided on the bump base metal.
A semiconductor integrated circuit device, wherein bumps made of g-alloy or Au are formed. 6. A method for manufacturing a semiconductor integrated circuit device, wherein a semiconductor substrate having a semiconductor integrated circuit element provided on its main surface is connected to a wiring board by using bump electrodes, comprising: (a) the semiconductor substrate Forming a semiconductor integrated circuit element, (b) forming a wiring connected to the semiconductor integrated circuit element, and forming an intermediate layer on the wiring for forming a bump base electrode by electroless plating, (c) Forming a surface protective film on the upper surfaces of the semiconductor substrate and the intermediate layer, and then forming an opening in the surface protective film for connecting the wiring to the outside through the intermediate layer, (d) the opening And a step of forming a bump base electrode on the surface of the intermediate layer in which the holes are formed by using an electroless plating method. 7. A method of manufacturing a semiconductor integrated circuit device, wherein a semiconductor substrate having a semiconductor integrated circuit element provided on its main surface is connected to a wiring substrate using bump electrodes, comprising: (a) the semiconductor substrate A step of forming a semiconductor integrated circuit element and a wiring connected to the semiconductor integrated circuit element; (b) forming a surface protective film on the upper surfaces of the semiconductor substrate and the wiring board, and thereafter connecting the wiring to the outside. Forming a hole in the surface protective film; (c) intermediate for forming a bump underlayer electrode by electroless plating in the hole portion where the hole is formed or in the region including the hole portion and its periphery. A method of manufacturing a semiconductor integrated circuit device, comprising: a step of forming a layer; and (d) a step of forming a bump base electrode on the surface of the intermediate layer by using an electroless plating method. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein (e) the semiconductor integrated circuit formed on the semiconductor substrate before the step (d) of forming the bump base metal. After the circuit is inspected, the semiconductor substrate is divided into semiconductor chips by dicing, and the semiconductor chips judged to be non-defective by the inspection are selected, and the semiconductor chips selected as non-defective by the inspection. Only in the subsequent step (d) the step of forming the bump underlayer metal and subsequent steps. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 6, 7 or 8, wherein after the step (d) of forming the bump base electrode, the bump formed on the bump forming substrate is A method of manufacturing a semiconductor integrated circuit device, comprising: a bump electrode forming step of forming a bump electrode by performing reflow after transferring onto a bump base metal.