JPH09152921A - Active insertion unit - Google Patents

Abstract

(57) An object of the present invention is to reduce the noise generated during active replacement of a unit using an element whose open-circuit voltage is 0 V or close to a power supply voltage to a certain level or less with a small circuit amount and low cost. The challenge is to suppress it. SOLUTION: In an active insertion unit, which has a connector 6 connected to a mother board 1, and the connector 6 is connected in order of a ground, a power supply, and a signal line at the time of insertion, the signal line is grounded at the time of the active insertion of the connector 6. And a potential determination circuit 5a for providing an intermediate potential between the power supply voltage and the power supply voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active insertion unit capable of exchanging units during system operation in a highly reliable system having a redundant configuration such as an information processing device.

[0002]

2. Description of the Related Art A conventional high-reliability system having a redundant configuration uses an element which operates at 5 V (volt), and an open circuit voltage is a threshold voltage level. State is low (“L”), high (“H”)
In any of the states, since the voltage fluctuation level due to the insertion of the unit has a margin with respect to the threshold, the malfunction due to the waveform crack or the like does not occur at the time of the active insertion of the unit.

However, recent bus interface devices are high-speed and have an amplitude of 3.3V level, so that the noise margin for the threshold is small. Moreover, since the open circuit voltage is "L" or "H" instead of the intermediate level, noise is generated in the signal line on the bus side at the timing when the signal line comes into contact during active insertion of the unit, and the system is It sometimes malfunctioned.

A conventional example will be described below with reference to the drawings.
FIG. 5 is an explanatory view (1) of the conventional example, and FIG. 6 is an explanatory view (2) of the conventional example. 1): Description when using an element that operates at 5V In FIG. 5, FIG. 5A is a description when using an element that operates at 5V, and a bus signal on the motherboard side to which a plurality of units are connected. The line and the signal line Sig of the transceiver 3 on the active insertion unit side are connected by a connector during system operation on the motherboard side.

The connector is provided with connecting pins, and when the pins contact each other, the point A on the bus signal line side and the point B on the signal line Sig on the transceiver 3 side are connected. The transceiver 3 is provided with a capacitor 4, AND circuits 11, 12, an output element 13, and an input element 14. It should be noted that the ∘ marks of the AND circuits 11 and 12, the output element 13, and the input element 14 indicate that they are active low (operate when "L"). Further, the capacitance 4 includes the wiring capacitance and the input capacitance.

(A) Description of Transceiver Operation The transceiver 3 operates when the enable signal EN is "L",
The outputs of the AND circuits 11 and 12 are both "H", and the output element 13 and the input element 14 are both off. As a result, the signal line Sig (point B) becomes high impedance. This high impedance signal line Sig
(Point B) is a threshold level (about 1.5) due to the output element 13 and the input element 14 when the bus signal line is opened.
V).

When the enable signal EN is "H" and the direction signal (direction signal) Dir is "H", the output of the AND circuit 11 becomes "L" and the output element 13 operates.
The signal from the signal line Sig on the transceiver 3 side is output to the bus signal line. Further, when the enable signal EN is “H” and the direction signal (direction signal) Dir is “L”, the output of the AND circuit 12 becomes “L” and the input element 14
Is operated and the signal from the bus signal line is received by the signal line Sig on the transceiver 3 side.

(B) Description at the time of active insertion FIG. 5 (b) is a description of noise on the bus when the pins make contact when point A is at the "H" level (5 V), and point A on the bus signal line side. Since the signal line Sig at the point B is at the threshold level (about 1.5 V) before the pin of the signal line Sig at the point B contacts, when the potential at the point A is 5 V (“H”), Even if the pin touched and insertion noise occurred, it did not fall below the threshold level.

In FIG. 5 (c), point A is at "L" level (0V).
This is an explanation of the noise on the bus when the pins make contact, and before the point A on the bus signal line side and the pin B of the signal line Sig make contact, the signal line Sig of the point B is at the threshold level ( Since it is about 1.5V), the potential at point A is 0V
At the time of (“L”), even if the pin came into contact and insertion noise occurred, it did not exceed the threshold level.

2): Description of the case where an element operating at 3.3V is used. In FIG. 6, FIG. 6A shows the case where an element operating at 3.3V is used, and the circuit configuration is shown in FIG. It is similar to that of (a).

(A) Description of Transceiver Operation The transceiver 3 operates when the enable signal EN is "L",
The outputs of the AND circuits 11 and 12 are both "H", and the output element 13 and the input element 14 are both off. As a result, the signal line Sig (point B) becomes high impedance. This high impedance signal line Sig
At (Point B), there were some that became 0 V when opened with the bus signal line.

When the enable signal EN is "H" and the direction signal (direction signal) Dir is "H", the output of the AND circuit 11 becomes "L" and the output element 13 operates.
The signal from the signal line Sig on the transceiver 3 side is output to the bus signal line. Further, when the enable signal EN is “H” and the direction signal (direction signal) Dir is “L”, the output of the AND circuit 12 becomes “L” and the input element 14
Operates to receive the signal from the bus signal line on the signal line Sig on the transceiver 3 side.

(B) Description of active insertion FIG. 6 (b) is a description of noise on the bus when a pin contacts when the point A is at "H" level (3.3V). Before the pin on the) side and the pin on the signal line Sig (point B) contact, the signal line Sig (point B) is 0 V, so when the potential at the point A is 3.3 V (“H”), the pin Contact with each other and insertion noise occurs. This figure shows that the insertion noise is below the threshold level.

In FIG. 6C, the point A is at the "L" level (0V).
This is an explanation of the noise on the bus when the pins contact each other, and the signal line Sig at the point B is 0V before the pin at the point A on the bus signal line and the pin at the point B of the signal line Sig contact each other. When the potential at the point A is 0 V (“L”), noise does not occur even if the pin contacts.

[0015]

In the conventional device as described above, noise may be generated in the signal line on the bus side at the timing when the signal line comes into contact during the active insertion of the unit, and the system may malfunction. there were.

The present invention solves such a conventional problem, and reduces noise generated during active replacement of a unit using an element whose open-circuit voltage is 0 V or close to the power supply voltage with a small circuit amount and low cost. The purpose is to keep it below a certain level.

[0017]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, 1 is a mother board, 2 is a unit,
3 is a transceiver, 5a is a potential determination circuit, 6 is a connector, 16 and 17 are drivers, is a ground (GND),
Is a power supply (Vcc), is a signal line (Sig), is a clock line (CLK), and R1 and R2 are resistors.

The present invention has the following structure in order to solve the above conventional problems. (1): has a connector 6 for connecting to the motherboard 1,
In the active insertion unit 2 in which the connector 6 is connected in the order of the ground, the power supply and the signal line at the time of insertion, the potential determining circuit 5a which gives the signal line an intermediate potential between the ground and the power supply voltage at the time of the active insertion of the connector 6. Equipped with.

(2): In the active insertion unit of (1), the potential determining circuit 5a uses resistance division. (3): In the active insertion unit of (1) above, clocks are supplied to the plurality of units 2 by the individual drivers 16, 17 ...

(Operation) The operation based on the above configuration will be described. When connecting the mother board 1 and the unit 2 with the connector 6, when the connector 6 is inserted, the ground, the power source,
Connect in the order of signal lines. Then, when the connector 6 is actively inserted, the potential determining circuit 5a causes the signal line to have an intermediate potential between the ground and the power supply voltage. For this reason,
Even when an element whose potential when the signal line is open is 0 volt or close to the power supply voltage Vcc is used, noise during active insertion can be suppressed to a certain level or lower.

Further, by using the resistance division for the potential determining circuit 5a, the noise at the time of active insertion can be suppressed to a certain level or less with a small circuit amount and low cost.
Furthermore, the individual drivers 16 and 1 are provided in the plurality of units 2.
Since the clock is supplied at 7 ..., When the unit 2 is actively inserted, it is possible to prevent waveform distortion from occurring in units other than the unit 2.

[0022]

2 to 4 are views showing an embodiment of the present invention, and an embodiment of the present invention will be described below with reference to the drawings. 1): Description of Overall Configuration FIG. 2 is an overall configuration diagram of the embodiment. In FIG. 2, a motherboard 1 of an information processing device or the like has a sequence connector 6a for connecting a plurality of units 2a, 2b, 2c, a clock circuit 9, a ground (GND), a power supply (Vcc), and a signal line of a common bus. (Sig) and clock lines (CLK) -1, -2, -3 are provided.

The plurality of units 2a, 2b, 2c are provided with a transceiver 3, a resistance 5 for determining an active insertion level, a sequence connector 6b, a control circuit 7, and a voltage detection circuit 8, and the transceiver 3 has a capacitance 4, AND circuit 11,
12, an output element 13 and an input element 14 are provided. It should be noted that the ∘ marks of the AND circuits 11 and 12, the output element 13, and the input element 14 indicate that they are active low (operate when "L"). Further, the capacitance 4 includes the wiring capacitance and the input capacitance.

The active insertion level determining resistor 5 has a resistor R.
1 and R2 voltage dividing resistors are provided. The sequence connectors 6a and 6b have a ground (GND) and a power supply (Vc).
c), the connection pins of the signal line (Sig) and the clock line (CLK) (-1, -2, -3) of the common bus are provided respectively, and the lengths of the connection pins of the sequence connector 6a are different. . The clock circuit 9 includes a clock generator 15, a clock distribution circuit (driver) 16,
17, 18 are provided.

The transceiver 3 switches between transmission and reception of the signal line Sig by the enable signal EN of the control circuit 7 and the direction signal (direction signal) Dir.

The active insertion level determining resistor 5 is connected to the power source (V
The voltage between cc) and ground (GND) is divided by resistors R1 and R2 and supplied to the signal line Sig. When the signal line Sig is in a high impedance state, the intermediate voltage (Vcc and G
The potential between ND). In addition, the resistance value R1,
The resistance value of R2 is set so as not to adversely affect the signal when the signal line Sig is not in the high impedance state. The output element 13, the input element 14, and the active insertion level determining resistor 5 are provided for each of the plurality of signal lines Sig (not shown).

The clock from the clock generator 15 is sent to the unit 2 via the clock driver 16 which is a buffer.
clock line-1 to a, clock line-2 to unit 2b via clock driver 17, clock line-3 to unit 2c via clock driver 18
And are connected respectively.

(A) Description of Active Insertion FIG. 2 shows an example in which the units 2b and 2c are mounted on the mother board 1 by the sequence connectors 6a and 6b, and the unit 2a is active inserted in the operating state.

When the unit 2a is actively inserted, since the connection pins of the sequence connector 6a have different lengths, the ground (GND) is first contacted, and then the power supply (V
cc) makes contact, and finally the signal line (Sig) and clock line (CLK) -1 make contact.

In the unit 2a, the voltage detection circuit 8 generates a reset (RST) signal when the power supply (Vcc) comes into contact, and the control circuit 7 is reset for a predetermined time. As a result, the enable signal EN of the transceiver 3 is turned off (“L”) (EN is negated), and the signal line Si
g contacts the pin of the sequence connector 6a in the high impedance state.

When a transceiver in which the open voltage of the signal line Sig is 0V is used, the unit 2a is actively inserted without the division resistors R1 and R2, and the bus signal line is at the "H" level at the contact timing. Then, the potential on the bus drops below the threshold for a moment, causing the circuit to malfunction.

However, the unit 2a is actively inserted by the resistance 5 for determining the active insertion level, which is set to the intermediate voltage in advance. This makes it possible to suppress the noise generated on the bus to a certain amount or less, regardless of whether the potential of the bus signal line at the time of insertion is “H” or “L”. There are various active insertion level determining means such as connecting to a voltage generation source by a resistor, but resistance division is most advantageous in terms of physical quantity and cost.

(B) Description of Clock Circuit In order to improve bus performance, the bus is generally operated in synchronization with a predetermined clock. On the other hand, when the unit is hot-swapped, if the pins of the sequence connectors 6a and 6b come into contact with each other at the rising and falling edges of the clock, the waveform of the clock may be broken and the system may not operate normally even if the above measures are taken. .

Therefore, the units to be replaced 2a, 2b,
Separate clock drivers 16, 17 and 18 are provided for each 2c in the clock circuit 9 to prevent waveform distortion in the clocks supplied to the units 2b and 2c other than the unit 2a when the unit 2a is actively inserted. There is.

2): Description of the sequence connector The sequence connector determines the connection order of the pins by making the connection pins of the connectors different in length and preventing malfunction of the circuit when the unit is hot inserted. is there.

FIG. 3 is an explanatory diagram of the sequence connector. In FIG. 3, the motherboard 1 is provided with a sequence connector 6a, and the unit 2a is provided with a sequence connector 6b. These sequence connectors 6a and 6b have a ground (GND), a power supply (V
cc), a common bus signal line (Sig), and a clock line (CLK) -1 connection pin are provided respectively, and the lengths of the connection pins of the sequence connector 6a are all the same, but the connection pins of the sequence connector 6b. Are of different lengths.

When the unit 2a is actively inserted, since the connecting pins of the sequence connector 6b have different lengths, the ground (GND) is first contacted, and then the power supply (V
cc) makes contact, and finally the signal line (Sig) and clock line (CLK) -1 make contact.

The sequence connector of FIG. 3 has different connection pin lengths of the sequence connector 6b, but the sequence connector of FIG. 2 has different connection pin lengths of the sequence connector 6a. It is different. However, any sequence connector may be used as long as the connecting order of the pins is the same, and the male type and the female type of the connecting pins can be reversed.

3): Description of Connection of Signal Lines FIG. 4 is an explanatory view of connection of signal lines. 4A illustrates the signal line circuit, and FIG. 4B illustrates the point A at the “H” level (3.
The noise on the bus when the pin contacts at 3V), and FIG. 4C illustrates the noise on the bus when the pin contacts at the "L" level (0V) at the point A.

In FIG. 4A, a bus signal line on the motherboard side to which a plurality of units are connected and a signal line Sig of the transceiver 3 on the active insertion unit side are connected by a sequence connector during system operation on the motherboard side. Is.

The sequence connector is provided with connecting pins, and when the pins contact each other, the point A on the bus signal line side and the point B on the transceiver 3 side are connected. The signal line Sig has a power supply (Vcc) and a ground (G).
ND) voltage is divided by resistors R1 and R2
The active insertion level determining resistor 5 supplied to g (point B) is connected. The transceiver 3 includes a capacitor 4, an AND circuit 11, an AND circuit 12, an output element 13, and an input element 14.
Is provided.

The circles of the AND circuits 11 and 12, the output element 13 and the input element 14 indicate that they are active low (operate when "L"). Also, capacity 4
Indicates the wiring capacitance and the input capacitance.

(A) Description of Transceiver Operation In the transceiver 3, when the enable signal EN is "L",
The outputs of the AND circuits 11 and 12 are both "H", and the output element 13 and the input element 14 are both off. As a result, the signal line Sig (point B) becomes high impedance. This high impedance signal line Sig
(Point B) becomes a potential close to the threshold level (about 1.5 V) by the active insertion level determining resistor 5 when opened to the bus signal line.

When the enable signal EN is "H" and the direction signal (direction signal) Dir is "H", the output of the AND circuit 11 becomes "L" and the output element 13 operates.
The signal from the signal line Sig on the transceiver 3 side is output to the bus signal line. Further, when the enable signal EN is “H” and the direction signal (direction signal) Dir is “L”, the output of the AND circuit 12 becomes “L” and the input element 14
The signal line Sig on the transceiver 3 side receives the signal from the bus signal line.

(B) Description at the time of active insertion FIG. 4 (b) is a description of noise on the bus when the pin contacts when the point A is at "H" level (3.3 V). Before the point A and the pin at the point B on the transceiver 3 side are in contact, the signal line Sig at the point B is at the threshold level (about 1.5 V) due to the resistance 5 for determining the active insertion level. When the potential is "H", even if the pin contacts and the insertion noise occurs, it does not fall below the threshold level.

In FIG. 4C, the point A is at the "L" level (0V).
This is an explanation of the noise on the bus when the pins contact each other. Before the pin at the point A on the bus signal line and the pin at point B on the transceiver 3 side contact, the signal line Sig at the point B determines the active insertion level. Since the potential is close to the threshold level (about 1.5V) due to the resistor 5 for use, the potential at the point A is "L".
At (0V), even if the pins come into contact with each other and insertion noise occurs, the threshold level is not exceeded.

As described above, the open circuit voltage of the signal line of the unit is set to the intermediate level by the resistance for active insertion level determination (resistance division), so that the noise generated in the signal line during the active insertion of the unit is minimized. Can be suppressed to
Further, this can be performed with a small circuit amount and low cost. Further, for example, any transceiver element (the output element 13, the input element 14, etc.) whose open-circuit voltage is “H” or “L” can be used, and the flexibility of selecting the transceiver element can be increased. Then, the optimum one for the system can be used.

[0048]

As described above, the present invention has the following effects. (1): When the connector is hot-inserted, the potential determining circuit gives the signal line an intermediate potential between the ground and the power supply voltage.
Even when an element whose potential when the signal line is open is 0 volt or close to the power supply voltage Vcc is used, noise during active insertion can be suppressed below a certain level. In addition, the degree of freedom in selecting elements to be used is increased, and the optimum technology for the system can be used.

(2): By using resistance division in the potential determining circuit, noise at the time of active insertion can be suppressed to a certain level or less with a small circuit amount and low cost. (3): Since clocks are supplied to a plurality of units by individual drivers, it is possible to prevent waveform distortion from occurring in units other than the unit when the unit is hot inserted.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an overall configuration diagram of an example.

FIG. 3 is an explanatory diagram of a sequence connector according to an embodiment.

FIG. 4 is an explanatory diagram of connection of signal lines in the embodiment.

FIG. 5 is an explanatory diagram (1) of a conventional example.

FIG. 6 is an explanatory diagram (2) of a conventional example.

[Explanation of symbols]

 1 Motherboard 2 Unit 3 Transceiver 5a Potential determining circuit 6 Connector 16 and 17 Driver ground (GND) Power supply (Vcc) Signal line (Sig) Clock line (CLK) R1 and R2 Resistance

Claims (3)

[Claims] 1. A connector for connecting to a mother board,
The connector includes an active insertion unit that connects a ground, a power supply, and a signal line in this order at the time of insertion, and includes a potential determination circuit that makes the signal line have an intermediate potential between the ground and the power supply voltage when the connector is actively inserted. Characterized active insertion unit. 2. The active insertion unit according to claim 1, wherein the potential determining circuit uses resistance division. 3. The active insertion unit according to claim 1, wherein clocks are supplied to the plurality of units by individual drivers.