JPH09160736A - Apparatus and method for overlay of image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the overlay function by hardware which solves the problem points of a conventional overlay system by addition to a general graphic controller. SOLUTION: This processing circuit has an address search circuit, an internal video memory 506, and an overlay data processing circuit 503. The address search circuit always monitors an object address at the time of the read operation of the graphic controller 502 and the internal video memory 506 stores image data to be overlaid. When a read address specified by the graphic controller 502 enters an address area to be overlaid, the image data from the internal video memory 506 are transferred to the graphic controller 502 instead of image data from an ordinary video memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates mainly to image overlay in a computer system, and more particularly to an overlay apparatus and method using RAM for overlay.

[0002]

2. Description of the Related Art In recent years, with the spread of multimedia, performance requirements for a graphics controller and its peripheral circuits for image processing in computer systems have been increasing. In particular, when displaying moving images and still images from a plurality of sources on a single display at the same time, a technique for displaying a plurality of such images in an overlapping manner, that is, an overlay technique has become important.

The following are the major conventional overlay technologies:
1. A method of switching the output of the image display signal at high speed, and 2. There are two shared memory methods,
Each has the following problems.

1. Method for switching output of image display signal at high speed The method will be described with reference to FIG. A graphic controller 31 connected to the system bus 30 for controlling the overall screen display, and a video memory 3 for storing screen display data under the control of the graphic controller
3, an overlay data processing circuit 34 for storing and processing display data different from the video memory, and a switch circuit 32 for switching the image signal 35 from the graphic controller 31 and the image signal 36 from the overlay circuit. , FIG.

However, in this method, it is generally necessary to have the image output circuits separately for the two systems of the graphic controller system and the overlay data processing circuit system as described above. Further, since the image display signal is an analog signal, it is difficult to design a circuit and a board necessary for the signal processing, as compared with a digital signal. In addition, it is not desirable in terms of cost because it has two similar circuits redundantly. On the other hand, in the case where the image display signal is switched in the preceding stage for converting into an analog signal,
There is also a problem that the two asynchronous display signals must be synchronized.

[0006] 2. Shared Memory Method The method will be described with reference to FIG. A graphic memory controller 42 connected to a system bus 41 similar to the system bus 31 shown in FIG. 3 for controlling the overall screen display, and a video memory for storing data for screen display under the control of the graphic controller. 46, and an overlay data processing circuit 47 for storing and processing display data different from the video memory. In order for the graphic controller 42 and the overlay data processing circuit 47 to access the same video memory 46 with each other, an arbitration function for arbitrating the memory access is required. With such an arbitration function, it is possible to solve the problem of simultaneously accessing the same video memory 46.

This method requires the graphic controller to have an arbitration function for accessing the video memory. That is, only a graphic controller having an arbitration function in advance can be used. On the other hand, there are few graphic controllers having such an arbitration function on the market, and since the cost is high, the range of selection of the graphic controllers usable in the computer system is extremely narrowed. Also, with this method, if the original image data at the same address as the overlay image data is actually rewritten and you want to restore it to the original image data, the original data is again stored in the video memory. There is a problem in that it is necessary to overwrite the same address in the memory, which takes extra time.

[0008]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to provide a hardware overlay function in addition to a general graphic controller, which solves the above-mentioned problems of the conventional overlay method. To do.

That is, (1) circuit processing is easy and low cost because image data is entirely processed by digital circuits, and (2) high-speed clock signal because there is no need to synchronize two display signals. You do n’t have to communicate with
(3) General graphics currently on the market
An overlay circuit that can utilize the controller is provided by the arrangement of the present invention.

[0010]

In order to implement the invention of the present application, a new and improved overlay data processing circuit is introduced. This overlay data processing circuit has an address search circuit, an internal video memory, and an overlay data control circuit as characteristic components.

The address search circuit constantly monitors the target address during the read operation of the graphic controller,
The internal video memory stores image data to be overlaid. If the read address specified by the graphic controller falls within the address area to be overlaid, the graphic
The overlay data control circuit controls the data buffer connected to the controller to transfer the image data from the internal video memory to the graphic controller in place of the image data from the normal video memory.
By such an operation, desired image data is overlaid on a desired screen position.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in the following order with reference to the drawings.

A. Personal computer system (Fig. 1) B. Hardware configuration of personal computer system (Fig. 2) C. Graphic controller peripheral circuit (Fig. 5) D. Internal Configuration of Overlay Data Processing Circuit of the Present Invention (FIG. 6) E. Operation of the present invention (FIGS. 7 to 9)

For convenience of explanation, the configuration and operation contents of the device of the present invention will be described below by mainly using an example of a notebook personal computer which has been widely sold in recent years.
The present invention is not limited to the notebook personal computer, and can be implemented in a wide range of computer systems such as desktop type and floor stand type.

A. Personal Computer System (FIG. 1) Referring to FIG. 1, there is shown an overall view of a computer system for practicing the present invention. Computer·
The main body 10 of the system may be a portable PC as shown in the figure, or may be a desktop or other PC or workstation. The computer system 10 includes a keyboard 12 as an input device for characters and the like, a liquid crystal panel 13 as an output device for characters and figures, a CD-ROM drive 14 as a large-capacity storage medium, a speaker 11 as an output device for voice, and a recent device. In some cases, a video camera 15 as an image input device is provided as standard. Note that details of the keyboard, the liquid crystal panel, and the like are not shown in FIG. 1 because they are not directly related to the configuration of the present invention.

B. Hardware Configuration of a Personal Computer System (FIG. 2) Referring to FIG. 2, there is shown a block diagram of the logic circuits internal to the notebook computer of FIG. 1 and typically located on a motherboard (planar). ing. In recent personal computer systems, there are a plurality of buses to which devices of various processing speeds are connected, and a circuit called a bus bridge that performs protocol conversion between the buses bridges the plurality of buses. . As a typical example of such a bus configuration, FIG. 2 shows a CPU local bus 212 directly connected to the CPU 202, PCI buses 213 and 216 for connecting a relatively high speed peripheral device, and a relatively low speed peripheral device. ISA bus 22 for connecting to
1, PCMCIA bus 219 and IDE bus 217 are shown.

The CPU bus 212 and the PCI bus 2
13 for connecting the host bridge / memory control circuit 204, the PCI bus 213 and the ISA bus 221 for connecting the PCI-ISA bus bridge circuit 21.
5, PCI-PCMCIA bus bridge circuit 214 for connecting PCI bus 213 and PCMCIA bus 219
Etc. are also shown in FIG. Further, each bus is connected with a plurality of peripheral devices adapted to the processing speed of the bus. For example, a CPU is connected to the fastest CPU local bus 212 as its name suggests, a high speed graphic / video controller 222 is connected to the PCI bus 213, and a keyboard controller 229 and an audio controller are connected to the ISA bus 221. 230, or a Super I / O controller 231 which is a general-purpose I / O control circuit is connected.

Furthermore, the host bridge / memory control circuit 204 has a memory control function in addition to the bus bridge function, and the BIO is connected via the memory data buffer 205.
It is connected to the SROM 206 and the main memory RAM 207. The graphic / video controller 222 connected to the PCI bus 213 has a video memory 223 for screen display, is connected to the LCD panel by a digital signal via a buffer 224, and has an analog front end (AFE). ) Digitize and capture external analog video input via 225.

C. Graphic Controller Peripheral Circuit (FIG. 5) FIG. 5 schematically shows the configuration of the present invention. FIG. 5 corresponds to FIGS. 3 and 4 described above as a conventional example. System bus 5 as a main component
01 (corresponding to 213 in FIG. 2), a graphic controller 502 (corresponding to 222 in FIG. 2), and a video memory 505 (22 in FIG. 2) for storing image data.
3), the overlay data processing circuit 503, the data buffer 504, etc. are shown in FIG. One of the main differences between the configuration of the present invention and the configurations shown in FIGS. 3 and 4 described above is that the graphics peripheral circuit shown in FIG. 5 has a video memory 505 and a graphics controller 502. Is to have a data buffer 504 between them. Another difference is that the overlay data processing circuit 503 is directly connected to the system bus 501, that is, from the CPU of the computer system to the overlay data processing circuit 50.
3 is that it is directly accessible. The overlay data processing circuit 503 is connected to the output control signal of the buffer 504 by the gate control signal 512,
A gate control signal 512 is used to control output permission and output prohibition of data from the video memory.

That is, when the gate control signal 512 is put into the output enable state by the overlay data processing circuit, the buffer 504 outputs the data from the video memory to the data bus 510 and the overlay data processing circuit.
The buffer 504 does not output the data from the video memory 505 to the data bus 510 when the gate control signal 512 is disabled by the data processing circuit.

Further, the overlay data processing circuit is
As will be described later, a unique image memory is built in, and the data is transferred to the graphic controller 502 via the data line 510 connected to the graphic controller 502 via the data line 511. On the other hand, the video memory 505 and the overlay data processing circuit 5
The image data from 03 is controlled and processed by the graphic controller 502, and then sent via a display signal line 508 to a display device (not shown) or the like connected to the computer system, and finally displayed. Display an overlay image on the device.

D. Internal Structure of Overlay Data Processing Circuit of Present Invention (FIG. 6) FIG. 6 shows a detailed internal structure of the overlay data processing circuit 503 which is one of the characteristic components of the present invention shown in FIG. Has been done. The overlay data processing circuit 600 (corresponding to 503 in FIG. 5) is connected as a main component to the overlay data control circuit 607 that controls the entire overlay data processing circuit 600, and the overlay data control circuit. Internal video ·
A memory control circuit 610 that controls the operation of the memory, and a system that controls the interface with the system bus 601.
Address search for monitoring the target address at the time of reading (writing) sent to the video memory 604 through the address line and control line 613 from the bus interface circuit 609 and the graphic chip 602 realizing the graphic controller. Circuit 60
6. A digital video interface circuit 608 for taking a digital video signal from a video A / D circuit for converting an analog signal from an external video device into a digital signal into the overlay data processing circuit, and RGB or YUV Format conversion circuit 61 for converting between a plurality of video data formats such as
One. In addition, the overlay data processing circuit 600 can also have a data buffer 603 built therein by design. Meanwhile, the internal memory 612
Can be provided outside the overlay data processing circuit 600 by design.

The operation of the overlay data processing circuit 600 shown in FIG. 6 will be described with reference to FIGS.

E. Operation of the Present Invention (FIGS. 7 to 9) First, FIG. 7 shows a flowchart of the operation of the present invention when overlaying two image data. First, in block 71, the address range of the area of the video memory to be overlaid is specified.
In block 72, the address search circuit 606 constantly monitors the next address read from the video memory 604 (corresponding to 505 in FIG. 5) by the graphics chip 602 (corresponding to 502 in FIG. 5), and the read address is Checks if it is in the address range covered by the specified overlay. As a result, if the address to be read (read) is within the range of the overlaid address area, the next block 73
If it is outside the range of the address area of the overlay, the process returns to the block 72 and the read address monitoring is continued. At block 73, the overlay data processing circuit 600 determines that the graphics chip 602 is about to read the address area specified in the overlay, and the overlay data processing circuit 600 determines that the internal overlay
Data buffer 603 using data control circuit 607
Control.

Such overlay data control circuit 607
Actually uses control line 621 to
3 (corresponding to 504 in FIG. 5) is prohibited. afterwards,
Moving to block 74, the overlay data processing circuit 600 uses the internal memory control circuit 610 to read the image data to be overlaid from the internal memory 612, and the overlay data control circuit 607 sends the image data on the data lines 613 and 614. To output the overlay data read from the internal memory 612. As a result, the graphics chip 602 will read the overlay data from such memory 612 instead of the data from the video memory 604. Then, this overlay data is sent to the display device by the graphic chip 602 and displayed on the screen. afterwards,
By returning to the block 72 again and repeating the above operation, desired image data is overlaid on the desired area on the display device.

FIG. 8 shows the operation of the overlay data processing circuit 600 when capturing image data from an external video. First, in block 81, the converted data format of the data captured from the external video is specified. In block 82, the digital
The video interface circuit 608 is a video A / D
The video data received from 605 is transferred to the format conversion circuit 611. In block 83, the format conversion circuit 611 that received the video data
Converts the captured video data into the data format specified in block 81. After that, the video data converted into the designated format is written in the internal memory 612 under the control of the memory control circuit 610.

FIG. 9 shows an overlay data processing circuit 6 for taking in image data via the system bus.
The operation of 00 is shown in the flow chart. First, the converted data format is specified (block 9).
1). System bus interface circuit 609
From the master device such as a processor to the system bus 60
The image data transferred to the overlay data processing circuit 600 via the format conversion circuit 611
(Block 92). The format conversion circuit 611 that has received the image data converts the received image data into the already specified data format. The converted image data is then written to the video memory 612 under the control of the memory control circuit 610 (block 93). By such operation of the graphic peripheral circuit 600, the image data is taken into the video memory by a master device such as a processor.

In summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) An image processing apparatus capable of overlaying a plurality of images, (a) an image processing controller for processing and controlling images, and (b) connected to the image processing controller to store image data. And an image memory for (c) an image memory for overlay which is connected to the image processing controller, and the image processing controller reads the data from a predetermined address area of the image memory. An image processing apparatus comprising: an overlay processing circuit that outputs the image data stored in the image memory for overlay instead of the image data stored in the memory to the image processing controller.

(2) The image processing device described in (1) further includes (d) a data buffer connected between the image processing controller and the image memory. An image processing apparatus, wherein the buffer inhibits output of image data from the data buffer when the image processing controller reads data from a predetermined address area of the image memory.

(3) An image overlay processing circuit which is connected to a graphic controller and its video memory and cooperates to perform image overlay, comprising: (a)
When the graphic controller reads data from the video memory, an address search circuit that monitors an address of the video memory to be read, and (b) an overlay that is separate from the video memory An overlay memory for storing an image for a video, and (c) the overlay instead of the data at the predetermined address of the video memory when the address search circuit detects that a predetermined address is read.・
A circuit for transferring data corresponding to the predetermined address of the memory to the graphic controller, and an image overlay processing circuit.

(4) The image overlay processing circuit according to (3) further includes (d) a buffer circuit connected to the video memory, the buffer circuit extending from the video memory to the graphic controller. An image overlay processing circuit, which controls the data output of the image overlay processing circuit.

(5) The image overlay processing circuit according to (3) further includes (e) a system bus interface circuit for transferring data to and from the system bus. An image overlay processing circuit, wherein the CPU can directly access the overlay memory.

(6) The image overlay processing circuit according to (3) further has a format conversion circuit (f) for performing format conversion of image data.

(7) The image overlay processing circuit according to (3) further has (g) an image interface for taking in image data from the outside.

(8) A computer system including a graphic controller and an image overlay processing circuit which is connected to a video memory of the graphic controller and cooperates with each other to overlay an image, wherein: (a) a processor; and (b) a main A memory, (c) a system bus for connecting peripheral devices, and (d) a graphic connected to the system bus
A controller, (e) a video memory connected to the graphic controller, and (f) an overlay processing circuit connected to the system bus, the overlay processing circuit comprising:
(I) The graphic controller is the video
An address search circuit for monitoring an address of the video memory to be read when reading data from the memory, and (b) for storing an image for overlay, which is separate from the video memory When the overlay memory and (a) the address search circuit detects that a predetermined address is read, the data corresponding to the predetermined address of the video memory is replaced with the predetermined address of the overlay memory. A circuit for transferring data to the graphic controller, the computer system comprising:

(9) Image overlay for overlaying an image including a graphic controller, a video memory connected to the graphic controller, and an overlay memory internally connected to the graphic controller and the video memory A method for overlaying an image in a computer system having a processing circuit, comprising:
When the controller reads data from the video memory, the controller reads the address of the video memory to be read, (b) the address read by the step of reading the address, and a predetermined address. As a result of the comparing step and (c) comparing the addresses, if two addresses match, the data of the predetermined address of the overlay memory is replaced with the data of the predetermined address of the video memory. Transferring the image to the graphics controller.

[0038]

As described above, the configuration of the present invention solves the problems of the conventional overlay method, and provides an overlay function by hardware in addition to a general graphic controller.

[0039]

[Brief description of the drawings]

FIG. 1 is a diagram representing a computer system for implementing the present invention.

FIG. 2 is a block diagram illustrating a logic circuit inside a computer system for implementing the present invention.

FIG. 3 is a block diagram showing a conventional method of switching the output of an image display signal at high speed.

FIG. 4 is a block diagram showing a conventional shared memory system.

FIG. 5 is a block diagram showing a graphics peripheral circuit for implementing the present invention.

FIG. 6 is a detailed block diagram of an overlay data processing circuit for implementing the present invention.

FIG. 7 is a flowchart showing an operation when overlaying image data according to the present invention.

FIG. 8 is a flowchart showing an operation when image data is captured from a video A / D according to the present invention.

FIG. 9 is a flowchart showing an operation when image data is fetched from the system bus according to the present invention.

[Explanation of symbols]

 10 Computer System 11 Speaker 12 Keyboard 13 Liquid Crystal Panel (LCD) 14 CD-ROM Drive 15 Video Camera 201 Clock Generation Circuit 202 CPU 204 Host Bridge / Memory Control Circuit 214 PCI-PCMCIA Bridge Circuit 215 PCI-ISA Bridge Circuit 222 Graphics / Video Controller 223 Video Memory 229 Keyboard 30 System Bus 31 Graphic Controller 32 Switch Circuit 33 Video Memory 34 Overlay Data Processing Circuit 41 System Bus 42 Graphic Controller 46 Video Memory 47 Overlay Data Processing Circuit 501 System Bus 502 Graphic Controller 503 Overlay Data Processing 504 data buffer 505 video memory 601 system bus 602 graphic chip 603 data buffer 604 video memory 605 video A / D 606 address search circuit 607 overlay data control circuit 608 digital video interface circuit 609 system Bus interface 610 Memory control circuit 611 Format conversion circuit 612 Internal video memory

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/36 530 9377-5H G09G 5/36 530G (72) Inventor Norio Fujita Yasu, Yasu-gun, Shiga Prefecture 800 Miyake-shi, Miyagi-cho Japan IBM Japan Ltd. Yasu Plant

Claims (9)

[Claims] 1. An image processing apparatus capable of overlaying a plurality of images, comprising: (a) an image processing controller for processing and controlling images; and (b) connected to the image processing controller for storing image data. Image memory for
(C) Image data stored in the image memory when the image processing controller is connected to the image processing controller and has an image memory for overlay therein and the image processing controller reads data from a predetermined address area of the image memory. Instead of outputting the image data stored in the image memory for overlay to the image processing controller,
An image processing apparatus comprising: an overlay processing circuit. 2. The image processing apparatus according to claim 1, further comprising: (d) a data buffer connected between the image processing controller and the image memory, the data buffer An image processing apparatus, wherein the image processing controller prohibits output of image data from the data buffer when the image processing controller reads data from a predetermined address area of the image memory. 3. An image overlay processing circuit, which is connected to a graphic controller and its video memory and cooperates to perform image overlay, comprising: (a) the graphic controller reading data from the video memory. An address search circuit that monitors the address of the video memory to be read when
(B) an overlay memory for storing an image for overlay, which is separate from the video memory,
(C) When the address search circuit detects that a predetermined address is read, the data corresponding to the predetermined address of the overlay memory is replaced with the graphic data instead of the data of the predetermined address of the video memory. An image overlay processing circuit having a circuit for transferring to a controller. 4. The image overlay processing circuit according to claim 3, further comprising: (d) a buffer circuit connected to the video memory, the buffer circuit extending from the video memory to the graphic controller. An image overlay processing circuit characterized by controlling data output. 5. The image overlay processing circuit according to claim 3, further comprising (e) a system bus interface circuit for transferring data to and from the system bus. An image overlay processing circuit, wherein the CPU can directly access the overlay memory. 6. The image overlay processing circuit according to claim 3, further comprising (f) a format conversion circuit for performing format conversion of image data. 7. The image overlay processing circuit according to claim 3, further comprising (g) an image interface for taking in image data from the outside. 8. A computer system including a graphic controller and an image overlay processing circuit which is connected to a video memory of the graphic controller and cooperates with each other to overlay an image, comprising: (a) a processor; and (b) a main. A memory, (c) a system bus for connecting peripheral devices, and (d) a graphic connected to the system bus
A controller, (e) a video memory connected to the graphic controller, and (f) an overlay processing circuit connected to the system bus, wherein the overlay processing circuit is (i) the graphic When the controller reads data from the video memory, an address search circuit that monitors an address of the video memory to be read, and (b) an overlay circuit that is separate from the video memory. An overlay memory for storing an image, and (a) the overlay memory instead of the data of the predetermined address of the video memory when the address search circuit detects that a predetermined address is read. Of the data corresponding to the predetermined address of the When, characterized by comprising a computer system. 9. An image overlay process for overlaying an image including a graphic controller, a video memory connected to the graphic controller, and an overlay memory internally connected to the graphic controller and the video memory. A method for overlaying an image in a computer system having a circuit, comprising: (a) an address of the video memory to be read when the graphic controller reads data from the video memory. When the two addresses match as a result of the steps of: reading the address, (b) comparing the address read by the step of reading the address with a predetermined address, and (c) comparing the address, The video memo Method of performing an image overlay, characterized in that it comprises the steps of: transferring data of the predetermined address of the overlay memory to the graphics controller instead of the predetermined address data.