JPH09167745A - Chemical / mechanical polishing method and apparatus, and semiconductor substrate manufacturing method - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a semiconductor device or the like with high reliability and high integration. Kind Code: A1 The present invention provides a chemical / mechanical polishing method and apparatus for controlling the polishing pressure distribution of a workpiece to make the thickness of the workpiece (interlayer insulating film) uniform, and a semiconductor device. It is a method of manufacturing a substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing method for flattening a surface of an insulating film, a metal film or the like formed on a substrate for manufacturing a semiconductor integrated circuit or the like by chemical / mechanical polishing. The present invention relates to a semiconductor substrate manufacturing method for manufacturing a semiconductor substrate having the device and a semiconductor integrated circuit.

[0002]

2. Description of the Related Art For example, as a flattening technique for manufacturing a semiconductor substrate having a semiconductor integrated circuit or the like, conventionally, a plasma oxide film (P-SiO ₂ ) is formed and the surface thereof is formed so as to eliminate fine irregularities. This has been performed by a combination of forming a coated insulating film (SOG) by applying liquid glass on the glass and heating it, and performing etch back to reduce the thickness of the insulating film. However, in this flattening technique, a large step remains. Further, as the wiring width decreases, the need for improvement of step coverage has led to the development of Bias-ECRCVD technology and an organic source (TEOS) having a reflow effect. However, it has not been possible to sufficiently improve the step coverage with respect to the reduction of the wiring width accompanying the ultra-high integration.

On the other hand, chemical and mechanical polishing (CMP: Chem) for flatly polishing the surfaces of semiconductor chips, ceramic packages, multilayer ceramic packages and other electronic components.
The mechanical mechanical polishing technique is known in the specification and drawings of US Pat. No. 4,954,142. This conventional technique is a CMP (Chemical Mechanical) which is supported on a polishing surface plate and presses the surface of the electronic component against a polishing cloth coated with an abrasive to chemically and mechanically polish the surface.
Polishing).

[0004]

The above prior art (CM)
In P), since the fluctuation of the polishing pressure due to the deformation of the workpiece during the chemical / mechanical polishing is not taken into consideration, the polishing amount of the insulating film on the surface of the workpiece can be controlled. Therefore, there is a problem that the thickness of the insulating film or the like cannot be made uniform.

[0005] An object of the present invention is to solve the above problems.
It is an object of the present invention to provide a chemical / mechanical polishing method and apparatus capable of achieving uniform polishing of the thickness of an insulating film or the like formed on a substrate. Another object of the present invention is to carry out a flat chemical / mechanical polishing process on the surface of the interlayer insulating film on the semiconductor substrate, which has no fine irregularities and has no large steps, and which is, for example, 0.35 μm or less. It is an object of the present invention to provide a chemical / mechanical polishing method and apparatus capable of forming ultrafine wiring. Another object of the present invention is to provide a method of manufacturing a semiconductor substrate, which can simplify the manufacturing of a semiconductor substrate having a multilayer wiring layer having an ultrafine wiring having a wiring width of 0.35 μm or less. .

[0006]

In order to achieve the above-mentioned object, the present invention is to control the polishing pressure by the shape of a supporting surface of a chuck for supporting a substrate to chemically or mechanically adjust the surface of the substrate. Chemically characterized by performing various polishing processes
This is a mechanical polishing method. The present invention also controls the polishing pressure by the curved surface shape or the uneven shape of the support surface of the chuck that supports the substrate to chemically or chemically remove the surface of the substrate.
A chemical / mechanical polishing method characterized by performing mechanical polishing processing. Further, the present invention controls the polishing pressure by the curved surface shape or the uneven shape of the support surface of the chuck for supporting the substrate having the insulating film surface to perform the chemical / mechanical polishing process on the insulating film surface on the substrate. This is a chemical / mechanical polishing method characterized by being performed. Further, the present invention controls the polishing pressure by the curved surface shape or the uneven shape of the support surface of the chuck for supporting the substrate having the metal film surface to perform the chemical / mechanical polishing process on the metal film surface on the substrate. This is a chemical / mechanical polishing method characterized by being performed. Further, the present invention controls the polishing pressure by the curved shape or the uneven shape of the support surface of the chuck that supports the substrate having the insulating film surface, and the variation in the polishing amount of the insulating film surface on the substrate is ± 5% or less. It is a chemical / mechanical polishing method characterized by performing a chemical / mechanical polishing process with an unevenness of the insulating film surface of 0.2 μm or less.

Further, according to the present invention, an interlayer insulating film forming step of forming an interlayer insulating film on a lower layer wiring on a substrate and a supporting surface of a chuck for supporting the substrate on which the interlayer insulating film is formed in the interlayer insulating film forming step. A chemical / mechanical polishing step of controlling the polishing pressure by a curved surface shape or an uneven shape to perform a chemical / mechanical polishing process on the surface of the interlayer insulating film of the substrate to flatten the surface; A method of manufacturing a semiconductor substrate, comprising: an upper layer wiring forming step of forming a desired upper layer wiring on the interlayer insulating film flattened by a mechanical polishing step. The present invention also provides an interlayer insulating film forming step of forming an interlayer insulating film on a lower layer wiring on a substrate, and a curved surface shape of a supporting surface of a chuck for supporting the substrate on which the interlayer insulating film is formed in the interlayer insulating film forming step. A chemical / mechanical polishing process for controlling the polishing pressure by the uneven shape to perform a chemical / mechanical polishing process on the surface of the interlayer insulating film of the substrate to flatten the surface; and the chemical / mechanical polishing process. Contact hole forming step of forming a contact hole in the interlayer insulating film flattened by various polishing processing steps, and a contact stud forming a contact stud by embedding a conductive material in the contact hole formed in the contact hole forming step After the forming step and the contact stud forming step,
And a step of forming a desired upper layer wiring on the interlayer insulating film, the method of manufacturing a semiconductor substrate.

Further, according to the present invention, there is provided an interlayer insulating film forming step of forming an interlayer insulating film on a lower layer wiring on the substrate, and a supporting surface of a chuck for supporting the substrate having the interlayer insulating film formed in the interlayer insulating film forming step. A chemical / mechanical polishing step of controlling the polishing pressure by a curved surface shape or an uneven shape to perform a chemical / mechanical polishing process on the surface of the interlayer insulating film of the substrate to flatten the surface; and the SiO ₂ film forming step of forming a SiO ₂ film by CVD on the planarized interlayer insulating film in-mechanical polishing step, the upper layer wiring SiO ₂ film formed by the SiO ₂ film forming step And a step of forming an upper wiring, which is a method of manufacturing a semiconductor substrate. Further, the present invention comprises a chuck for supporting the substrate on a supporting surface formed in a curved shape or an uneven shape so that the polishing pressure is controlled, and the surface of the substrate is chemically and flatly formed.
The chemical / mechanical polishing apparatus is characterized by being configured to perform mechanical polishing processing. That is, according to the present invention, a support having a uniform thickness is attached to the surface of the chuck, the polishing machine surface plate and the chuck are rotated to drop the polishing liquid onto the polishing pad, and the surface of the substrate is polished to the polishing pad. It was configured to be subjected to chemical and mechanical polishing processing by pressing and sliding on. Further, the present invention is characterized in that, in the chemical / mechanical polishing apparatus, an elastic body is provided on a support surface of the chuck. Further, in the chemical / mechanical polishing apparatus of the present invention, the contour line of the support surface of the chuck is a curve having a plurality of inflection points. Further, the present invention is characterized in that, in the chemical / mechanical polishing apparatus, the height difference between the convex portion and the concave portion of the supporting surface of the chuck is 0.5 μm to 10 μm.

As described above, according to the present invention, it is possible to make the polishing amount in the surface of the substrate, which is the workpiece, uniform, and to make the thickness of the interlayer insulating film in a semiconductor device uniform, for example. High reliability and high integration of the semiconductor device can be realized. That is, since the semiconductor integrated circuit forms a multilayer wiring layer, an interlayer insulating layer exists between the lower layer wiring and the upper layer wiring, and the surface of this interlayer insulating film has, for example, a polishing amount variation of ± 5% or less with accuracy. Moreover, the micro unevenness is 0.2μ
m or less, and as a result, a wiring film having a uniform thickness can be formed on the interlayer insulating film, and the focus margin in exposure is expanded to easily form a wiring with a wiring width of 0.35 μm or less. can do. Further, a step of about 1 μm existing on the surface of the interlayer insulating film before polishing can be made into a minute unevenness of 0.1 μm or less after polishing, and as a result, a wiring width of 0.25 μm or less can be formed on the surface of the interlayer insulating layer. Wiring can be easily formed. According to the present invention,
When a conductor such as tungsten is formed as a contact stand in the contact hole formed in the interlayer insulating layer by selective CVD, the conductive film such as tungsten grown by using the minute defects on the interlayer insulating film as nuclei is completely removed. Thus, it is possible to form an interconnection having high reliability on the interlayer insulating film. Further, according to the present invention, since high flatness can be obtained on the surface of the insulating film or the metal film, for example, defocusing can be prevented in the exposure process, exposure with high resolution can be realized, and high integration can be achieved. can do.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. The overall structure of the chemical / mechanical polishing apparatus and the chemical / mechanical polishing procedure according to the present invention will be described with reference to FIG. FIG. 1 is a conceptual diagram of a chemical and mechanical polishing apparatus. That is, the workpiece (substrate: wafer) 1 is mounted on a support body 3 attached (attached) on a chuck 2 which is a rigid body rotatable by a motor (not shown). On the rotating polishing machine surface plate 4, a polishing pad 5 made of, for example, a hard polyurethane foam, which is resistant to acid or alkali and has excellent wear resistance, is attached to improve flatness. On the polishing pad 5, add Si to the solution containing alkali.
Colloidal silica containing O ₂ abrasive grains or a polishing liquid 6 containing alumina or cerium oxide abrasive grains in a solution containing an acid is supplied. Chemical and mechanical polishing (CMP: Chemic
al Mechanical Polishing) is supported by a chuck 2 that is rotated by a motor (not shown) while supplying a polishing liquid 6 onto a polishing pad 5 mounted on a polishing machine surface plate 4 that rotates as shown in FIG. The processed workpiece (substrate: wafer) 1 is brought into contact with the polishing pad 5, and a polishing load 7 is further applied to the chuck 2 so that the polishing machine surface plate 4 is moved in the radial direction of the polishing machine surface plate 4 as indicated by an arrow 11. 4, while being relatively reciprocated between the polishing liquid 6 and the polishing liquid 6, a chemical reaction by a chemical reaction with, for example, an alkaline solution contained in the polishing liquid 6 and a mechanical polishing by abrasive grains such as SiO ₂ are used. -Mechanical polishing (CMP) is performed on the workpiece (eg, the surface of the insulating film on the semiconductor substrate such as a wafer) 1.

FIG. 2 is a sectional structural view of the chuck 2. 8
Is a substrate holder that prevents the workpiece 1 from coming off the support 3 during polishing. Reference numeral 9 is a contour curve of the surface shape of the chuck 2. An inflection point 10 exists on the contour curve 9 of the chuck 2. FIG. 3 is a diagram for explaining the relationship between the distribution of the polishing amount and the contour curve 9 of the chuck 2. FIG.
(A) is a polishing amount distribution of the insulating film when the insulating film on the wafer is polished using the chuck 2 having a flat support surface having a flatness of 0.2 μm or less. Here, the polishing amount Z in the wafer surface is expressed by a function of the radius r as shown in the following (Equation 1). Z = f (r) (Equation 1) Here, the maximum value of the polishing amount Z = f (r) on the wafer surface is Zmax, the minimum value is Zmin, and the polishing amount Z = f
When the average value of (r) is Zave, the polishing amount deviation D is
It is expressed by the following equation (2). D = (Zmax-Zmin) / Zave (Equation 2) In order to eliminate this polishing amount deviation D, it is necessary to increase the polishing pressure in the portion where the polishing amount is small. When the wafer is polished with the polishing pressure P, the pressure P is applied to the support 3 and the support 3 is deformed. When the amount of deformation at this time is δ, the elastic modulus K of the support 3 is expressed by the following (Equation 3). K = δ / P (Equation 3) Therefore, the amount of deformation of the support 3 of the convex portion during polishing is formed by forming a curved portion or an uneven shape on the supporting surface of the chuck 2 to form a convex portion. Is increased, the polishing pressure is increased, and as a result, the polishing pressure distribution can be controlled, and a substantially uniform polishing amount can be obtained from the inner circumference to the outer circumference. That is, the polishing amount deviation D can be almost eliminated.

FIG. 3 (b) is a view for explaining the curved surface shape or the uneven shape formed on the support surface of the chuck 2 according to the present invention. Here, the height H of the contour curve of the curved surface shape or the concavo-convex shape formed on the support surface of the chuck 2 is expressed by a function of the radius r as shown in the following equation (4). H = g (r) (Equation 4) And the maximum value Hmax in the contour curve 9 of the chuck 2
And the minimum value Hmin is ΔH, ΔH is the product of the elastic modulus K of the support 3, the polishing pressure P, and the polishing amount deviation D, and is therefore expressed by the following equation (5). ΔH = (Hmax−Hmin) = K · P · D (Equation 5) Therefore, in order to obtain a substantially uniform polishing amount from the inner circumference to the outer circumference, the polishing quantity Z = f (shown in FIG. 3A) From the relationship of r), the height H of the contour curve 9 of the chuck 2 at the radius r can be calculated from the relationship of the following (Equation 6). However, the expression (6) is calculated as (f (r) -Z) at the outermost periphery of the wafer.
Since (min) becomes 0, H shows an infinite extremum, and it is necessary to correct it. As described above, the chuck 2 supporting the workpiece 1 based on the deviation D of the polishing amount distribution.
Since the polishing amount distribution can be controlled by correcting the shape of the supporting surface, it is possible to make the polishing pressure distribution on the workpiece (substrate) 1 uniform and the polishing amount uniform. H = −α · ΔH · f (r) / (f (r) -Zmin) (Equation 6) where α is a correction coefficient experimentally obtained.

As described above, in the polishing amount Z = f (r) shown in FIG. 3A, since the center of the wafer is symmetrical and has an inflection point, the curved surface formed on the support surface of the chuck 2 is curved. Even in the shape or the uneven shape, the center of the chuck 2 is symmetrical and has an inflection point. In any case, by forming the supporting surface of the chuck 2 into a curved surface shape or an uneven shape, the polishing pressure distribution from the inner circumference to the outer circumference of the wafer (substrate) is controlled to obtain a substantially uniform polishing amount. For example, the surface of the insulating film on the wafer can be flattened by chemical / mechanical polishing. In the above-described embodiment, as shown in FIG. 2, the surface of the rigid body portion of the chuck 2 is formed into a curved surface shape or an uneven shape, and the support body 3 made of an elastic body having a uniform thickness is attached and attached to the surface. However, even if the surface of the rigid portion of the chuck 2 is made flat and the thickness of the support 3 is changed from the inner circumference to the outer circumference of the chuck 2, the polishing pressure distribution is theoretically shown. Can be controlled. However, the support 3 needs to be replaced when it is used to some extent. Further, since it is usually difficult to manufacture by changing the thickness of the support body 3 which is an elastic body with high precision, it is better to form the surface of the rigid body portion of the chuck 2 into a curved surface shape or an uneven shape for manufacturing. However, it is also excellent in that high precision is required.

As described above, the workpiece (substrate) 1
By forming the supporting surface of the chuck 2 into a curved surface shape or a concavo-convex shape so that the polishing pressure distribution from the inner periphery to the outer periphery of the workpiece can be controlled, the workpiece 1 becomes an insulating film (for example, plasma TEOS) on the semiconductor substrate. Membrane etc.),
While supplying the polishing liquid 6 onto the rotating polishing pad 5, the insulating film on the semiconductor substrate supported by the chuck 2 is brought into contact with the polishing pad 5, and a polishing load is applied to the rotating chuck 2 by a motor to move the arrow 11 When the polishing machine surface plate 4 is reciprocally moved relative to the polishing machine surface plate 4 in the radial direction, the surface of the insulating film chemically reacts with the alkaline solution contained in the polishing solution 6. While the reaction is being performed, mechanical polishing is performed with the abrasive grains such as SiO ₂ contained in the polishing liquid 6 to progress the chemical / mechanical polishing process, and the fine irregularities are flattened to 0.01 μm or less. Thus, it is possible to obtain an interlayer insulating film having a desired film thickness with a variation in polishing amount of ± 5% or less. In addition, the chemical
In the case of mechanical polishing, the polishing liquid 6 may be colloidal silica obtained by adding SiO ₂ abrasive grains to a solution containing alkali, or one containing abrasive grains such as alumina or cerium oxide in a solution containing acid. Used.

[0015]

EXAMPLES Next, a plasma TEOS film (1.
The case of application to an interlayer insulating film formed of 5 μm deposition) will be described. The main chemical / mechanical polishing conditions are: polishing pressure: 30-40 kPa, polishing liquid 6: colloidal silica made of an alkaline solution (particle size: about 30 nm), polishing pad 5: hard polyurethane foam (hardness: about 60 degrees). ) The thickness is 0.95 mm, the support 3 of the semiconductor substrate has a thickness of about 0.5 mm formed on the surface of the chuck, and the elastic modulus K is about 1 μm /
A kPa suede type elastic body was used. FIG.
In (b), the height of the convex portion at the center of the chuck 2 is set to about 1 μm.
m, and the height of the convex portion on the outer peripheral portion of the chuck 2 was set to about 2 μm. The following (Table 1) shows the surface of the chuck 2 according to the present invention and the comparative example in the case where the polishing pressure distribution is not controlled in the chemical / mechanical polishing process for the interlayer insulating film. An example in which an insulating film thickness after polishing and variation in the polishing amount are compared with the example in which the polishing pressure distribution is formed and controlled.

[0016]

[Table 1]

The chemical / mechanical polishing characteristics were evaluated by the variation in the polishing amount of the insulating film after polishing. For the evaluation, the thickness of the insulating film was measured at 49 points in the plane of the semiconductor substrate (wafer) using a light interference type thin film thickness meter. Then, when the maximum value of the thickness of the insulating film is Tmax, the minimum value is Tmin, and the average value is Tave, the film thickness variation V is calculated from the following (Equation 7). V = ± 100 (Tmax−Tmin) / 2Tave (Equation 7) In (Table 1), Comparative 1 is an experimental result as a comparative example using a chuck having a surface flatness of 0.2 μm, Comparatives 2 and 3. Shows the experimental result as a comparative example using a chuck whose surface is a curved surface of 2 μm convex and 5 μm convex, respectively.
Comparisons 1, 2, and 3 show residual film thicknesses of 0.52 μm and 0.48 μm for the plasma TEOS film (deposited to 1.5 μm).
When chemical / mechanical polishing processing is performed up to 0.5 μm, the variation in the polishing amount is ± 10%, ± 8%, and ± 7%.

In Table 1, Examples 1 to 3 show experimental results as Examples in which the surface of the chuck according to the present invention is formed into a curved surface shape or an uneven shape to control the polishing pressure distribution. Example 1 is a case where the surface shape of the chuck is poor and the control of the polishing pressure distribution is also poor, and Examples 2 and 3 are cases where the surface shape of the chuck is good and the control of the polishing pressure distribution is good. In Example 1, the control of the polishing pressure distribution was poor, and when the plasma TEOS film (1.5 μm deposited) was chemically and mechanically polished to a residual film thickness of 0.5 μm, the amount of polishing varied. Was ± 5%. In Examples 2 and 3, the control of polishing pressure distribution was good, and plasma TE
The residual film thickness is 0.52 with respect to the OS film (1.5 μm deposition)
When chemical / mechanical polishing is performed up to μm and 0.47 μm, the variation in polishing amount is ± 5% or less ± 2%,
It was ± 3%.

As can be seen from the results of these experiments (Table 1), as compared with the comparative example, the surface of the chuck was formed into a curved surface shape or an uneven shape as in the present invention, and the polishing pressure distribution was controlled to control the interlayer pressure. It was confirmed that the effect of reducing the variation in the thickness of the insulating film was obtained.
Further, as in the present invention, the surface of the chuck is formed into a curved surface shape or a concavo-convex shape to control the polishing pressure distribution so that the step of 1 μm existing on the surface of the insulating film before polishing is reduced to 0.1 μm or less after polishing. I was able to. This value is
It is a value that enables formation of a wiring having a wiring width of 0.25 μm or less on this interlayer insulating film. Next, a semiconductor device having a two-layer aluminum wiring structure on a 6-inch silicon substrate was manufactured by applying a chemical / mechanical polishing method of controlling the polishing pressure distribution according to the present invention. An example will be described with reference to FIG.

That is, 41 is a step of forming a first layer of aluminum wiring after forming a semiconductor element on a semiconductor substrate (6 inch silicon substrate). 42 is a step of depositing (depositing) a plasma TEOS film (interlayer insulating film) on the first-layer aluminum wiring formed in step 41 by CVD to a thickness of about 1.7 μm. Reference numeral 43 denotes the surface of the plasma TEOS film having a thickness of 1.7 μm formed in step 42,
As described in the embodiments of the present invention, in the step of forming the surface of the chuck into a curved surface shape or an uneven shape and controlling the polishing pressure distribution to perform chemical / mechanical polishing processing to planarize the surface. is there. As a result of the polishing process of 1.2 μm in this step 43, the thickness distribution of the plasma TEOS film was measured by using an optical interference type thin film thickness measuring device.
It was confirmed that it was 5 μm ± 0.02 μm (the variation of the film thickness was ± 4%). At this time, 1 μm existing on the surface of the plasma TEOS film after the plasma TEOS film was deposited.
A step difference measuring device of a stylus type and a SEM observation of the cross section of the wafer are performed for the step difference of 1 .mu.m.
It was confirmed that the thickness was reduced to 1 μm or less. Further, the surface roughness of the polished plasma TEOS film was measured using a contact-type surface roughness measuring device and an atomic force microscope to obtain a plasma T
The surface roughness of the EOS film is 0.2 to 0.3 nm Rmax
Was confirmed.

Reference numeral 44 shows a SiO ₂ film having a thickness of 0.1 μm deposited on the surface of the polished plasma TEOS film by CVD (deposition).
This is the step of performing Step 45 is a step of forming a contact hole for electrical connection with the lower aluminum wiring in the SiO ₂ film deposited in step 44 by etching. Step 46 is a step of forming a contact via of a conductor made of tungsten or the like on the surface of the SiO ₂ film formed in step 45. Step 47 is a step of forming aluminum upper layer wiring having a width of 0.25 μm on the surface of the SiO ₂ film formed in step 44. By the steps 41 to 47 described above, a semiconductor device having a two-layer aluminum wiring structure can be manufactured on a 6-inch silicon substrate. As described above, the semiconductor device was manufactured and the contact via resistance and the wiring resistance were measured. As a result, it was found that there was no contact resistance failure and no wiring failure, and a highly reliable semiconductor device could be manufactured.

Next, an example of manufacturing a semiconductor device having a two-layer wiring structure on a semiconductor substrate by applying the chemical / mechanical polishing method according to the present invention by controlling the polishing pressure distribution , FIG. 5 will be described. That is, 51 is a step of forming a lower layer wiring on the semiconductor substrate. 52 is, for example, plasma TEO on the lower layer wiring formed in step 51.
This is a step of depositing (forming) an S film by CVD to a thickness of about 1.7 μm. Reference numeral 53 denotes a plasma TEOS film (interlayer insulating film) having a thickness of, for example, 1.7 μm formed in the step 52.
The surface of, as described in the embodiment of the present invention,
In this step, the surface of the chuck is formed into a curved surface shape or a concavo-convex shape, the polishing pressure distribution is controlled, and chemical / mechanical polishing processing is performed to flatten the surface. 1 μm in this step 53
As a result of polishing, the thickness was 0.5 μm ± 0.02 μm (the variation in the film thickness was ± 4, similar to the example shown in FIG.
%), The unevenness of the film thickness can be controlled to ± 5% or less, and the level difference (fine irregularities) can be reduced to 0.1 μm or less for planarization. The surface roughness of the plasma TEOS film can be 0.2 to 0.3 nm Rmax.

Step 54 is a step of forming a contact hole for electrically connecting the lower layer wiring to the plasma TEOS film whose surface is flattened in step 53 and polished to a desired thickness. Step 55 is a step of forming a contact stud of a conductor made of tungsten or the like by selective CVD in the contact hole formed in the step 54. Step 56 is a step similar to step 43 in which the polishing pressure distribution is controlled to carry out chemical / mechanical polishing to remove the metal film such as tungsten grown on the surface. 57 is a step of forming an upper wiring on the surface of the plasma TEOS film (interlayer insulating film). Step 51 described above
Through 57, it is possible to manufacture a semiconductor device having a multilayer wiring structure on a semiconductor substrate. As a result of manufacturing the semiconductor device and measuring the contact stud resistance and the wiring resistance as described above, it is found that there is no contact resistance defect or wiring defect, and a highly reliable semiconductor device can be manufactured. Further, the present invention can be applied to manufacture a thin film multilayer wiring board.

[0024]

According to the present invention, in chemical / mechanical polishing, the support surface (surface) of the chuck is formed into a curved surface shape or an uneven shape to control the polishing pressure distribution in the substrate surface. Uniform thickness of insulating film and metal film,
Moreover, since it can be processed flatly (for example, the variation of the film thickness is ± 5% or less and the fine unevenness is 0.2 μm or less), the semiconductor device can be highly reliable and highly integrated.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a chemical / mechanical polishing apparatus according to the present invention.

FIG. 2 is a diagram showing a sectional structure of a chuck according to the present invention.

FIG. 3 is a diagram for explaining a relationship between a distribution of a polishing amount and a contour curve of a chuck according to the present invention.

FIG. 4 is a diagram showing a process flow of an example for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a diagram showing a process flow of another embodiment for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

1 ... Workpiece (substrate: wafer), 2 ... Chuck, 3 ... Support, 4 ... Polishing machine surface plate 5 ... Polishing pad, 6 ... Polishing liquid, 7 ... Polishing load, 8 ... Substrate pressing 9 ... Chuck surface Contour curve of shape, 10 ... Inflection point

Claims (10)

[Claims] 1. A chemical / mechanical polishing method for controlling a polishing pressure according to a shape of a supporting surface of a chuck for supporting a substrate to perform a chemical / mechanical polishing process on the surface of the substrate. Polishing method. 2. A chemical method characterized in that a polishing pressure is controlled by a curved surface shape or a concave-convex shape of a support surface of a chuck for supporting a substrate to perform a chemical / mechanical polishing process on the surface of the substrate. -Mechanical polishing method. 3. A chemical / mechanical polishing process is performed on the surface of the insulating film on the substrate by controlling the polishing pressure by the curved shape or uneven shape of the support surface of a chuck that supports the substrate having the insulating film surface. A chemical / mechanical polishing method characterized by being performed. 4. A chemical / mechanical polishing process is performed on the surface of the metal film on the substrate by controlling the polishing pressure by the curved shape or the uneven shape of the support surface of the chuck that supports the substrate having the metal film surface. A chemical / mechanical polishing method characterized by being performed. 5. A polishing amount is controlled by controlling a curved surface shape or an uneven shape of a support surface of a chuck for supporting a substrate having an insulating film surface, so that the variation of the polishing amount of the insulating film surface on the substrate is ±.
A chemical / mechanical polishing method comprising: performing a chemical / mechanical polishing process with an unevenness of the insulating film surface of 5% or less to 0.2 μm or less. 6. An interlayer insulating film forming step of forming an interlayer insulating film on a lower layer wiring on a substrate, and a curved surface shape of a support surface of a chuck for supporting the substrate on which the interlayer insulating film is formed in the interlayer insulating film forming step or A chemical / mechanical polishing process for controlling the polishing pressure by the uneven shape to perform a chemical / mechanical polishing process on the surface of the interlayer insulating film of the substrate to planarize the surface; and the chemical / mechanical polishing process. And a step of forming a desired upper layer wiring on the interlayer insulating film flattened by another polishing process, the method for manufacturing a semiconductor substrate. 7. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a curved surface shape of a support surface of a chuck for supporting the substrate on which the interlayer insulating film is formed in the interlayer insulating film forming step or A chemical / mechanical polishing process for controlling the polishing pressure by the uneven shape to perform a chemical / mechanical polishing process on the surface of the interlayer insulating film of the substrate to planarize the surface; and the chemical / mechanical polishing process. Contact hole forming step of forming a contact hole in the interlayer insulating film flattened by various polishing processing steps, and a contact stud forming a contact stud by embedding a conductive material in the contact hole formed in the contact hole forming step And a step of forming a desired upper layer wiring on the interlayer insulating film after the contact stud forming step. Method for manufacturing a semiconductor substrate. 8. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a curved surface shape of a support surface of a chuck for supporting the substrate on which the interlayer insulating film is formed in the interlayer insulating film forming step or A chemical / mechanical polishing process for controlling the polishing pressure by the uneven shape to perform a chemical / mechanical polishing process on the surface of the interlayer insulating film of the substrate to planarize the surface; and the chemical / mechanical polishing process. and the SiO ₂ film forming step of forming a SiO ₂ film by CVD to Do polishing step at planarized interlayer insulating film, the upper layer to form the upper wiring on the SiO ₂ film forming step SiO ₂ film formed by A method of manufacturing a semiconductor substrate, comprising: a wiring forming step. 9. A chuck for supporting a substrate on a support surface formed in a curved shape or an uneven shape so that the polishing pressure is controlled, and the surface of the substrate is subjected to chemical / mechanical polishing processing. A chemical / mechanical polishing device characterized in that 10. The chemical / mechanical polishing apparatus according to claim 9, wherein the difference in height between the convex portion and the concave portion of the chuck support surface is 0.5 μm to 10 μm.