JPH09172187A - Junction field effect semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Leakage current of a SiC field effect semiconductor device is reduced and reliability is improved. A main surface of a semiconductor device is parallel to a {0001} plane or a plane equivalent to the {0001} plane, and a sidewall surface of a groove in which a pn junction is formed is a {1-100} plane or a plane equivalent thereto. Configure to be parallel. [Effect] Since the polytypes of the crystals on the pn junction surface of the groove match, defects that cause a leak current are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction field effect semiconductor device using silicon carbide as a semiconductor material and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, operating voltage is from several tens of volts to several hundreds.
In a so-called power semiconductor device such as a transistor or a thyristor or a power IC, which has an operating current in the range of 0 V and ranges from several hundred mA to several hundred A or more, mainly silicon (Si) or gallium arsenide (GaAs) is used. Single crystal wafers are used.

By the way, in recent years, with the progress of speed control technology for railway vehicles that are becoming faster and high-voltage power transmission technology between a power plant and a substation, etc., there has been a demand for power semiconductor devices used in these techniques. The values of operating voltage and operating current are increasing. Moreover, the operating frequency also tends to increase. Also, regarding power ICs, the operating environment conditions when they are used in automobiles, industrial robots, etc. are becoming stricter, and with respect to operation under high temperature environment and operation under radiation irradiation environment, etc. , High reliability is required.

In order to meet such various requests, S
In a semiconductor device using a single crystal wafer of i or GaAs, the structure of the semiconductor device is being actively improved, and in particular, the increase in voltage and the increase in current are handled by increasing the size of the semiconductor device. However, a problem that a cooling device that dissipates heat generated when a large semiconductor device operates increases in size is becoming apparent. On the other hand, with respect to the increase in operating frequency of semiconductor elements, the limit of improvement in characteristics is beginning to be seen from the fundamental physical properties of semiconductor materials.

In order to overcome such a problem, in recent years, a single crystal of silicon carbide (SiC) having a large energy band gap has attracted attention as a constituent material of a semiconductor device. This SiC has an energy bandgap and a dielectric breakdown electric field several times larger than those of Si, and even a small semiconductor device can operate with a high voltage and a large current. Further, in principle, the operable temperature may be higher than Si by several hundreds of degrees Celsius or more. And
The semiconductor device made of SiC may have a high frequency characteristic sufficiently higher than that of the semiconductor device made of Si even in a high voltage operation and a large current operation. Although there are cubic and hexagonal SiC single crystals similar to Si and GaAs, hexagonal crystals are more excellent in characteristics such as band gap and dielectric breakdown electric field.

However, it has been very difficult to manufacture a single crystal of SiC having a purity and a size required for forming a semiconductor device. For this reason, research and development of power semiconductor devices using SiC have not been advanced so much.

On the other hand, only recently, a SiC single crystal having a relatively high purity necessary for forming a semiconductor device and having a sufficient size can be produced with relatively high efficiency. The technology that can be developed has been developed, and the development of a semiconductor device using SiC as a material has been rapidly advanced. As an example, the MOSFET disclosed in JP-A-4-239778 can be cited.

FIG. 7 is a sectional view of a conventional MOSFET formed of a SiC single crystal.

In a semiconductor substrate made of SiC single crystal, an n + type layer 51 having a low resistivity, an n− type drain layer 52 having a high resistivity, and a p type well layer 53 are laminated in this order. n is formed on a part of the surface of the p-type well layer 53.
The mold source layer 54 is formed. In the portion where the n-type source layer 54 is formed, an elongated groove portion 56 that is cut in a substantially vertical direction so as to reach the n − -type drain layer 52 from the n-type source layer 54 through the p-type well layer 53 is formed. ing. An insulating film 55 is provided in the groove 56 so as to cover the exposed surface thereof, and a gate electrode 59 is arranged on the upper surface of the insulating film 55. The drain electrode 57 is ohmic-bonded to the open surface of the n + type layer 51, and the source electrode 58 is ohmic-bonded to the open surface of the p-type well layer 53 and a part of the surface of the n-type source layer 54.

[0010]

SUMMARY OF THE INVENTION However, SiC
The conventional field effect transistor using is not fully utilized the advantage of SiC. It is for the following reasons.

Since the conventional field effect transistor is a MOS type, a channel is formed near the interface between the p type well region and the insulating film. The insulating film formed on SiC is generally silicon dioxide by thermal oxidation, but unlike Si, the formation mechanism of silicon dioxide by thermal oxidation on SiC is complicated, and the interface between SiC and silicon dioxide is complicated. A large number of defects are formed in. Therefore, the carriers passing through the channel formed near this interface are scattered by this defect, and the mobility thereof is significantly reduced as compared with the original value of SiC. This increases the on resistance of the MOSFET. Therefore, SiC that theoretically shows excellent device characteristics
However, since the characteristics of the interface are poor, it has not been able to fully utilize its advantages.

[0012]

The present invention is first characterized by a junction type field effect semiconductor device using a hexagonal silicon carbide single crystal as a semiconductor material. With the junction type, since the controlled current path is not near the interface between the gate layer and the insulating film, the characteristics of the interface are essentially unaffected and the original characteristics of the SiC material are easily reflected.

Further, a specific structural feature of the junction field effect semiconductor device of the present invention is that the {0001} plane of a hexagonal silicon carbide single crystal or a plane equivalent thereto is used as a main surface, and That is, the groove is formed, and the side wall of the groove is parallel to the crystallographic plane index {1-100} plane of the silicon carbide single crystal or a plane equivalent thereto. Where "-1" in the index
Has the same meaning as the conventional notation in which "-" is added above "1".

When the main surface is made of {0001} or its equivalent surface and the side wall of the groove is made parallel to the {1-100} surface or its equivalent surface, the pn junction surface formed on the side wall of the groove is formed. The stacking faults due to the difference in the growth polytype and the microscopic protrusions generated during the formation of the groove are reduced. Therefore, the breakdown voltage is prevented from lowering when a reverse voltage is applied to the pn junction, and the breakdown voltage of the semiconductor device is improved. Further, the method for manufacturing the junction field effect semiconductor device of the present invention has the following steps.

A step of preparing an n-type conductivity type high impurity concentration hexagonal silicon carbide single crystal wafer having a {0001} plane or a plane equivalent thereto as a main surface; Forming an n-type conductivity type silicon carbide drain layer on the surface by epitaxial growth; forming a plurality of n-type conductivity type source layers on the surface of the drain layer by ion implantation; forming the source layer Forming a groove portion whose side wall is perpendicular to the surface of the drain layer and whose crystal plane is parallel to the {1-100} plane or a plane equivalent thereto, in the portion; Thus forming a p-type conductivity type silicon carbide layer by epitaxial growth.

According to this manufacturing method, the main surface is covered with {000
1) plane or a plane equivalent to this plane is used, and a groove is formed on the surface so that the side wall is parallel to the {1-100} plane or a plane equivalent thereto. As a result, a difference in growth polytype is unlikely to occur at the pn junction surface formed on the sidewall of the groove. Therefore, stacking faults and microscopic protrusions are reduced, so that the breakdown voltage of the pn junction is prevented from lowering and the breakdown voltage of the semiconductor device is improved.

The present invention can be applied to various junction field effect semiconductor devices such as field effect transistors, field effect thyristors, static induction thyristors, and static induction thyristors, as long as the semiconductor device has a pn junction on the side wall of the groove. Effective against Further, the sidewall is not limited to the pn junction, and may be, for example, a Schottky junction.

[0018]

1 is a sectional view of a junction field effect transistor embodying the present invention. In this embodiment, hexagonal SiC is used as a semiconductor material. An n-type (n-type) drain layer 12 having a higher resistivity than this layer is provided in contact with an n-type (n + type) layer 11 having a low resistivity. On the source side, the groove 16 is formed and the semiconductor surface has irregularities. N is lower in resistivity than the drain layer 12 in the top planar region of the protrusion (hereinafter referred to as the main surface 20).
A mold source layer 14 is provided. The p-type layer 13 is provided on the side wall 21 of the concave portion, that is, the groove portion 16, and on the bottom portion of the groove portion 16. Here, the n-type source layer 14 and the p-type layer 13 are not in direct contact with each other because the drain layer 12 is interposed therebetween. The drain electrode 17 makes ohmic contact with the n + type layer 11, and the source electrode 18 makes ohmic contact with the n type source layer 14. Furthermore, at the bottom of the groove 16, the gate electrode 19 makes ohmic contact with the p-type layer 13. In addition, on the main surface 20, the drain layer 12
An oxide film 15 is provided between the surface of the p-type layer 13 and the source electrode 18. As a result, the source electrode 18 and p
The mold layer 13 is insulated.

In this embodiment, when a predetermined positive operating voltage is supplied to the drain electrode 17, the gate electrode 19 is turned on unless a voltage is applied. Gate electrode 19
When a negative gate voltage is applied to the gate, a reverse voltage is applied to the pn junction formed by the p-type layer 13 and the drain layer 12 in parallel with the sidewall 21 of the groove, and the depletion layer expands to expand the source electrode and the drain. The drain current flowing between the electrodes is limited. Then, under a sufficiently large gate voltage, this embodiment is turned off.

2A, 2B and 2C are hexagonal silicon carbides.
{0001}, {1 in the unit cell of (SiC) single crystal
It is a structure explanatory view showing each crystal plane of -100} and {11-20}.

In FIG. 2, they are in the same plane and are 1
In the vectors a ₁ , a ₂ and a ₃ that intersect at 20 degrees, a
₁ is the <1000> direction axis of the unit cell, a ₂ is the <010> axis
0> direction axis, a ₃ is the <0010> direction axis, and <1000> direction axis a ₁ , <0100> direction axis a ₂ ,
The vertical axis extending in the direction perpendicular to each of the <0010> direction axes a ₃ is the c axis.

Then, as indicated by the diagonal lines in FIG.
The <1000> direction axis a ₁ , the <0100> direction axis a ₂ ,
A plane parallel to each <0010> direction axis a ₃ , that is, c
The plane whose axis is the vertical line is the {0001} plane. In addition, the hatched surfaces in FIGS. 2B and 2C are {1
-100} plane and {11-20} plane.

In the embodiment shown in FIG. 1, the source layer 14 is formed by ion implantation and the p-type layer 13 is formed by epitaxial growth. At that time, the main surface 20 has a {0001} crystal plane of hexagonal SiC, and the groove portion 16 has a side crystal plane of {1-}.
100 plane. It is for the following reasons.

When the p-type layer 13 is formed by epitaxial growth, the p-type layer 13 needs to have the same polytype as the drain layer 12. This is because when different polytypes are used, structural defects occur at the interface, that is, at the pn junction surface, and a large leak current occurs when a reverse voltage is applied to this pn junction.

Polytype in SiC is {000
It depends on the difference in the stacking order in the <0001> direction of the atomic plane parallel to the 1} plane. There are three kinds of atomic arrangements in the atomic plane parallel to the {0001} plane. Therefore, if these are distinguished from A, B, and C, the polytype of SiC is this A in the stack in the <0001> direction. , B, C permutations. For example, 6H
-SiC is ACBABC ..., 4H-SiC is ACBC ...
It is expressed as

Generally, in epitaxial growth, the atomic arrangement of the growth layer strongly depends on the atomic arrangement of the underlying layer. Therefore, the p-type layer 13 epitaxially grown on the surface of the drain layer 12
In order to make the polytype of the same as the drain layer 12,
The crystal orientation of the surface of the drain layer 12 in contact with the p-type layer 13 is preferably a crystal surface in which the permutation of the atomic layers such as A, B, and C described above appears clearly. For that purpose, the main surface 20 is {0
It is better to make the 001} plane.

As described above, since the side wall surface and the bottom surface of the groove portion 16 are joint surfaces of the pn junction, they must be as flat as possible. Usually, a method such as a reactive ion etching method is used to form the groove portion 16, but the flatness of the etching surface is achieved by optimizing the etching conditions in macroscopic terms, but the crystallographic surface is microscopically determined. Strongly depends on.

The {0001} plane of hexagonal SiC, that is, FIG.
The atomic arrangement of SiC viewed from the direction of the main surface 20 of is shown in FIG. In FIG. 3, the atoms 31 to be etched are shown by colored circles, the remaining atoms 32 are shown by white circles, and the side wall 33 of the groove portion 16 in macro view is shown by a broken line.
FIG. 3 (a) shows a plane parallel to the 0} plane. In this case, since the direction of the side wall surface coincides with the direction of the dense arrangement of atoms, the etching surface is flat when viewed microscopically.

On the other hand, the side wall is a plane other than the {1-100} plane,
For example, FIG. 3 (b) shows one that is parallel to the {11-20} plane. In this case, since the direction of the side wall surface does not coincide with the direction of the dense arrangement of atoms, etching is performed along the direction of the dense arrangement of atoms even if it is flat in the macro, even if it is flat in the macro. The etching surface is a zigzag surface as shown in FIG. In that case,
The interface with the p-type layer 13 (pn junction surface) also becomes zigzag, so that when a reverse voltage is applied, the electric field may concentrate on the protruding portion and cause breakdown. Therefore, such inconvenience causes the side wall 21 of the groove portion 16 to have a length of {1-
This can be prevented by making it parallel to the 100} plane.

When the drain layer 12 is formed by epitaxial growth on the n + type layer 11 having the {0001} plane orientation, in order to obtain a good epitaxial growth film without defects, the main surface of the n + type layer is It is effective to tilt in the <11-20> direction about 6 degrees from the {0001} plane. Even in that case, the actual main surface of the crystal has a structure in which steps having the {0001} plane as the surface direction are arranged in a stepwise manner in the <11-20> direction. Moreover, since the stepwise surface and the {1-100} plane have a vertical positional relationship, the main surface can be changed from the {0001} plane to the <11-2 plane.
There is no problem even if it is tilted a few degrees in the 0> direction.

FIG. 4 is a diagram showing the structure of a junction field effect transistor which is another embodiment of the present invention, in which (a)
Is a plan view, and (b) is a perspective view showing a cross-sectional configuration as seen from the line AA '. In this figure, the portions corresponding to or corresponding to those in FIG.

In the present embodiment, the main surface 20 is configured to coincide with the {0001} plane of the hexagonal SiC single crystal. Furthermore, in the groove portion 16, the crystal orientation of the entire side wall surface is {1-100} of hexagonal SiC single crystal.
Selected to match the face. Therefore, as described above, the pn junction surface composed of the p-type layer 13 and the drain layer 12 is flat even on a microscopic scale, so that a local electric field is applied when a reverse voltage is applied to this pn junction. Concentration does not occur. Therefore, the leakage current between the source and the drain at the time of turning off is significantly reduced.

FIGS. 5A to 5F are sectional views showing an example of the manufacturing process of the embodiment shown in FIG. In the figure, the same components as those shown in FIG. 4 are designated by the same reference numerals.

First, as shown in FIG. 5A, the n + type layer 11 has a low resistivity of the n + type and has a crystal plane orientation {0.
Hexagonal S cut out so that 001} becomes the main surface 20
An iC single crystal wafer is prepared. This single crystal wafer (n
On the main surface 20 side of the + type layer 11), hydrogen is used as a carrier gas and silane and propane are used as source gases, and n-type having a desired resistivity and thickness is formed by epitaxial growth while adding an n-type impurity gas. The drain layer 12 is formed.

Next, as shown in FIG. 5B, the surface of the drain layer 12 is partially oxidized to form an oxide film 15.
Using this oxide film as a mask, n-type impurity ions are implanted to partially form the n-type source layer 14.

Next, as shown in FIG. 5C, the main surface 2
Oxide film is formed on the entire surface of the drain layer 12 and the groove portion 1 on the surface of the drain layer 12 is formed.
A window is opened by removing the oxide film by photolithography at the place where 6 is to be formed. At that time, the side wall of the groove is hexagonal S
The oxide film is patterned so as to match the {1-100} plane of iC. Specifically, the plane pattern as shown in FIG.

Next, as shown in FIG. 5D, the main surface 2 is formed by reactive ion etching using the oxide film as a mask.
The groove 16 is formed perpendicular to 0. Due to the patterning of the oxide film in the previous step, the side wall of the groove 16 is made of hexagonal Si.
It matches the {1-100} plane of C.

Next, as shown in FIG. 5E, the groove 16
Hydrogen is used as a carrier gas and silane and propane are used as raw material gases on the inner wall of the substrate to epitaxially grow while adding a p-type impurity gas to form a p-type layer 13.

Further, as shown in FIG. 5F, the oxide film covering the n-type source layer 14 is etched to form a source electrode 18 made of a metal film on the n-type source layer 14. At the same time, the source electrode 19 made of a metal film is formed on the bottom surface of the groove 16. On the other hand, the drain electrode 17 made of a metal film is formed on the other open surface of the single crystal wafer.

FIG. 6 is a plan view showing the structure of a field effect transistor which is another embodiment of the present invention. 6, the same components as those shown in FIG. 1 are designated by the same reference numerals. Main surface 21 of each transistor
Is formed so as to coincide with the {0001} plane of a hexagonal SiC single crystal.
6 are provided. These groove portions 16 are (a) elongated hexagonal groove portions as viewed from above,
(b) A trapezoidal groove portion and (c) a parallelogram-shaped groove portion. In addition, the sidewalls of these grooves are all formed in a direction coinciding with the {1-100} plane of the hexagonal SiC single crystal.

Also in these embodiments, similarly to the embodiments of FIGS. 1 and 4, in the pn junction parallel to the side wall surface 21 of the groove portion 16, the difference between the polytypes of SiC forming the p layer and the n layer is different. Does not occur and stacking faults do not occur. Further, the pn junction interface is flat even when viewed on a micro scale. Therefore, electric field concentration does not occur even when a reverse voltage is applied to the pn junction, so that the leakage current between the source and the drain at the time of off can be significantly reduced.

Each crystal face in each embodiment may be a face having an index different from the above-mentioned index as long as it is a crystallographically equivalent face.

[0043]

According to the present invention, the leak current of a field effect transistor made of a single crystal of hexagonal silicon carbide can be significantly reduced, and the reliability can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a junction field effect transistor embodying the present invention.

FIG. 2 is a structural explanatory diagram showing {0001}, {1-100}, and {11-20} crystal faces in a unit cell of a single crystal of hexagonal silicon carbide (SiC).

3 is a diagram showing the {0001} plane of hexagonal SiC, that is, the atomic arrangement of SiC as seen from the direction of main surface 20 in FIG. 1. FIG.

FIG. 4 is a diagram showing a configuration of a junction field effect transistor which is another embodiment of the present invention, in which (a) is a plan view,
(B) is a perspective view showing a cross-sectional configuration as seen from the line AA '.

FIG. 5 is a cross-sectional view showing an example of a manufacturing process of the embodiment shown in FIG.

FIG. 6 is a plan view showing the configuration of a field effect transistor which is another embodiment of the present invention.

FIG. 7: Conventional MOSF formed of SiC single crystal
It is sectional drawing of ET.

[Explanation of symbols]

11 ... N + type layer, 12 ... Drain layer, 13 ... P type layer, 1
4 ... N-type source layer, 15 ... Oxide film, 16 ... Groove part, 17 ...
Drain electrode, 18 ... Source electrode, 19 ... Gate electrode,
20 ... Main surface of semiconductor substrate, 21 ... Side wall of groove.

Front Page Continuation (72) Inventor Tsutomu Yao 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (3)

[Claims] 1. A {0001} plane of a hexagonal silicon carbide single crystal or a plane equivalent thereto is used as a main surface, a groove is formed in this main surface, and the side wall of the groove is a crystallographic plane of the silicon carbide single crystal. A junction-type field effect semiconductor device, which is parallel to an index {1-100} plane or a plane equivalent thereto. 2. The junction field effect semiconductor device according to claim 1, wherein a pn junction is formed in parallel with a side wall of the groove. 3. A method of manufacturing a junction field effect semiconductor device, which comprises the following steps (1) to (3). A step of preparing an n-type conductivity type high impurity concentration hexagonal silicon carbide single crystal wafer having a {0001} plane or a plane equivalent thereto as a main surface; A step of forming an n-type conductivity type silicon carbide drain layer by epitaxial growth; a step of forming a plurality of n-type conductivity type source layers on the surface of the drain layer by ion implantation; and a step of forming the source layer, A step of forming a groove portion whose side wall is perpendicular to the surface of the drain layer and whose crystal plane is parallel to the {1-100} plane or a plane equivalent thereto, and p so as to cover the groove portion Forming a conductive type silicon carbide layer by epitaxial growth.