JPH0917890A - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Purpose] To prevent over-erasure from occurring in flash EEPROM. [Structure] The tunnel insulating film 4 is formed on the surface of the semiconductor substrate 1 in order.
Floating gate electrode material, insulating film, control gate electrode material is deposited, these tunnel insulating film 4, floating gate electrode material,
After the floating gate electrode 5 and the control gate electrode 6 are formed by patterning the insulating film and the control gate electrode material, the floating gate electrode material is preferentially isotropically etched by using the predetermined patterned resist as a mask. Increase the radius of curvature of the corner on the source region 2 side. Then, the resist is removed and heat treatment is performed in an oxygen atmosphere to cover the floating gate electrode 5 with the insulating film 8 and process the floating gate electrode 5 to have a corner radius of curvature of 10 nm or more. Form. As a result, the controllability of the amount of electrons in the floating gate electrode 5 can be improved, so that overerasure can be prevented and the memory retention characteristic can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device (EEP) which can be electrically written and erased.
ROM ； Erasable and Electrically Programmable Read
Only Memory).

[0002]

2. Description of the Related Art In EEPROM, (1) the stored information of the device is not lost even if the power supply is cut off (non-volatile), (2)
It has a feature that it can be electrically erased and written. For this reason, it has a wide range of uses, such as being used to store data that has changed after being incorporated into the system, including the setting of facsimile interface settings and registration of speed dials.

In addition to today's increasing capacity from 16M to 64M and 256M, the development of a memory for files for portable information terminals and sub-notebook personal computers is being accelerated.

Below, a typical structure of the EEPROM is referred to as ETOX (EPR
OM Thin Oxide) type flash EEPROM will be explained as an example.

In general, a memory is composed of memory cells which are unit circuits for storing 1-bit information. FIG.
As shown in the memory block diagram of each memory cell 10,
A bit line 11 that transfers input data and output data and a word line 12 that connects the bit line 11 and the memory cell 10 are connected, and after selecting one word line 12 by the row decoder, Writing is performed to the memory cell 10 via the bit line 11, or information in the memory cell 10 is amplified by the sense amplifier 13 via the bit line 11 and transferred to the output buffer 14 for reading.

Specifically, the memory cell array of the NOR type ETOX type flash EEPROM is as shown in FIG. 11, and the plan view of one memory cell 10 from above is as shown in FIG. 12 (a). A cross-sectional view taken along the line ab of FIG. 12 (a) is a MOSFET (Metal Oxide Semicon) having two gate structures of a floating gate and a control gate as shown in FIG. 12 (b).
ductor Field Effect Transistor).

In this example, an N ⁺ type source region 2 and a drain region 3 are formed on a P-type semiconductor substrate 1, and a channel region 9 formed between the source region 2 and the drain region 3 is formed.
A floating gate electrode 5 is formed on the tunnel insulating film 4. On the floating gate electrode 5, a composite film of Si oxide film / Si nitride film / Si oxide film (ONO film 6)
The control electrode 7 is formed via the. A post oxide film (thermal oxide film) 8 is formed around the floating gate electrode 5, the ONO film 6, and the control gate electrode 7.

FIGS. 13A to 13C are cross-sectional views showing a manufacturing process of the conventional nonvolatile semiconductor memory device described above.

The method of manufacturing the conventional nonvolatile semiconductor memory device is as follows.

(1) A tunnel insulating film is formed on the surface of the semiconductor substrate 1.
After forming the Si oxide film 4a as 4, the impurity-doped polycrystalline Si film 5a is formed. Then, on the polycrystalline Si film 5a,
Si oxide film / Si nitride film / Si oxide film are sequentially deposited to form ONO film 6
After forming, the polycrystalline Si film 7a doped with impurities is formed (FIG. 13 (a) shown).

(2) Resist that has been subjected to predetermined patterning
Using the 18 as a mask, the polycrystalline Si film 5a, the ONO film 6, the polycrystalline Si film 7a
Is anisotropically etched to form the floating gate electrode 5 and the control gate electrode 7 (shown in FIG. 13 (b)), and the resist 18 is removed.

(3) The resist 18 is removed by O ₂ plasma treatment and a mixed solution of sulfuric acid and hydrogen peroxide, and then heat-treated in an oxygen atmosphere to form an oxide film 8 and then the resist 18 covering the control gate electrode 7 is masked. Impurities are implanted into the source region 2 and the drain region 3 to form the source region 2 and the resist 18 is removed (see FIG. 13).
(c) Shown).

Here, the source region 2 and the drain region 3
The four corners in the cross section of the floating gate electrode including
The radius of curvature is 0 (radius of curvature = 0), and the radius of curvature is 10 nm or less even if it is slightly rounded by the heat treatment of (3).

In such a memory, electrons are injected into the floating gate electrode 5 to write data, and erasing is performed by extracting electrons 16 from the floating gate electrode 5. In addition, for reading, the fact that the threshold value seen from the control gate electrode 7 increases and decreases as the number of electrons in the floating gate electrode 5 increases and decreases, and when a predetermined voltage is applied to a predetermined portion of the selected memory cell, the current is '1' or '0' depending on whether it flows
Recognize

Therefore, the accurate control of the amount of electrons existing in the floating gate electrode 5 leads to the accuracy of the information stored in this memory.

[0016]

[Problems to be solved by the invention] ETOX flash EEPR
In the OM, a specific memory cell is not designated for erasing, but a batch erasing is performed by an intelligent method or the like.

FIG. 13 is a diagram showing the relationship between the threshold voltage of a memory cell seen from the word line and the number of memory cells having the threshold voltage.

From FIG. 13, it can be seen that there is a large variation in the threshold voltage among the memory cells, and it is difficult to perform batch erase under the same conditions.

Further, as presumed from this point, since the intelligent method repeats the erase operation until the erase of all memory cells is confirmed, the memory cells in which too many electrons are extracted from the floating gate electrode, that is, as shown in FIG. To
There was over-erasure in which the threshold voltage was 0 V or less. In the NOR-type connection, this over-erase causes a problem that the memory cell data on the same bit line cannot be read because the current flows even when the control gate electrode is in the non-selected state (0V).

In addition, in the NOR type connection, a high voltage is applied to a non-selected memory cell on the same word line as the selected memory cell at the time of writing or a low voltage is applied at the time of reading. There is a problem in that electrons enter the floating gate electrode and the storage state becomes inaccurate.

Therefore, it is an object of the present invention to reduce the number of erase operations at the time of batch erase, prevent the occurrence of over-erase, and suppress the deterioration of the memory retention characteristic at the time of writing and reading. .

[0022]

In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention comprises a tunnel insulating film, a floating gate electrode forming material, an insulating film,
A floating gate electrode and a control gate are formed by sequentially forming a control gate electrode forming material and anisotropically etching the control gate electrode forming material, the insulating film, and the floating gate electrode forming material using a predetermined patterned resist as a mask. After forming the electrode, a step of removing the resist, a step of forming a resist on the floating gate electrode so that one side surface of the floating gate electrode and the control gate electrode is exposed, and using the resist as a mask The exposed side surface of the floating gate electrode is isotropically etched to increase the radius of curvature of a corner portion of the end portion of the floating gate electrode that is in contact with the tunnel insulating film, and after the isotropic etching, the resist is removed. After removing the resist and heat treatment, the radius of curvature of the corner portion of the floating gate electrode is set to 10 nm. In the above steps, so as to define a channel region in the semiconductor substrate under the control gate electrode, a first impurity region on the corner portion side of the floating gate electrode having a radius of curvature of 10 nm or more, the corner portion and And a step of forming a second impurity region on an end portion side of the floating gate electrode which is opposite to the floating gate electrode and is in contact with the tunnel insulating film.

The overlapping portion of the floating gate electrode and the first impurity region is larger than the overlapping portion of the floating gate electrode and the second impurity region.

In order to achieve the above object, in the nonvolatile semiconductor memory device of the present invention, a step of sequentially forming a tunnel insulating film, a floating gate electrode forming material, an insulating film, and a control gate electrode forming material on a semiconductor substrate. A step of forming a floating gate electrode and a control gate electrode by anisotropically etching the floating gate electrode forming material, the insulating film, and the control gate electrode forming material using a resist having a predetermined pattern as a mask; After the formation, the exposed both side surfaces of the floating gate electrode are isotropically etched by using the resist as a mask to contact the tunnel insulating film.
A step of increasing the radius of curvature of one corner portion, a step of removing the resist after isotropic etching, and a heat treatment after removing the resist so that the radius of curvature of the two corner portions of the floating gate electrode is 10 nm or more. And a step of forming a first impurity region and a second impurity region so as to define a channel region in the semiconductor substrate below the control gate electrode.

The floating gate electrode forming material is polycrystal Si doped with impurities, and the heat treatment is performed in an oxygen atmosphere to oxidize the peripheral portion of the floating gate electrode. .

Polycrystalline Si doped with impurities is used as the material for forming the floating gate electrode, and the heat treatment is performed in an oxygen atmosphere to oxidize the peripheral portion of the floating gate electrode, and then the deposited interlayer insulating film is removed. It is characterized in that it is a flattening process.

The above isotropic etching is performed with CF ₄ gas.
It is characterized by using a mixed gas with O ₂ gas.

The corner of the floating gate electrode, which is in contact with the tunnel insulating film, has a radius of curvature of 50 nm or more.

The channel region is an N-type region, the first impurity region is a source region, and the second impurity region is a drain region.

[0030]

[Function] The radius of curvature of the corners of the source region and the drain region (for convenience, referred to as the corners of the floating gate) in contact with the tunnel insulating film of the floating gate electrode with respect to the direction along the source region-drain region is 10 nm or more. Has become. When viewed three-dimensionally, this cross-sectional shape continues in a direction perpendicular to the direction along the source region-drain region at a predetermined length of the floating gate electrode.

According to this, when a voltage is applied to the floating gate electrode, the electric field applied to the corner portion of the floating gate electrode becomes smaller than in the conventional case.

Therefore, when a voltage is applied to the gate electrode of the selected memory cell at the time of writing and reading, in the non-selected memory cell on the same word line as the selected memory cell, electrons are transferred from the source region and the drain region to the floating gate electrode. Avoid injecting.

Further, the following effects can be obtained.

The capacitance due to the tunnel insulating film is C _OX , and the capacitance due to the insulating film between the floating gate electrode and the control electrode is C _OX .
_ONO, placing the floating gate electrode caused when a voltage is applied to the floating voltage applied to the gate electrode V _FG, the voltage applied to the control gate electrode and the V _CG.

From C _OX · V _FG = C _ONO (V _CG − V _FG ) V _FG = C _ONO (C _ONO + C _OX ) ⁻¹ · V _CG (where C _ONO (C _ONO + C _OX ) ⁻¹ Is defined as the coupling ratio).

In the present invention, since the radius of curvature of the corner of the floating gate electrode is increased, when a plurality of memory cells have electrons flowing into and out of the floating gate electrode, the tunnel insulating film (in the region where the electrons pass) is formed. Variations in the size of the tunnel insulation film (which determines the capacitance) are reduced. Especially,
The increase in the corner radius of curvature of the floating gate electrode on the source region side contributes to the reduction in the variation in size of the tunnel insulating film. This is because the overlap with the floating gate electrode in the source region is larger than the overlap in the drain region.

As a result, C _OX becomes uniform, so that the variation in the coupling ratio is reduced, and when the voltage applied to the control gate electrode is the same, the voltage applied to the floating gate electrode, that is, the electric field is uniform.

Therefore, batch erasing is facilitated and overerasure can be prevented.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device of the present invention will be described below with reference to the drawings.

1 (a) and 1 (b) are a schematic cross-sectional view and a magnified view of the non-volatile semiconductor memory device of the first embodiment of the present invention as seen from a line along line a-b in FIG. Is. See also Figure 2
(a) thru | or (d) are schematic sectional drawing which showed the manufacturing process of the non-volatile semiconductor memory device of the 1st Example of this invention.

As shown in FIG. 1 (a), N ^{+ is formed} on the P-type semiconductor substrate 1.
The source region 2 and the drain region 3 of the mold are
A floating gate electrode 5 is formed on the channel region 9 formed between the drain region 3 and the drain region 3 via a tunnel insulating film 4. On the floating gate electrode 5, Si
A control electrode 7 is formed via an ONO film 6 composed of an oxide film, a Si nitride film, and a Si oxide film. Then, around the floating gate electrode 5, the ONO film 6, and the control gate electrode 7,
A post oxide film (Si oxide film) 8 is formed.

In the first embodiment, as shown in FIG. 1 (b), the radius of curvature of the lower surface of the floating gate electrode 5 on the source region 2 side is about 50 nm. The thickness of the tunnel insulating film and the thickness of the post oxide film are about 10 nm, and the floating gate electrode 5 and the source region are
The overlap of 2 is about 100 to 150 nm, and the overlap with the drain region 3 is about 10 to 30 nm.

Next, a method of manufacturing the nonvolatile semiconductor memory device of this embodiment will be described.

(1) A tunnel insulating film is formed on the surface of the semiconductor substrate 1.
After forming the Si oxide film 4a as 4, the impurity-doped polycrystalline Si film 5a is formed. Then, on the polycrystalline Si film 5a,
Si oxide film / Si nitride film / Si oxide film are sequentially deposited to form ONO film 6
After forming, the polycrystalline Si film 7a doped with impurities is formed (shown in FIG. 2 (a)).

(2) Resist that has been subjected to predetermined patterning
Using the 18 as a mask, the polycrystalline Si film 5a, the ONO film 6, the polycrystalline Si film 7a
Is anisotropically etched to form the floating gate electrode 5 and the control gate electrode 7, and the resist 18 is removed (see FIG. 2 (b)).

(3) Floating gate electrode on the planned side of the source region 2
5 ・ ONO film 6 ・ Pattern the resist 18 covering the side surface of the control gate electrode 7 and the corners of the control gate electrode 7 above this side surface (see FIG. 2 (c)), and remove the polycrystalline Si films 5a and 7a. Isotropic etching is performed using an etching gas that is selectively removed, for example, a mixed gas of CF ₄ and O ₂ .

(4) The resist 18 is removed by O ₂ plasma treatment and a mixed solution of sulfuric acid and hydrogen peroxide, and then heat-treated in an oxygen atmosphere to form an oxide film 8 and then the resist 18 covering the control gate electrode 7 is masked. Impurities are implanted into the source region 2 and the drain region 3 to remove the resist 18 (FIG. 2 (d)).
(Shown). Thereafter, although not shown, an interlayer insulating film is formed, heat treatment is performed for planarization, and then a contact hole is formed and a wiring is formed, thereby forming a nonvolatile semiconductor device.

In the isotropic etching of (3), the etching gas, for example, a mixed gas of CF4 and O2 is used as a polycrystalline Si film.
It is easy to enter the interface between 5a, 7a and the ONO film 6 and the interface between the polycrystalline Si film 5a and the tunnel insulating film 4. Therefore, the polycrystalline Si films 5a, 7
At a, the interface portion is etched more than other portions, and the radius of curvature of the corner of the floating gate electrode 5 in contact with the tunnel insulating film 4 is increased. Furthermore, the peripheral portion of the floating gate electrode 5 is oxidized by the heat treatment (4) during the formation of the post oxide film 8 or the heat treatment during the formation of the post oxide film 8 and the heat treatment for planarizing the interlayer insulating film. Therefore, the corner of the floating gate electrode 5 on the source region side 2 in contact with the tunnel insulating film 4 can be rounded, and finally the radius of curvature can be reduced.
It can be 50 nm.

FIG. 3 shows the radius of curvature of the corners of the floating gate electrode on the side of the impurity region (source region 2 in this embodiment) that receives the electrons extracted from the floating gate electrode and the floating gate electrode.
5 is a diagram showing the relationship of electric fields between source regions 3. FIG. From this figure, the following two trends can be read.

(Tendency 1) If the radius of curvature of the edge of the floating gate electrode 5 is large, the electric field at the edge becomes small.

(Tendency 2) When all the memory cells are viewed, the radius of curvature of the corner of the floating gate electrode 5 always varies even though the same manufacturing process is performed. Letting ΔE be the variation of the electric field due to the variation Δr of the radius of curvature with respect to the overall average value, the greater the radius of curvature, the smaller ΔE.

Two effects obtained from these two tendencies will be described below.

First, consider the case where writing / reading is performed in a memory in which the memory cells of this embodiment are NOR-type connected.

When writing is performed, as shown in FIG. 4A, the word line 11 in which the selected memory cell 17 is present has 12V, the bit line 12 has 6.5V, the other word lines 12 and the bit line 11 have a voltage of 12V.
0V is applied to.

Therefore, a high voltage is also applied to the control gate electrode 7 of the non-selected memory cell existing on the same word line 11 as the selected memory cell 17, but in the present embodiment, due to tendency 1, the source region 2 side Since the electric field applied to the corner of the floating gate electrode 5 is small, it is possible to suppress erroneous writing in which electrons enter the floating gate electrode 5.

For reading, as shown in FIG. 4B, 5V is applied to the word line 11 in which the selected memory cell 17 exists, 1V is applied to the bit line 12, and 0V is applied to the other word lines 12 and bit lines 11. Apply.

Although the voltage is lower than that at the time of writing,
Since reading takes time, 5V is applied to the control gate electrode 7 of the non-selected memory cell existing on the same word line 11 as the selected memory cell 17 for a long time. However, in this example, the trend
Since the electric field applied to the corner of the floating gate electrode 5 on the side of the source region 2 is smaller than that of 1, the erroneous writing of electrons into the floating gate electrode 5 can be suppressed.

As is well known, as shown in FIG. 5, the current I between the source and drain after writing is higher than that in the initial state in which electrons are not injected or extracted into the floating gate electrode.
_The characteristic representing the relationship between _DS and the voltage V _CG applied to the gate electrode shifts to the right as compared to the conventional case, and the threshold voltage Vth increases and Vth
Becomes In addition, the characteristics that show the relationship between I _DS and V _CG after erasing are:
It shifts to the left, and the threshold voltage drops to Vth2.

In this embodiment, since erroneous writing at the time of writing or reading can be suppressed, the difference ΔVt between Vth1 and Vth2 can be suppressed.
can hold h.

That is, the memory state can be accurately maintained for a long period of time. Therefore, the storage characteristics can be improved as compared with the conventional case.

Second, 16 bits × L × 10 ^M words (L = 2
Consider the case where batch erasing is performed in a memory cell of ^N / 16; N, M natural number) configuration.

In erasing, as shown in the flow chart of FIG. 6, the intelligent erase system was adopted.

First, 16 memory cells on each word line are checked, the memory cells that are not in the written state are written, and after confirming that all the memory cells have been written, the addresses of the selected memory cells are sequentially set from 0 to L × 10 ^M −1. Specify up to and perform the following steps for each. A prescribed voltage is applied for 10 msec to a prescribed portion of 16 memory cells on the same word line, an erase operation is performed to pull out electrons from the floating gate electrode, and then one memory cell is read and erased until it becomes the erased state. The operation and reading are performed alternately (this series of work is called a cycle process). Then, the memory cells are checked one by one until the erase of the 16 memory cells is confirmed, and if an unerased memory cell is found, a cycle process is performed.

FIG. 7 is a diagram showing the relationship between the threshold voltage of the memory cells as viewed from the word line and the number of memory cells having the threshold voltage with respect to the result of batch erasing.

From this figure, it can be seen that the variation in the threshold voltage is reduced as compared with the conventional one, and there is no over-erasure in which the threshold voltage is 0 V or less.

The reason is that in the memory cell of this embodiment in a series of erase operations, due to tendency 1, a high electric field does not work at the corners of the floating gate electrode 5, so that excessive extraction of electrons from the floating gate electrode 5 is suppressed. Because you can.

Further, from tendency 2, in each memory cell, the variation in the electric field of each memory cell caused when a voltage is applied to the memory cell is reduced, so that the amount of electrons in the floating gate electrode 5 of each memory cell is set to the same condition. This is because the same can be controlled with.

As described above, in the ETOX type flash EEPROM, batch erasing can be performed with a small number of erasing operations, and the effect of preventing overerasing can be obtained.

Therefore, according to the present embodiment, overerasure can be prevented and the memory retention characteristic can be improved.

Next, an application example of the first embodiment will be described.

FIGS. 8A and 8B show a nonvolatile semiconductor memory device according to an application example of the first embodiment of the present invention, which is shown in FIG.
It is the schematic sectional drawing seen from the line along the ab line, and the enlarged view. 9A to 9D are schematic cross-sectional views showing the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

As shown in FIGS. 8A and 8B, in this nonvolatile semiconductor memory device, the radius of curvature of the edges on both sides of the source region 2 side and the drain region 3 side on the lower surface of the floating gate electrode 5 is , 50 nm. Further, the thickness of the tunnel insulating film 4 and the thickness of the post oxide film 8 are about 10 nm, the overlap between the floating gate electrode 5 and the source region 2 is about 100 to 150 nm, and the overlap with the drain region 3 is about 10 to 30 nm. .

The method of manufacturing the non-volatile semiconductor memory device of this embodiment is as follows.

(1) A tunnel insulating film is formed on the surface of the semiconductor substrate 1.
After forming the Si oxide film 4a as 4, the impurity-doped polycrystalline Si film 5a is formed. Then, on the polycrystalline Si film 5a,
Si oxide film / Si nitride film / Si oxide film are sequentially deposited to form ONO film 6
After forming, a polycrystalline Si film 7a doped with impurities is formed (FIG. 9A).

(2) Resist which has been subjected to predetermined patterning
With 18 as a mask, polycrystalline Si film 5a, ONO film 6, polycrystalline Si film 7a
Is anisotropically etched to form the floating gate electrode 5 and the control gate electrode 7 (shown in FIG. 9 (b)). Next, polycrystalline Si
Using an etching gas that selectively removes the films 5a and 7a,
For example, isotropic etching is performed using a mixed gas of CF ₄ and O ₂ (see FIG. 9 (c)).

(3) The resist 18 is removed by O ₂ plasma treatment and a mixed solution of sulfuric acid and hydrogen peroxide, and then heat-treated in an oxygen atmosphere to form an oxide film 8 and then the resist 18 covering the control gate electrode 7 is masked. Impurities are implanted into the source region 2 and the drain region 3 to remove the resist 18 (FIG. 9 (d)).
(Shown). Thereafter, although not shown, an interlayer insulating film is formed, heat treatment is performed for planarization, and then a contact hole is formed and a wiring is formed, thereby forming a nonvolatile semiconductor device.

(2) isotropic etching, (3) heat treatment for forming the post oxide film, or (2) isotropic etching, (3) for forming the post oxide film, and interlayer insulation By the heat treatment for flattening the film, the radius of curvature of the corner of the floating gate electrode 5 on the source region 2 side and the drain region 3 side in contact with the tunnel insulating film 4 can be processed to 50 nm.

According to this, as in the first embodiment, a high electric field is not applied to the corner of the floating gate electrode 5 on the source region 2 side, and a high electric field is not applied to the corner on the drain region 3 side. -Prevents erroneous writing when reading.

In addition to the above reason, in the present embodiment, the variation of the coupling ratio in a plurality of memory cells is further reduced as compared with the first embodiment, so that the amount of electrons in the floating gate electrode 7 can be highly controlled. .

Therefore, according to this embodiment, a highly reliable storage state can be maintained for a long time.

In the first and second embodiments, the ONO film 6 increases the capacitance between the floating gate electrode 5 and the control electrode 7, and the potential of the control gate electrode 7 is the potential of the floating gate electrode. Although it is preferable that the insulating film is easily changed, the type and the number of layers are not limited as long as they are insulating films. However, since the Si nitride film has a property of trapping electrons, the film that is in direct contact with the floating gate electrode 5 or the control gate electrode 7 may be other than the Si nitride film.

Impurities to be ion-implanted to form the source region 2 and the drain region 3 are N 2 such as P or As.
Any type impurities will do.

[0083]

Since the present invention is configured as described above, it is possible to obtain a non-volatile semiconductor memory device having improved storage reliability and improved reliability of stored information.

[Brief description of the drawings]

1A and 1B are a schematic cross-sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention and an enlarged view of a part thereof, respectively.

2A to 2D are cross-sectional views showing a manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is an impurity region for receiving electrons from the floating gate electrode.
It is a figure showing the relationship between the electric field between floating gate electrodes, and the curvature radius of the corner of the floating gate electrode which emits electrons.

4A and 4B are schematic diagrams showing a memory cell array at the time of writing / reading in a NOR type EEPROM.

FIG. 5 is a diagram showing a relationship between a source-drain current value and a gate voltage of an N-channel MOSFET.

FIG. 6 is a flowchart of an intelligent erase method.

FIG. 7 is a diagram showing the relationship between the threshold value as viewed from the word line and the number of memory cells having the threshold value in this embodiment after erasing.

8A and 8B are respectively a schematic cross-sectional view showing a nonvolatile semiconductor memory device according to an application example of the first embodiment of the present invention, and an enlarged view of a part thereof.

9A to 9D are cross-sectional views showing a manufacturing process of a nonvolatile semiconductor memory device according to an application example of the first embodiment of the present invention.

FIG. 10 is a schematic plan view showing a general configuration of a flash memory.

11 is an equivalent circuit diagram showing a schematic configuration of the memory cell array shown in FIG.

12 (a) and 12 (b) are plan views of a nonvolatile semiconductor memory device included in a conventional flash memory, respectively.
It is sectional drawing seen along the ab line.

13A to 13C are cross-sectional views showing a manufacturing process of a conventional nonvolatile semiconductor memory device.

FIG. 14 is a diagram showing a relationship between a threshold value seen from a word line and the number of memory cells of a conventional example having the threshold value after erasing.

[Explanation of symbols]

 1 substrate 2 source region 3 drain region 4 tunnel insulating film 4a Si oxide film 5 floating gate electrodes 5a, 7a polycrystalline Si film 6 ONO film 7 control gate electrode 8 post oxide film 9 channel region 10 memory cell 11 bit line 12 word line 13 Sense Amplifier 14 Input / Output Buffer 15 Electron Injection 16 Electron Extraction 17 Selected Memory Cell 18 Resist

[Procedure amendment]

[Submission date] July 25, 1995

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 8

[Correction method] Change

[Correction contents]

[Figure 8]

Claims (8)

[Claims] 1. A step of sequentially forming a tunnel insulating film, a floating gate electrode forming material, an insulating film, and a control gate electrode forming material on a semiconductor substrate, and the control gate electrode forming material and the insulating film using a patterned resist as a mask. And forming a floating gate electrode and a control gate electrode by anisotropically etching the floating gate electrode forming material, and then removing the resist, and one side surface of the floating gate electrode and the control gate electrode is A step of forming a resist on the floating gate electrode so as to expose it; isotropic etching is performed on the exposed side surface of the floating gate electrode using the resist as a mask, and the tunnel insulating film is formed at an end of the floating gate electrode. A step of increasing the radius of curvature of a corner portion contacting with, and a step of removing the resist after isotropic etching After removing the resist, heat treatment is performed to make the radius of curvature of the corner portion of the floating gate electrode 10 nm or more, and the radius of curvature is 10 nm or more so as to define a channel region in the semiconductor substrate under the control gate electrode. Forming a first impurity region on a corner portion side of the floating gate electrode, and forming a second impurity region on an end portion side of the floating gate electrode located opposite to the corner portion and in contact with the tunnel insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 2. The non-volatile semiconductor according to claim 1, wherein an overlapping portion between the floating gate electrode and the first impurity region is larger than an overlapping portion between the floating gate electrode and the second impurity region. Storage device manufacturing method. 3. A step of sequentially forming a tunnel insulating film, a floating gate electrode forming material, an insulating film, and a control gate electrode forming material on a semiconductor substrate, and the floating gate electrode forming material and the insulating film using a patterned resist as a mask. And a step of forming the floating gate electrode and the control gate electrode by anisotropically etching the control gate electrode forming material, and exposing the floating gate electrode with the resist as a mask after forming the floating gate electrode. Isotropic etching of both sides to increase the radius of curvature of the two corner portions in contact with the tunnel insulating film; after isotropic etching, the step of removing the resist; and after removing the resist, heat treatment is performed. Floating gate electrode 2
A step of setting a radius of curvature of one corner portion to 10 nm or more, and a step of forming a first impurity region and a second impurity region so as to define a channel region in the semiconductor substrate under the control gate electrode. A method for manufacturing a non-volatile semiconductor memory device, comprising: 4. The floating gate electrode forming material is polycrystal Si doped with impurities, and the heat treatment is a treatment for oxidizing the peripheral portion of the floating gate electrode by performing the heat treatment in an oxygen atmosphere. A method of manufacturing a nonvolatile semiconductor memory device according to claim 1. 5. The floating gate electrode forming material is polycrystal Si doped with impurities, and the heat treatment is performed in an oxygen atmosphere to oxidize the peripheral portion of the floating gate electrode, and then the deposited interlayer insulating film is removed. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the process is a planarization process. 6. The isotropic etching is performed with CF ₄ gas and O 2.
5. A mixed gas of ₂ gases is used.
A method for manufacturing the nonvolatile semiconductor memory device described. 7. The non-volatile semiconductor memory device according to claim 1, wherein a corner of the end of the floating gate electrode, which is in contact with the tunnel insulating film, has a radius of curvature of 50 nm or more. Method. 8. The channel region is an N-type region,
4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1 or 3, wherein the first impurity region is a source region and the second impurity region is a drain region.